[u-boot.git] / arch / arm / dts / hi3798cv200.dtsi

/*
 * DTS File for HiSilicon Hi3798cv200 SoC.
 *
 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
 *
 * Released under the GPLv2 only.
 * SPDX-License-Identifier: GPL-2.0
 */

#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>

/ {
	compatible = "hisilicon,hi3798cv200";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
		      <0x0 0xf1002000 0x0 0x100>;   /* GICC */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc@f0000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xf0000000 0x10000000>;

		crg: clock-reset-controller@8a22000 {
			compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
			reg = <0x8a22000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <2>;

			gmacphyrst: reset-controller {
				compatible = "ti,syscon-reset";
				#reset-cells = <1>;
				ti,reset-bits =
					<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
					 DEASSERT_SET|STATUS_NONE)>,
					<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
					 DEASSERT_SET|STATUS_NONE)>;
			};
		};

		sysctrl: system-controller@8000000 {
			compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
			reg = <0x8000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <2>;
		};

		perictrl: peripheral-controller@8a20000 {
			compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
				     "simple-mfd";
			reg = <0x8a20000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x8a20000 0x1000>;

			usb2_phy1: usb2-phy@120 {
				compatible = "hisilicon,hi3798cv200-usb2-phy";
				reg = <0x120 0x4>;
				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
				resets = <&crg 0xbc 4>;
				#address-cells = <1>;
				#size-cells = <0>;

				usb2_phy1_port0: phy@0 {
					reg = <0>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 8>;
				};

				usb2_phy1_port1: phy@1 {
					reg = <1>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 9>;
				};
			};

			usb2_phy2: usb2-phy@124 {
				compatible = "hisilicon,hi3798cv200-usb2-phy";
				reg = <0x124 0x4>;
				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
				resets = <&crg 0xbc 6>;
				#address-cells = <1>;
				#size-cells = <0>;

				usb2_phy2_port0: phy@0 {
					reg = <0>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 10>;
				};
			};

			combphy0: phy@850 {
				compatible = "hisilicon,hi3798cv200-combphy";
				reg = <0x850 0x8>;
				#phy-cells = <1>;
				clocks = <&crg HISTB_COMBPHY0_CLK>;
				resets = <&crg 0x188 4>;
				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
				assigned-clock-rates = <100000000>;
				hisilicon,fixed-mode = <PHY_TYPE_USB3>;
			};

			combphy1: phy@858 {
				compatible = "hisilicon,hi3798cv200-combphy";
				reg = <0x858 0x8>;
				#phy-cells = <1>;
				clocks = <&crg HISTB_COMBPHY1_CLK>;
				resets = <&crg 0x188 12>;
				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
				assigned-clock-rates = <100000000>;
				hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
			};
		};

		pmx0: pinconf@8a21000 {
			compatible = "pinconf-single";
			reg = <0x8a21000 0x180>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <7>;
			pinctrl-single,gpio-range = <
				&range 0  8 2  /* GPIO 0 */
				&range 8  1 0  /* GPIO 1 */
				&range 9  4 2
				&range 13 1 0
				&range 14 1 1
				&range 15 1 0
				&range 16 5 0  /* GPIO 2 */
				&range 21 3 1
				&range 24 4 1  /* GPIO 3 */
				&range 28 2 2
				&range 86 1 1
				&range 87 1 0
				&range 30 4 2  /* GPIO 4 */
				&range 34 3 0
				&range 37 1 2
				&range 38 3 2  /* GPIO 6 */
				&range 41 5 0
				&range 46 8 1  /* GPIO 7 */
				&range 54 8 1  /* GPIO 8 */
				&range 64 7 1  /* GPIO 9 */
				&range 71 1 0
				&range 72 6 1  /* GPIO 10 */
				&range 78 1 0
				&range 79 1 1
				&range 80 6 1  /* GPIO 11 */
				&range 70 2 1
				&range 88 8 0  /* GPIO 12 */
			>;

			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};
		};

		uart0: serial@8b00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x8b00000 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl HISTB_UART0_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart2: serial@8b02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x8b02000 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_UART2_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		i2c0: i2c@8b10000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b10000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C0_CLK>;
			status = "disabled";
		};

		i2c1: i2c@8b11000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b11000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C1_CLK>;
			status = "disabled";
		};

		i2c2: i2c@8b12000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b12000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C2_CLK>;
			status = "disabled";
		};

		i2c3: i2c@8b13000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b13000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C3_CLK>;
			status = "disabled";
		};

		i2c4: i2c@8b14000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b14000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C4_CLK>;
			status = "disabled";
		};

		spi0: spi@8b1a000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x8b1a000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			cs-gpios = <&gpio7 1 0>;
			clocks = <&crg HISTB_SPI0_CLK>;
			clock-names = "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sd0: mmc@9820000 {
			compatible = "snps,dw-mshc";
			reg = <0x9820000 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
				 <&crg HISTB_SDIO0_BIU_CLK>;
			clock-names = "ciu", "biu";
			resets = <&crg 0x9c 4>;
			reset-names = "reset";
			status = "disabled";
		};

		emmc: mmc@9830000 {
			compatible = "hisilicon,hi3798cv200-dw-mshc";
			reg = <0x9830000 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_MMC_CIU_CLK>,
				 <&crg HISTB_MMC_BIU_CLK>,
				 <&crg HISTB_MMC_SAMPLE_CLK>,
				 <&crg HISTB_MMC_DRV_CLK>;
			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
			resets = <&crg 0xa0 4>;
			reset-names = "reset";
			status = "disabled";
		};

		gpio0: gpio@8b20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b20000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 0 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio1: gpio@8b21000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b21000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <
				&pmx0 0 8 1
				&pmx0 1 9 4
				&pmx0 5 13 1
				&pmx0 6 14 1
				&pmx0 7 15 1
			>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio2: gpio@8b22000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b22000 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio3: gpio@8b23000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b23000 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <
				&pmx0 0 24 4
				&pmx0 4 28 2
				&pmx0 6 86 1
				&pmx0 7 87 1
			>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio4: gpio@8b24000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b24000 0x1000>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio5: gpio@8004000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8004000 0x1000>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio6: gpio@8b26000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b26000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio7: gpio@8b27000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b27000 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 46 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio8: gpio@8b28000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b28000 0x1000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 54 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio9: gpio@8b29000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b29000 0x1000>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio10: gpio@8b2a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2a000 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio11: gpio@8b2b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2b000 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio12: gpio@8b2c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2c000 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 88 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gmac0: ethernet@9840000 {
			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
			reg = <0x9840000 0x1000>,
			      <0x984300c 0x4>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_ETH0_MAC_CLK>,
				 <&crg HISTB_ETH0_MACIF_CLK>;
			clock-names = "mac_core", "mac_ifc";
			resets = <&crg 0xcc 8>,
				 <&crg 0xcc 10>,
				 <&gmacphyrst 0>;
			reset-names = "mac_core", "mac_ifc", "phy";
			status = "disabled";
		};

		gmac1: ethernet@9841000 {
			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
			reg = <0x9841000 0x1000>,
			      <0x9843010 0x4>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_ETH1_MAC_CLK>,
				 <&crg HISTB_ETH1_MACIF_CLK>;
			clock-names = "mac_core", "mac_ifc";
			resets = <&crg 0xcc 9>,
				 <&crg 0xcc 11>,
				 <&gmacphyrst 1>;
			reset-names = "mac_core", "mac_ifc", "phy";
			status = "disabled";
		};

		ir: ir@8001000 {
			compatible = "hisilicon,hix5hd2-ir";
			reg = <0x8001000 0x1000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl HISTB_IR_CLK>;
			status = "disabled";
		};

		pcie: pcie@9860000 {
			compatible = "hisilicon,hi3798cv200-pcie";
			reg = <0x9860000 0x1000>,
			      <0x0 0x2000>,
			      <0x2000000 0x01000000>;
			reg-names = "control", "rc-dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0 15>;
			num-lanes = <1>;
			ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
				  0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_PCIE_AUX_CLK>,
				 <&crg HISTB_PCIE_PIPE_CLK>,
				 <&crg HISTB_PCIE_SYS_CLK>,
				 <&crg HISTB_PCIE_BUS_CLK>;
			clock-names = "aux", "pipe", "sys", "bus";
			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
			reset-names = "soft", "sys", "bus";
			phys = <&combphy1 PHY_TYPE_PCIE>;
			phy-names = "phy";
			status = "disabled";
		};

		ohci: ohci@9880000 {
			compatible = "generic-ohci";
			reg = <0x9880000 0x10000>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_USB2_BUS_CLK>,
				 <&crg HISTB_USB2_12M_CLK>,
				 <&crg HISTB_USB2_48M_CLK>;
			clock-names = "bus", "clk12", "clk48";
			resets = <&crg 0xb8 12>;
			reset-names = "bus";
			phys = <&usb2_phy1_port0>;
			phy-names = "usb";
			status = "disabled";
		};

		ehci: ehci@9890000 {
			compatible = "generic-ehci";
			reg = <0x9890000 0x10000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_USB2_BUS_CLK>,
				 <&crg HISTB_USB2_PHY_CLK>,
				 <&crg HISTB_USB2_UTMI_CLK>;
			clock-names = "bus", "phy", "utmi";
			resets = <&crg 0xb8 12>,
				 <&crg 0xb8 16>,
				 <&crg 0xb8 13>;
			reset-names = "bus", "phy", "utmi";
			phys = <&usb2_phy1_port0>;
			phy-names = "usb";
			status = "disabled";
		};
	};
};
Commit	Line	Data
ccaa83f8 JRO	1	/*
	2	* DTS File for HiSilicon Hi3798cv200 SoC.
	3	*
	4	* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8eef803a SG	5	*
	6	* Released under the GPLv2 only.
	7	* SPDX-License-Identifier: GPL-2.0
ccaa83f8 JRO	8	*/
	9
	10	#include <dt-bindings/clock/histb-clock.h>
8eef803a	11	#include <dt-bindings/gpio/gpio.h>
ccaa83f8	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
8eef803a	13	#include <dt-bindings/phy/phy.h>
ccaa83f8 JRO	14	#include <dt-bindings/reset/ti-syscon.h>
	15
	16	/ {
	17	compatible = "hisilicon,hi3798cv200";
	18	interrupt-parent = <&gic>;
	19	#address-cells = <2>;
	20	#size-cells = <2>;
	21
	22	psci {
	23	compatible = "arm,psci-0.2";
	24	method = "smc";
	25	};
	26
	27	cpus {
	28	#address-cells = <2>;
	29	#size-cells = <0>;
	30
	31	cpu@0 {
	32	compatible = "arm,cortex-a53";
	33	device_type = "cpu";
	34	reg = <0x0 0x0>;
	35	enable-method = "psci";
	36	};
	37
	38	cpu@1 {
	39	compatible = "arm,cortex-a53";
	40	device_type = "cpu";
	41	reg = <0x0 0x1>;
	42	enable-method = "psci";
	43	};
	44
	45	cpu@2 {
	46	compatible = "arm,cortex-a53";
	47	device_type = "cpu";
	48	reg = <0x0 0x2>;
	49	enable-method = "psci";
	50	};
	51
	52	cpu@3 {
	53	compatible = "arm,cortex-a53";
	54	device_type = "cpu";
	55	reg = <0x0 0x3>;
	56	enable-method = "psci";
	57	};
	58	};
	59
	60	gic: interrupt-controller@f1001000 {
	61	compatible = "arm,gic-400";
	62	reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
	63	<0x0 0xf1002000 0x0 0x100>; /* GICC */
	64	#address-cells = <0>;
	65	#interrupt-cells = <3>;
	66	interrupt-controller;
	67	};
	68
	69	timer {
	70	compatible = "arm,armv8-timer";
	71	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \|
	72	IRQ_TYPE_LEVEL_LOW)>,
	73	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \|
	74	IRQ_TYPE_LEVEL_LOW)>,
	75	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \|
	76	IRQ_TYPE_LEVEL_LOW)>,
	77	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \|
78	IRQ_TYPE_LEVEL_LOW)>;
79	};
80
81	soc: soc@f0000000 {
82	compatible = "simple-bus";
83	#address-cells = <1>;
84	#size-cells = <1>;
85	ranges = <0x0 0x0 0xf0000000 0x10000000>;
86
87	crg: clock-reset-controller@8a22000 {
88	compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
89	reg = <0x8a22000 0x1000>;
90	#clock-cells = <1>;
91	#reset-cells = <2>;
92
93	gmacphyrst: reset-controller {
94	compatible = "ti,syscon-reset";
95	#reset-cells = <1>;
96	ti,reset-bits =
97	<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR \|
98	DEASSERT_SET\|STATUS_NONE)>,
99	<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR \|
100	DEASSERT_SET\|STATUS_NONE)>;
101	};
102	};
103
104	sysctrl: system-controller@8000000 {
105	compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
106	reg = <0x8000000 0x1000>;
107	#clock-cells = <1>;
108	#reset-cells = <2>;
109	};
110
8eef803a SG	111	perictrl: peripheral-controller@8a20000 {
	112	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
	113	"simple-mfd";
	114	reg = <0x8a20000 0x1000>;
	115	#address-cells = <1>;
	116	#size-cells = <1>;
	117	ranges = <0x0 0x8a20000 0x1000>;
	118
	119	usb2_phy1: usb2-phy@120 {
	120	compatible = "hisilicon,hi3798cv200-usb2-phy";
	121	reg = <0x120 0x4>;
	122	clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
	123	resets = <&crg 0xbc 4>;
	124	#address-cells = <1>;
	125	#size-cells = <0>;
	126
	127	usb2_phy1_port0: phy@0 {
	128	reg = <0>;
	129	#phy-cells = <0>;
	130	resets = <&crg 0xbc 8>;
	131	};
	132
	133	usb2_phy1_port1: phy@1 {
	134	reg = <1>;
	135	#phy-cells = <0>;
	136	resets = <&crg 0xbc 9>;
	137	};
	138	};
	139
	140	usb2_phy2: usb2-phy@124 {
	141	compatible = "hisilicon,hi3798cv200-usb2-phy";
	142	reg = <0x124 0x4>;
	143	clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
	144	resets = <&crg 0xbc 6>;
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147
	148	usb2_phy2_port0: phy@0 {
	149	reg = <0>;
	150	#phy-cells = <0>;
	151	resets = <&crg 0xbc 10>;
	152	};
	153	};
	154
	155	combphy0: phy@850 {
	156	compatible = "hisilicon,hi3798cv200-combphy";
	157	reg = <0x850 0x8>;
	158	#phy-cells = <1>;
	159	clocks = <&crg HISTB_COMBPHY0_CLK>;
	160	resets = <&crg 0x188 4>;
	161	assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
	162	assigned-clock-rates = <100000000>;
	163	hisilicon,fixed-mode = <PHY_TYPE_USB3>;
	164	};
	165
	166	combphy1: phy@858 {
	167	compatible = "hisilicon,hi3798cv200-combphy";
	168	reg = <0x858 0x8>;
	169	#phy-cells = <1>;
	170	clocks = <&crg HISTB_COMBPHY1_CLK>;
	171	resets = <&crg 0x188 12>;
	172	assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
	173	assigned-clock-rates = <100000000>;
	174	hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
175	};
176	};
177
178	pmx0: pinconf@8a21000 {
179	compatible = "pinconf-single";
180	reg = <0x8a21000 0x180>;
181	pinctrl-single,register-width = <32>;
182	pinctrl-single,function-mask = <7>;
183	pinctrl-single,gpio-range = <
184	&range 0 8 2 /* GPIO 0 */
185	&range 8 1 0 /* GPIO 1 */
186	&range 9 4 2
187	&range 13 1 0
188	&range 14 1 1
189	&range 15 1 0
190	&range 16 5 0 /* GPIO 2 */
191	&range 21 3 1
192	&range 24 4 1 /* GPIO 3 */
193	&range 28 2 2
194	&range 86 1 1
195	&range 87 1 0
196	&range 30 4 2 /* GPIO 4 */
197	&range 34 3 0
198	&range 37 1 2
199	&range 38 3 2 /* GPIO 6 */
200	&range 41 5 0
201	&range 46 8 1 /* GPIO 7 */
202	&range 54 8 1 /* GPIO 8 */
203	&range 64 7 1 /* GPIO 9 */
204	&range 71 1 0
205	&range 72 6 1 /* GPIO 10 */
206	&range 78 1 0
207	&range 79 1 1
208	&range 80 6 1 /* GPIO 11 */
209	&range 70 2 1
210	&range 88 8 0 /* GPIO 12 */
211	>;
212
213	range: gpio-range {
214	#pinctrl-single,gpio-range-cells = <3>;
215	};
216	};
217
ccaa83f8 JRO	218	uart0: serial@8b00000 {
	219	compatible = "arm,pl011", "arm,primecell";
	220	reg = <0x8b00000 0x1000>;
	221	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	222	clocks = <&sysctrl HISTB_UART0_CLK>;
	223	clock-names = "apb_pclk";
	224	status = "disabled";
	225	};
	226
	227	uart2: serial@8b02000 {
	228	compatible = "arm,pl011", "arm,primecell";
	229	reg = <0x8b02000 0x1000>;
	230	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	231	clocks = <&crg HISTB_UART2_CLK>;
	232	clock-names = "apb_pclk";
	233	status = "disabled";
	234	};
	235
	236	i2c0: i2c@8b10000 {
	237	compatible = "hisilicon,hix5hd2-i2c";
	238	reg = <0x8b10000 0x1000>;
	239	#address-cells = <1>;
	240	#size-cells = <0>;
	241	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	242	clock-frequency = <400000>;
	243	clocks = <&crg HISTB_I2C0_CLK>;
	244	status = "disabled";
	245	};
	246
	247	i2c1: i2c@8b11000 {
	248	compatible = "hisilicon,hix5hd2-i2c";
	249	reg = <0x8b11000 0x1000>;
	250	#address-cells = <1>;
	251	#size-cells = <0>;
	252	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	253	clock-frequency = <400000>;
	254	clocks = <&crg HISTB_I2C1_CLK>;
	255	status = "disabled";
	256	};
	257
	258	i2c2: i2c@8b12000 {
	259	compatible = "hisilicon,hix5hd2-i2c";
	260	reg = <0x8b12000 0x1000>;
	261	#address-cells = <1>;
	262	#size-cells = <0>;
	263	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	264	clock-frequency = <400000>;
	265	clocks = <&crg HISTB_I2C2_CLK>;
	266	status = "disabled";
	267	};
	268
	269	i2c3: i2c@8b13000 {
	270	compatible = "hisilicon,hix5hd2-i2c";
	271	reg = <0x8b13000 0x1000>;
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	275	clock-frequency = <400000>;
	276	clocks = <&crg HISTB_I2C3_CLK>;
	277	status = "disabled";
	278	};
	279
	280	i2c4: i2c@8b14000 {
	281	compatible = "hisilicon,hix5hd2-i2c";
282	reg = <0x8b14000 0x1000>;
283	#address-cells = <1>;
284	#size-cells = <0>;
285	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
286	clock-frequency = <400000>;
287	clocks = <&crg HISTB_I2C4_CLK>;
288	status = "disabled";
289	};
290
291	spi0: spi@8b1a000 {
292	compatible = "arm,pl022", "arm,primecell";
293	reg = <0x8b1a000 0x1000>;
294	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
295	num-cs = <1>;
296	cs-gpios = <&gpio7 1 0>;
297	clocks = <&crg HISTB_SPI0_CLK>;
298	clock-names = "apb_pclk";
299	#address-cells = <1>;
300	#size-cells = <0>;
301	status = "disabled";
302	};
303
8eef803a	304	sd0: mmc@9820000 {
ccaa83f8	305	compatible = "snps,dw-mshc";
8eef803a SG	306	reg = <0x9820000 0x10000>;
	307	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	308	clocks = <&crg HISTB_SDIO0_CIU_CLK>,
	309	<&crg HISTB_SDIO0_BIU_CLK>;
	310	clock-names = "ciu", "biu";
	311	resets = <&crg 0x9c 4>;
	312	reset-names = "reset";
	313	status = "disabled";
	314	};
	315
	316	emmc: mmc@9830000 {
	317	compatible = "hisilicon,hi3798cv200-dw-mshc";
ccaa83f8 JRO	318	reg = <0x9830000 0x10000>;
	319	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	320	clocks = <&crg HISTB_MMC_CIU_CLK>,
8eef803a SG	321	<&crg HISTB_MMC_BIU_CLK>,
	322	<&crg HISTB_MMC_SAMPLE_CLK>,
	323	<&crg HISTB_MMC_DRV_CLK>;
	324	clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
	325	resets = <&crg 0xa0 4>;
	326	reset-names = "reset";
	327	status = "disabled";
ccaa83f8 JRO	328	};
	329
	330	gpio0: gpio@8b20000 {
	331	compatible = "arm,pl061", "arm,primecell";
	332	reg = <0x8b20000 0x1000>;
	333	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	334	gpio-controller;
	335	#gpio-cells = <2>;
	336	interrupt-controller;
	337	#interrupt-cells = <2>;
8eef803a	338	gpio-ranges = <&pmx0 0 0 8>;
ccaa83f8 JRO	339	clocks = <&crg HISTB_APB_CLK>;
	340	clock-names = "apb_pclk";
	341	status = "disabled";
	342	};
	343
	344	gpio1: gpio@8b21000 {
	345	compatible = "arm,pl061", "arm,primecell";
	346	reg = <0x8b21000 0x1000>;
	347	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	348	gpio-controller;
	349	#gpio-cells = <2>;
	350	interrupt-controller;
	351	#interrupt-cells = <2>;
8eef803a SG	352	gpio-ranges = <
	353	&pmx0 0 8 1
	354	&pmx0 1 9 4
	355	&pmx0 5 13 1
	356	&pmx0 6 14 1
	357	&pmx0 7 15 1
	358	>;
ccaa83f8 JRO	359	clocks = <&crg HISTB_APB_CLK>;
	360	clock-names = "apb_pclk";
	361	status = "disabled";
	362	};
	363
	364	gpio2: gpio@8b22000 {
	365	compatible = "arm,pl061", "arm,primecell";
	366	reg = <0x8b22000 0x1000>;
	367	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	368	gpio-controller;
	369	#gpio-cells = <2>;
	370	interrupt-controller;
	371	#interrupt-cells = <2>;
8eef803a	372	gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
ccaa83f8 JRO	373	clocks = <&crg HISTB_APB_CLK>;
	374	clock-names = "apb_pclk";
	375	status = "disabled";
	376	};
	377
	378	gpio3: gpio@8b23000 {
	379	compatible = "arm,pl061", "arm,primecell";
	380	reg = <0x8b23000 0x1000>;
	381	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	382	gpio-controller;
	383	#gpio-cells = <2>;
	384	interrupt-controller;
	385	#interrupt-cells = <2>;
8eef803a SG	386	gpio-ranges = <
	387	&pmx0 0 24 4
	388	&pmx0 4 28 2
	389	&pmx0 6 86 1
	390	&pmx0 7 87 1
	391	>;
ccaa83f8 JRO	392	clocks = <&crg HISTB_APB_CLK>;
	393	clock-names = "apb_pclk";
	394	status = "disabled";
	395	};
	396
	397	gpio4: gpio@8b24000 {
	398	compatible = "arm,pl061", "arm,primecell";
	399	reg = <0x8b24000 0x1000>;
	400	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	401	gpio-controller;
	402	#gpio-cells = <2>;
	403	interrupt-controller;
	404	#interrupt-cells = <2>;
8eef803a	405	gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
ccaa83f8 JRO	406	clocks = <&crg HISTB_APB_CLK>;
	407	clock-names = "apb_pclk";
	408	status = "disabled";
	409	};
	410
	411	gpio5: gpio@8004000 {
	412	compatible = "arm,pl061", "arm,primecell";
	413	reg = <0x8004000 0x1000>;
	414	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	415	gpio-controller;
	416	#gpio-cells = <2>;
	417	interrupt-controller;
	418	#interrupt-cells = <2>;
	419	clocks = <&crg HISTB_APB_CLK>;
	420	clock-names = "apb_pclk";
	421	status = "disabled";
	422	};
	423
	424	gpio6: gpio@8b26000 {
	425	compatible = "arm,pl061", "arm,primecell";
	426	reg = <0x8b26000 0x1000>;
	427	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	428	gpio-controller;
	429	#gpio-cells = <2>;
	430	interrupt-controller;
	431	#interrupt-cells = <2>;
8eef803a	432	gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
ccaa83f8 JRO	433	clocks = <&crg HISTB_APB_CLK>;
	434	clock-names = "apb_pclk";
	435	status = "disabled";
	436	};
	437
	438	gpio7: gpio@8b27000 {
	439	compatible = "arm,pl061", "arm,primecell";
	440	reg = <0x8b27000 0x1000>;
	441	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	442	gpio-controller;
	443	#gpio-cells = <2>;
	444	interrupt-controller;
	445	#interrupt-cells = <2>;
8eef803a	446	gpio-ranges = <&pmx0 0 46 8>;
ccaa83f8 JRO	447	clocks = <&crg HISTB_APB_CLK>;
	448	clock-names = "apb_pclk";
	449	status = "disabled";
	450	};
	451
	452	gpio8: gpio@8b28000 {
	453	compatible = "arm,pl061", "arm,primecell";
	454	reg = <0x8b28000 0x1000>;
	455	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	456	gpio-controller;
	457	#gpio-cells = <2>;
	458	interrupt-controller;
	459	#interrupt-cells = <2>;
8eef803a	460	gpio-ranges = <&pmx0 0 54 8>;
ccaa83f8 JRO	461	clocks = <&crg HISTB_APB_CLK>;
	462	clock-names = "apb_pclk";
	463	status = "disabled";
	464	};
	465
	466	gpio9: gpio@8b29000 {
	467	compatible = "arm,pl061", "arm,primecell";
	468	reg = <0x8b29000 0x1000>;
	469	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	470	gpio-controller;
	471	#gpio-cells = <2>;
	472	interrupt-controller;
	473	#interrupt-cells = <2>;
8eef803a	474	gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
ccaa83f8 JRO	475	clocks = <&crg HISTB_APB_CLK>;
	476	clock-names = "apb_pclk";
	477	status = "disabled";
	478	};
	479
	480	gpio10: gpio@8b2a000 {
	481	compatible = "arm,pl061", "arm,primecell";
	482	reg = <0x8b2a000 0x1000>;
	483	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	484	gpio-controller;
	485	#gpio-cells = <2>;
	486	interrupt-controller;
	487	#interrupt-cells = <2>;
8eef803a	488	gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
ccaa83f8 JRO	489	clocks = <&crg HISTB_APB_CLK>;
	490	clock-names = "apb_pclk";
	491	status = "disabled";
	492	};
	493
	494	gpio11: gpio@8b2b000 {
	495	compatible = "arm,pl061", "arm,primecell";
	496	reg = <0x8b2b000 0x1000>;
	497	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	498	gpio-controller;
	499	#gpio-cells = <2>;
	500	interrupt-controller;
	501	#interrupt-cells = <2>;
8eef803a	502	gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
ccaa83f8 JRO	503	clocks = <&crg HISTB_APB_CLK>;
	504	clock-names = "apb_pclk";
	505	status = "disabled";
	506	};
	507
	508	gpio12: gpio@8b2c000 {
	509	compatible = "arm,pl061", "arm,primecell";
	510	reg = <0x8b2c000 0x1000>;
	511	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	512	gpio-controller;
	513	#gpio-cells = <2>;
	514	interrupt-controller;
	515	#interrupt-cells = <2>;
8eef803a	516	gpio-ranges = <&pmx0 0 88 8>;
ccaa83f8 JRO	517	clocks = <&crg HISTB_APB_CLK>;
	518	clock-names = "apb_pclk";
	519	status = "disabled";
	520	};
	521
	522	gmac0: ethernet@9840000 {
	523	compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
	524	reg = <0x9840000 0x1000>,
	525	<0x984300c 0x4>;
	526	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	527	clocks = <&crg HISTB_ETH0_MAC_CLK>,
	528	<&crg HISTB_ETH0_MACIF_CLK>;
	529	clock-names = "mac_core", "mac_ifc";
	530	resets = <&crg 0xcc 8>,
	531	<&crg 0xcc 10>,
	532	<&gmacphyrst 0>;
	533	reset-names = "mac_core", "mac_ifc", "phy";
	534	status = "disabled";
	535	};
	536
	537	gmac1: ethernet@9841000 {
	538	compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
	539	reg = <0x9841000 0x1000>,
	540	<0x9843010 0x4>;
	541	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	542	clocks = <&crg HISTB_ETH1_MAC_CLK>,
	543	<&crg HISTB_ETH1_MACIF_CLK>;
	544	clock-names = "mac_core", "mac_ifc";
	545	resets = <&crg 0xcc 9>,
	546	<&crg 0xcc 11>,
	547	<&gmacphyrst 1>;
	548	reset-names = "mac_core", "mac_ifc", "phy";
	549	status = "disabled";
	550	};
	551
	552	ir: ir@8001000 {
	553	compatible = "hisilicon,hix5hd2-ir";
	554	reg = <0x8001000 0x1000>;
	555	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	556	clocks = <&sysctrl HISTB_IR_CLK>;
	557	status = "disabled";
	558	};
8eef803a SG	559
	560	pcie: pcie@9860000 {
	561	compatible = "hisilicon,hi3798cv200-pcie";
	562	reg = <0x9860000 0x1000>,
	563	<0x0 0x2000>,
	564	<0x2000000 0x01000000>;
	565	reg-names = "control", "rc-dbi", "config";
	566	#address-cells = <3>;
	567	#size-cells = <2>;
	568	device_type = "pci";
	569	bus-range = <0 15>;
	570	num-lanes = <1>;
	571	ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
	572	0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
	573	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
	574	interrupt-names = "msi";
	575	#interrupt-cells = <1>;
	576	interrupt-map-mask = <0 0 0 0>;
	577	interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
	578	clocks = <&crg HISTB_PCIE_AUX_CLK>,
	579	<&crg HISTB_PCIE_PIPE_CLK>,
	580	<&crg HISTB_PCIE_SYS_CLK>,
	581	<&crg HISTB_PCIE_BUS_CLK>;
	582	clock-names = "aux", "pipe", "sys", "bus";
	583	resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
	584	reset-names = "soft", "sys", "bus";
	585	phys = <&combphy1 PHY_TYPE_PCIE>;
	586	phy-names = "phy";
	587	status = "disabled";
	588	};
	589
	590	ohci: ohci@9880000 {
	591	compatible = "generic-ohci";
	592	reg = <0x9880000 0x10000>;
	593	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	594	clocks = <&crg HISTB_USB2_BUS_CLK>,
	595	<&crg HISTB_USB2_12M_CLK>,
	596	<&crg HISTB_USB2_48M_CLK>;
	597	clock-names = "bus", "clk12", "clk48";
	598	resets = <&crg 0xb8 12>;
	599	reset-names = "bus";
	600	phys = <&usb2_phy1_port0>;
	601	phy-names = "usb";
	602	status = "disabled";
	603	};
	604
	605	ehci: ehci@9890000 {
	606	compatible = "generic-ehci";
	607	reg = <0x9890000 0x10000>;
	608	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	609	clocks = <&crg HISTB_USB2_BUS_CLK>,
	610	<&crg HISTB_USB2_PHY_CLK>,
	611	<&crg HISTB_USB2_UTMI_CLK>;
	612	clock-names = "bus", "phy", "utmi";
	613	resets = <&crg 0xb8 12>,
	614	<&crg 0xb8 16>,
	615	<&crg 0xb8 13>;
	616	reset-names = "bus", "phy", "utmi";
	617	phys = <&usb2_phy1_port0>;
	618	phy-names = "usb";
	619	status = "disabled";
	620	};
ccaa83f8 JRO	621	};
ccaa83f8 JRO	622	};