[u-boot.git] / drivers / serial / lpc32xx_hsuart.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2011-2015 Vladimir Zapolskiy <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <serial.h>
#include <dm/platform_data/lpc32xx_hsuart.h>

#include <asm/arch/uart.h>
#include <linux/compiler.h>

struct lpc32xx_hsuart_priv {
	struct hsuart_regs *hsuart;
};

static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	struct hsuart_regs *hsuart = priv->hsuart;
	u32 div;

	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
	div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
	if (div > 255)
		div = 255;

	writel(div, &hsuart->rate);

	return 0;
}

static int lpc32xx_serial_getc(struct udevice *dev)
{
	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	struct hsuart_regs *hsuart = priv->hsuart;

	if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
		return -EAGAIN;

	return readl(&hsuart->rx) & HSUART_RX_DATA;
}

static int lpc32xx_serial_putc(struct udevice *dev, const char c)
{
	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	struct hsuart_regs *hsuart = priv->hsuart;

	/* Wait for empty FIFO */
	if (readl(&hsuart->level) & HSUART_LEVEL_TX)
		return -EAGAIN;

	writel(c, &hsuart->tx);

	return 0;
}

static int lpc32xx_serial_pending(struct udevice *dev, bool input)
{
	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	struct hsuart_regs *hsuart = priv->hsuart;

	if (input) {
		if (readl(&hsuart->level) & HSUART_LEVEL_RX)
			return 1;
	} else {
		if (readl(&hsuart->level) & HSUART_LEVEL_TX)
			return 1;
	}

	return 0;
}

static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
{
	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
	       &hsuart->ctrl);

	return 0;
}

static int lpc32xx_hsuart_probe(struct udevice *dev)
{
	struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);

	priv->hsuart = (struct hsuart_regs *)platdata->base;

	lpc32xx_serial_init(priv->hsuart);

	return 0;
}

static const struct dm_serial_ops lpc32xx_hsuart_ops = {
	.setbrg	= lpc32xx_serial_setbrg,
	.getc	= lpc32xx_serial_getc,
	.putc	= lpc32xx_serial_putc,
	.pending = lpc32xx_serial_pending,
};

U_BOOT_DRIVER(lpc32xx_hsuart) = {
	.name	= "lpc32xx_hsuart",
	.id	= UCLASS_SERIAL,
	.probe	= lpc32xx_hsuart_probe,
	.ops	= &lpc32xx_hsuart_ops,
	.priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
	.flags	= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
cc35fdbc	2	/*
f21069ed	3	* Copyright (C) 2011-2015 Vladimir Zapolskiy <[email protected]>
cc35fdbc VZ	4	*/
	5
	6	#include <common.h>
f21069ed	7	#include <dm.h>
e503f90a	8	#include <serial.h>
f21069ed VZ	9	#include <dm/platform_data/lpc32xx_hsuart.h>
	10
	11	#include <asm/arch/uart.h>
e503f90a	12	#include <linux/compiler.h>
cc35fdbc	13
f21069ed VZ	14	struct lpc32xx_hsuart_priv {
	15	struct hsuart_regs *hsuart;
	16	};
cc35fdbc	17
f21069ed	18	static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
cc35fdbc	19	{
f21069ed VZ	20	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
f21069ed VZ	21	struct hsuart_regs *hsuart = priv->hsuart;
cc35fdbc VZ	22	u32 div;
	23
	24	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
f21069ed	25	div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
cc35fdbc VZ	26	if (div > 255)
	27	div = 255;
	28
	29	writel(div, &hsuart->rate);
f21069ed VZ	30
f21069ed VZ	31	return 0;
cc35fdbc VZ	32	}
cc35fdbc VZ	33
f21069ed	34	static int lpc32xx_serial_getc(struct udevice *dev)
cc35fdbc	35	{
f21069ed VZ	36	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	37	struct hsuart_regs *hsuart = priv->hsuart;
	38
	39	if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
	40	return -EAGAIN;
cc35fdbc VZ	41
	42	return readl(&hsuart->rx) & HSUART_RX_DATA;
	43	}
	44
f21069ed	45	static int lpc32xx_serial_putc(struct udevice *dev, const char c)
cc35fdbc	46	{
f21069ed VZ	47	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	48	struct hsuart_regs *hsuart = priv->hsuart;
	49
	50	/* Wait for empty FIFO */
	51	if (readl(&hsuart->level) & HSUART_LEVEL_TX)
	52	return -EAGAIN;
5deccafa	53
cc35fdbc VZ	54	writel(c, &hsuart->tx);
cc35fdbc VZ	55
f21069ed	56	return 0;
cc35fdbc VZ	57	}
cc35fdbc VZ	58
f21069ed	59	static int lpc32xx_serial_pending(struct udevice *dev, bool input)
cc35fdbc	60	{
f21069ed VZ	61	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	62	struct hsuart_regs *hsuart = priv->hsuart;
	63
	64	if (input) {
	65	if (readl(&hsuart->level) & HSUART_LEVEL_RX)
	66	return 1;
	67	} else {
	68	if (readl(&hsuart->level) & HSUART_LEVEL_TX)
	69	return 1;
	70	}
cc35fdbc VZ	71
	72	return 0;
	73	}
	74
f21069ed	75	static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
cc35fdbc	76	{
cc35fdbc VZ	77	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
	78	writel(HSUART_CTRL_TMO_16 \| HSUART_CTRL_HSU_OFFSET(20) \|
	79	HSUART_CTRL_HSU_RX_TRIG_32 \| HSUART_CTRL_HSU_TX_TRIG_0,
	80	&hsuart->ctrl);
f21069ed	81
e503f90a	82	return 0;
cc35fdbc VZ	83	}
cc35fdbc VZ	84
f21069ed VZ	85	static int lpc32xx_hsuart_probe(struct udevice *dev)
	86	{
	87	struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
	88	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
	89
	90	priv->hsuart = (struct hsuart_regs *)platdata->base;
	91
	92	lpc32xx_serial_init(priv->hsuart);
	93
	94	return 0;
	95	}
	96
	97	static const struct dm_serial_ops lpc32xx_hsuart_ops = {
e503f90a	98	.setbrg = lpc32xx_serial_setbrg,
e503f90a	99	.getc = lpc32xx_serial_getc,
f21069ed VZ	100	.putc = lpc32xx_serial_putc,
f21069ed VZ	101	.pending = lpc32xx_serial_pending,
e503f90a MV	102	};
e503f90a MV	103
f21069ed VZ	104	U_BOOT_DRIVER(lpc32xx_hsuart) = {
	105	.name = "lpc32xx_hsuart",
	106	.id = UCLASS_SERIAL,
	107	.probe = lpc32xx_hsuart_probe,
	108	.ops = &lpc32xx_hsuart_ops,
	109	.priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
	110	.flags = DM_FLAG_PRE_RELOC,
	111	};