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875c7893 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, [email protected]. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
875c7893 WD |
6 | */ |
7 | ||
8 | #ifndef _SPARTAN3_H_ | |
9 | #define _SPARTAN3_H_ | |
10 | ||
11 | #include <xilinx.h> | |
12 | ||
875c7893 WD |
13 | /* Slave Parallel Implementation function table */ |
14 | typedef struct { | |
2df9d5c4 MS |
15 | xilinx_pre_fn pre; |
16 | xilinx_pgm_fn pgm; | |
17 | xilinx_init_fn init; | |
18 | xilinx_err_fn err; | |
19 | xilinx_done_fn done; | |
20 | xilinx_clk_fn clk; | |
21 | xilinx_cs_fn cs; | |
22 | xilinx_wr_fn wr; | |
23 | xilinx_rdata_fn rdata; | |
24 | xilinx_wdata_fn wdata; | |
25 | xilinx_busy_fn busy; | |
26 | xilinx_abort_fn abort; | |
27 | xilinx_post_fn post; | |
2a6e3869 | 28 | } xilinx_spartan3_slave_parallel_fns; |
875c7893 WD |
29 | |
30 | /* Slave Serial Implementation function table */ | |
31 | typedef struct { | |
2df9d5c4 MS |
32 | xilinx_pre_fn pre; |
33 | xilinx_pgm_fn pgm; | |
34 | xilinx_clk_fn clk; | |
35 | xilinx_init_fn init; | |
36 | xilinx_done_fn done; | |
37 | xilinx_wr_fn wr; | |
38 | xilinx_post_fn post; | |
39 | xilinx_bwr_fn bwr; /* block write function */ | |
40 | xilinx_abort_fn abort; | |
2a6e3869 | 41 | } xilinx_spartan3_slave_serial_fns; |
875c7893 | 42 | |
a99a06cb | 43 | #if defined(CONFIG_FPGA_SPARTAN3) |
14cfc4f3 | 44 | extern struct xilinx_fpga_op spartan3_op; |
a99a06cb MS |
45 | # define FPGA_SPARTAN3_OPS &spartan3_op |
46 | #else | |
47 | # define FPGA_SPARTAN3_OPS NULL | |
48 | #endif | |
14cfc4f3 | 49 | |
875c7893 WD |
50 | /* Device Image Sizes |
51 | *********************************************************************/ | |
52 | /* Spartan-III (1.2V) */ | |
53677ef1 WD |
53 | #define XILINX_XC3S50_SIZE 439264/8 |
54 | #define XILINX_XC3S200_SIZE 1047616/8 | |
55 | #define XILINX_XC3S400_SIZE 1699136/8 | |
56 | #define XILINX_XC3S1000_SIZE 3223488/8 | |
57 | #define XILINX_XC3S1500_SIZE 5214784/8 | |
58 | #define XILINX_XC3S2000_SIZE 7673024/8 | |
59 | #define XILINX_XC3S4000_SIZE 11316864/8 | |
60 | #define XILINX_XC3S5000_SIZE 13271936/8 | |
875c7893 | 61 | |
923efd28 BA |
62 | /* Spartan-3E (v3.4) */ |
63 | #define XILINX_XC3S100E_SIZE 581344/8 | |
64 | #define XILINX_XC3S250E_SIZE 1353728/8 | |
65 | #define XILINX_XC3S500E_SIZE 2270208/8 | |
66 | #define XILINX_XC3S1200E_SIZE 3841184/8 | |
67 | #define XILINX_XC3S1600E_SIZE 5969696/8 | |
68 | ||
28cdc1c8 SB |
69 | /* |
70 | * Spartan-6 : the Spartan-6 family can be programmed | |
71 | * exactly as the Spartan-3 | |
72 | */ | |
73 | #define XILINK_XC6SLX4_SIZE (3713568/8) | |
74 | ||
875c7893 WD |
75 | /* Descriptor Macros |
76 | *********************************************************************/ | |
3bff4ffa | 77 | /* Spartan-III devices */ |
875c7893 | 78 | #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ |
a99a06cb MS |
79 | { xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \ |
80 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
81 | |
82 | #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
83 | { xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \ |
84 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
85 | |
86 | #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
87 | { xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \ |
88 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
89 | |
90 | #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
91 | { xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \ |
92 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
93 | |
94 | #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
95 | { xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \ |
96 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
97 | |
98 | #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
99 | { xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \ |
100 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
101 | |
102 | #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
103 | { xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \ |
104 | FPGA_SPARTAN3_OPS } | |
875c7893 WD |
105 | |
106 | #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
107 | { xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \ |
108 | FPGA_SPARTAN3_OPS } | |
875c7893 | 109 | |
923efd28 BA |
110 | /* Spartan-3E devices */ |
111 | #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
112 | { xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \ |
113 | FPGA_SPARTAN3_OPS } | |
923efd28 BA |
114 | |
115 | #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
116 | { xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \ |
117 | FPGA_SPARTAN3_OPS } | |
923efd28 BA |
118 | |
119 | #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ | |
a99a06cb MS |
120 | { xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \ |
121 | FPGA_SPARTAN3_OPS } | |
923efd28 BA |
122 | |
123 | #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ | |
14cfc4f3 | 124 | { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ |
a99a06cb | 125 | FPGA_SPARTAN3_OPS } |
923efd28 BA |
126 | |
127 | #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ | |
14cfc4f3 | 128 | { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ |
a99a06cb | 129 | FPGA_SPARTAN3_OPS } |
923efd28 | 130 | |
28cdc1c8 | 131 | #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ |
a99a06cb MS |
132 | { xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \ |
133 | FPGA_SPARTAN3_OPS } | |
28cdc1c8 | 134 | |
875c7893 | 135 | #endif /* _SPARTAN3_H_ */ |