[u-boot.git] / drivers / video / sunxi / sunxi_dw_hdmi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Allwinner DW HDMI bridge
 *
 * (C) Copyright 2017 Jernej Skrabec <[email protected]>
 */

#include <common.h>
#include <display.h>
#include <dm.h>
#include <dw_hdmi.h>
#include <edid.h>
#include <log.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
#include <linux/bitops.h>
#include <linux/delay.h>

struct sunxi_dw_hdmi_priv {
	struct dw_hdmi hdmi;
	int mux;
};

struct sunxi_hdmi_phy {
	u32 pol;
	u32 res1[3];
	u32 read_en;
	u32 unscramble;
	u32 res2[2];
	u32 ctrl;
	u32 unk1;
	u32 unk2;
	u32 pll;
	u32 clk;
	u32 unk3;
	u32 status;
};

#define HDMI_PHY_OFFS 0x10000

static int sunxi_dw_hdmi_get_divider(uint clock)
{
	/*
	 * Due to missing documentaion of HDMI PHY, we know correct
	 * settings only for following four PHY dividers. Select one
	 * based on clock speed.
	 */
	if (clock <= 27000000)
		return 11;
	else if (clock <= 74250000)
		return 4;
	else if (clock <= 148500000)
		return 2;
	else
		return 1;
}

static void sunxi_dw_hdmi_phy_init(void)
{
	struct sunxi_hdmi_phy * const phy =
		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	unsigned long tmo;
	u32 tmp;

	/*
	 * HDMI PHY settings are taken as-is from Allwinner BSP code.
	 * There is no documentation.
	 */
	writel(0, &phy->ctrl);
	setbits_le32(&phy->ctrl, BIT(0));
	udelay(5);
	setbits_le32(&phy->ctrl, BIT(16));
	setbits_le32(&phy->ctrl, BIT(1));
	udelay(10);
	setbits_le32(&phy->ctrl, BIT(2));
	udelay(5);
	setbits_le32(&phy->ctrl, BIT(3));
	udelay(40);
	setbits_le32(&phy->ctrl, BIT(19));
	udelay(100);
	setbits_le32(&phy->ctrl, BIT(18));
	setbits_le32(&phy->ctrl, 7 << 4);

	/* Note that Allwinner code doesn't fail in case of timeout */
	tmo = timer_get_us() + 2000;
	while ((readl(&phy->status) & 0x80) == 0) {
		if (timer_get_us() > tmo) {
			printf("Warning: HDMI PHY init timeout!\n");
			break;
		}
	}

	setbits_le32(&phy->ctrl, 0xf << 8);
	setbits_le32(&phy->ctrl, BIT(7));

	writel(0x39dc5040, &phy->pll);
	writel(0x80084343, &phy->clk);
	udelay(10000);
	writel(1, &phy->unk3);
	setbits_le32(&phy->pll, BIT(25));
	udelay(100000);
	tmp = (readl(&phy->status) & 0x1f800) >> 11;
	setbits_le32(&phy->pll, BIT(31) | BIT(30));
	setbits_le32(&phy->pll, tmp);
	writel(0x01FF0F7F, &phy->ctrl);
	writel(0x80639000, &phy->unk1);
	writel(0x0F81C405, &phy->unk2);

	/* enable read access to HDMI controller */
	writel(0x54524545, &phy->read_en);
	/* descramble register offsets */
	writel(0x42494E47, &phy->unscramble);
}

static int sunxi_dw_hdmi_get_plug_in_status(void)
{
	struct sunxi_hdmi_phy * const phy =
		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);

	return !!(readl(&phy->status) & (1 << 19));
}

static int sunxi_dw_hdmi_wait_for_hpd(void)
{
	ulong start;

	start = get_timer(0);
	do {
		if (sunxi_dw_hdmi_get_plug_in_status())
			return 0;
		udelay(100);
	} while (get_timer(start) < 300);

	return -1;
}

static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
{
	struct sunxi_hdmi_phy * const phy =
		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	int div = sunxi_dw_hdmi_get_divider(clock);
	u32 tmp;

	/*
	 * Unfortunately, we don't know much about those magic
	 * numbers. They are taken from Allwinner BSP driver.
	 */
	switch (div) {
	case 1:
		writel(0x30dc5fc0, &phy->pll);
		writel(0x800863C0 | (phy_div - 1), &phy->clk);
		mdelay(10);
		writel(0x00000001, &phy->unk3);
		setbits_le32(&phy->pll, BIT(25));
		mdelay(200);
		tmp = (readl(&phy->status) & 0x1f800) >> 11;
		setbits_le32(&phy->pll, BIT(31) | BIT(30));
		if (tmp < 0x3d)
			setbits_le32(&phy->pll, tmp + 2);
		else
			setbits_le32(&phy->pll, 0x3f);
		mdelay(100);
		writel(0x01FFFF7F, &phy->ctrl);
		writel(0x8063b000, &phy->unk1);
		writel(0x0F8246B5, &phy->unk2);
		break;
	case 2:
		writel(0x39dc5040, &phy->pll);
		writel(0x80084380 | (phy_div - 1), &phy->clk);
		mdelay(10);
		writel(0x00000001, &phy->unk3);
		setbits_le32(&phy->pll, BIT(25));
		mdelay(100);
		tmp = (readl(&phy->status) & 0x1f800) >> 11;
		setbits_le32(&phy->pll, BIT(31) | BIT(30));
		setbits_le32(&phy->pll, tmp);
		writel(0x01FFFF7F, &phy->ctrl);
		writel(0x8063a800, &phy->unk1);
		writel(0x0F81C485, &phy->unk2);
		break;
	case 4:
		writel(0x39dc5040, &phy->pll);
		writel(0x80084340 | (phy_div - 1), &phy->clk);
		mdelay(10);
		writel(0x00000001, &phy->unk3);
		setbits_le32(&phy->pll, BIT(25));
		mdelay(100);
		tmp = (readl(&phy->status) & 0x1f800) >> 11;
		setbits_le32(&phy->pll, BIT(31) | BIT(30));
		setbits_le32(&phy->pll, tmp);
		writel(0x01FFFF7F, &phy->ctrl);
		writel(0x8063b000, &phy->unk1);
		writel(0x0F81C405, &phy->unk2);
		break;
	case 11:
		writel(0x39dc5040, &phy->pll);
		writel(0x80084300 | (phy_div - 1), &phy->clk);
		mdelay(10);
		writel(0x00000001, &phy->unk3);
		setbits_le32(&phy->pll, BIT(25));
		mdelay(100);
		tmp = (readl(&phy->status) & 0x1f800) >> 11;
		setbits_le32(&phy->pll, BIT(31) | BIT(30));
		setbits_le32(&phy->pll, tmp);
		writel(0x01FFFF7F, &phy->ctrl);
		writel(0x8063b000, &phy->unk1);
		writel(0x0F81C405, &phy->unk2);
		break;
	}
}

static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
{
	int value, n, m, div, diff;
	int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;

	/*
	 * Find the lowest divider resulting in a matching clock. If there
	 * is no match, pick the closest lower clock, as monitors tend to
	 * not sync to higher frequencies.
	 */
	for (div = 1; div <= 16; div++) {
		int target = clk_khz * div;

		if (target < 192000)
			continue;
		if (target > 912000)
			continue;

		for (m = 1; m <= 16; m++) {
			n = (m * target) / 24000;

			if (n >= 1 && n <= 128) {
				value = (24000 * n) / m / div;
				diff = clk_khz - value;
				if (diff < best_diff) {
					best_diff = diff;
					best_m = m;
					best_n = n;
					best_div = div;
				}
			}
		}
	}

	*phy_div = best_div;

	clock_set_pll3_factors(best_m, best_n);
	debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
	      clk_khz, (clock_get_pll3() / 1000) / best_div,
	      best_n, best_m, best_div);
}

static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
				    int bpp)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
	struct sunxi_lcdc_reg *lcdc;

	if (mux == 0) {
		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;

		/* Reset off */
		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);

		/* Clock on */
		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
		writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
		       &ccm->lcd0_clk_cfg);
	} else {
		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;

		/* Reset off */
		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);

		/* Clock on */
		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
		writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
		       &ccm->lcd1_clk_cfg);
	}

	lcdc_init(lcdc);
	lcdc_tcon1_mode_set(lcdc, edid, false, false);
	lcdc_enable(lcdc, bpp);
}

static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
{
	int phy_div;

	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);

	return 0;
}

static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
{
	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);

	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
}

static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
				const struct display_timing *edid)
{
	struct sunxi_hdmi_phy * const phy =
		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
	int ret;

	ret = dw_hdmi_enable(&priv->hdmi, edid);
	if (ret)
		return ret;

	sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);

	if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
		setbits_le32(&phy->pol, 0x200);

	if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
		setbits_le32(&phy->pol, 0x100);

	setbits_le32(&phy->ctrl, 0xf << 12);

	/*
	 * This is last hdmi access before boot, so scramble addresses
	 * again or othwerwise BSP driver won't work. Dummy read is
	 * needed or otherwise last write doesn't get written correctly.
	 */
	(void)readb(SUNXI_HDMI_BASE);
	writel(0, &phy->unscramble);

	return 0;
}

static int sunxi_dw_hdmi_probe(struct udevice *dev)
{
	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int ret;

	/* Set pll3 to 297 MHz */
	clock_set_pll3(297000000);

	/* Set hdmi parent to pll3 */
	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
			CCM_HDMI_CTRL_PLL3);

	/* Set ahb gating to pass */
	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);

	/* Clock on */
	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);

	sunxi_dw_hdmi_phy_init();

	ret = sunxi_dw_hdmi_wait_for_hpd();
	if (ret < 0) {
		debug("hdmi can not get hpd signal\n");
		return -1;
	}

	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
	priv->hdmi.i2c_clk_high = 0xd8;
	priv->hdmi.i2c_clk_low = 0xfe;
	priv->hdmi.reg_io_width = 1;
	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
	priv->mux = uc_plat->source_id;

	uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
				     &priv->hdmi.ddc_bus);

	dw_hdmi_init(&priv->hdmi);

	return 0;
}

static const struct dm_display_ops sunxi_dw_hdmi_ops = {
	.read_edid = sunxi_dw_hdmi_read_edid,
	.enable = sunxi_dw_hdmi_enable,
};

U_BOOT_DRIVER(sunxi_dw_hdmi) = {
	.name	= "sunxi_dw_hdmi",
	.id	= UCLASS_DISPLAY,
	.ops	= &sunxi_dw_hdmi_ops,
	.probe	= sunxi_dw_hdmi_probe,
	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
};

U_BOOT_DEVICE(sunxi_dw_hdmi) = {
	.name = "sunxi_dw_hdmi"
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
56009451 JS	2	/*
	3	* Allwinner DW HDMI bridge
	4	*
	5	* (C) Copyright 2017 Jernej Skrabec <[email protected]>
56009451 JS	6	*/
	7
	8	#include <common.h>
	9	#include <display.h>
	10	#include <dm.h>
	11	#include <dw_hdmi.h>
	12	#include <edid.h>
f7ae49fc	13	#include <log.h>
1045315d	14	#include <time.h>
56009451 JS	15	#include <asm/io.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/lcdc.h>
cd93d625	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
56009451 JS	20
	21	struct sunxi_dw_hdmi_priv {
	22	struct dw_hdmi hdmi;
	23	int mux;
	24	};
	25
	26	struct sunxi_hdmi_phy {
	27	u32 pol;
	28	u32 res1[3];
	29	u32 read_en;
	30	u32 unscramble;
	31	u32 res2[2];
	32	u32 ctrl;
	33	u32 unk1;
	34	u32 unk2;
	35	u32 pll;
	36	u32 clk;
	37	u32 unk3;
	38	u32 status;
	39	};
	40
	41	#define HDMI_PHY_OFFS 0x10000
	42
	43	static int sunxi_dw_hdmi_get_divider(uint clock)
	44	{
	45	/*
	46	* Due to missing documentaion of HDMI PHY, we know correct
	47	* settings only for following four PHY dividers. Select one
	48	* based on clock speed.
	49	*/
	50	if (clock <= 27000000)
	51	return 11;
	52	else if (clock <= 74250000)
	53	return 4;
	54	else if (clock <= 148500000)
	55	return 2;
	56	else
	57	return 1;
	58	}
	59
	60	static void sunxi_dw_hdmi_phy_init(void)
	61	{
	62	struct sunxi_hdmi_phy * const phy =
	63	(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	64	unsigned long tmo;
	65	u32 tmp;
	66
	67	/*
	68	* HDMI PHY settings are taken as-is from Allwinner BSP code.
	69	* There is no documentation.
	70	*/
	71	writel(0, &phy->ctrl);
	72	setbits_le32(&phy->ctrl, BIT(0));
	73	udelay(5);
	74	setbits_le32(&phy->ctrl, BIT(16));
	75	setbits_le32(&phy->ctrl, BIT(1));
	76	udelay(10);
	77	setbits_le32(&phy->ctrl, BIT(2));
	78	udelay(5);
	79	setbits_le32(&phy->ctrl, BIT(3));
	80	udelay(40);
	81	setbits_le32(&phy->ctrl, BIT(19));
	82	udelay(100);
	83	setbits_le32(&phy->ctrl, BIT(18));
84	setbits_le32(&phy->ctrl, 7 << 4);
85
86	/* Note that Allwinner code doesn't fail in case of timeout */
87	tmo = timer_get_us() + 2000;
88	while ((readl(&phy->status) & 0x80) == 0) {
89	if (timer_get_us() > tmo) {
90	printf("Warning: HDMI PHY init timeout!\n");
91	break;
92	}
93	}
94
95	setbits_le32(&phy->ctrl, 0xf << 8);
96	setbits_le32(&phy->ctrl, BIT(7));
97
98	writel(0x39dc5040, &phy->pll);
99	writel(0x80084343, &phy->clk);
100	udelay(10000);
101	writel(1, &phy->unk3);
102	setbits_le32(&phy->pll, BIT(25));
103	udelay(100000);
104	tmp = (readl(&phy->status) & 0x1f800) >> 11;
105	setbits_le32(&phy->pll, BIT(31) \| BIT(30));
106	setbits_le32(&phy->pll, tmp);
107	writel(0x01FF0F7F, &phy->ctrl);
108	writel(0x80639000, &phy->unk1);
109	writel(0x0F81C405, &phy->unk2);
110
111	/* enable read access to HDMI controller */
112	writel(0x54524545, &phy->read_en);
113	/* descramble register offsets */
114	writel(0x42494E47, &phy->unscramble);
115	}
116
117	static int sunxi_dw_hdmi_get_plug_in_status(void)
118	{
119	struct sunxi_hdmi_phy * const phy =
120	(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
121
122	return !!(readl(&phy->status) & (1 << 19));
123	}
124
125	static int sunxi_dw_hdmi_wait_for_hpd(void)
126	{
127	ulong start;
128
129	start = get_timer(0);
130	do {
131	if (sunxi_dw_hdmi_get_plug_in_status())
132	return 0;
133	udelay(100);
134	} while (get_timer(start) < 300);
135
136	return -1;
137	}
138
1feed358	139	static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
56009451 JS	140	{
	141	struct sunxi_hdmi_phy * const phy =
	142	(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	143	int div = sunxi_dw_hdmi_get_divider(clock);
	144	u32 tmp;
	145
	146	/*
	147	* Unfortunately, we don't know much about those magic
	148	* numbers. They are taken from Allwinner BSP driver.
	149	*/
	150	switch (div) {
	151	case 1:
	152	writel(0x30dc5fc0, &phy->pll);
1feed358	153	writel(0x800863C0 \| (phy_div - 1), &phy->clk);
56009451 JS	154	mdelay(10);
	155	writel(0x00000001, &phy->unk3);
	156	setbits_le32(&phy->pll, BIT(25));
	157	mdelay(200);
	158	tmp = (readl(&phy->status) & 0x1f800) >> 11;
	159	setbits_le32(&phy->pll, BIT(31) \| BIT(30));
	160	if (tmp < 0x3d)
	161	setbits_le32(&phy->pll, tmp + 2);
	162	else
	163	setbits_le32(&phy->pll, 0x3f);
	164	mdelay(100);
	165	writel(0x01FFFF7F, &phy->ctrl);
	166	writel(0x8063b000, &phy->unk1);
	167	writel(0x0F8246B5, &phy->unk2);
	168	break;
	169	case 2:
	170	writel(0x39dc5040, &phy->pll);
1feed358	171	writel(0x80084380 \| (phy_div - 1), &phy->clk);
56009451 JS	172	mdelay(10);
	173	writel(0x00000001, &phy->unk3);
	174	setbits_le32(&phy->pll, BIT(25));
	175	mdelay(100);
	176	tmp = (readl(&phy->status) & 0x1f800) >> 11;
	177	setbits_le32(&phy->pll, BIT(31) \| BIT(30));
	178	setbits_le32(&phy->pll, tmp);
	179	writel(0x01FFFF7F, &phy->ctrl);
	180	writel(0x8063a800, &phy->unk1);
	181	writel(0x0F81C485, &phy->unk2);
	182	break;
	183	case 4:
	184	writel(0x39dc5040, &phy->pll);
1feed358	185	writel(0x80084340 \| (phy_div - 1), &phy->clk);
56009451 JS	186	mdelay(10);
	187	writel(0x00000001, &phy->unk3);
	188	setbits_le32(&phy->pll, BIT(25));
	189	mdelay(100);
	190	tmp = (readl(&phy->status) & 0x1f800) >> 11;
	191	setbits_le32(&phy->pll, BIT(31) \| BIT(30));
	192	setbits_le32(&phy->pll, tmp);
	193	writel(0x01FFFF7F, &phy->ctrl);
	194	writel(0x8063b000, &phy->unk1);
	195	writel(0x0F81C405, &phy->unk2);
	196	break;
	197	case 11:
	198	writel(0x39dc5040, &phy->pll);
1feed358	199	writel(0x80084300 \| (phy_div - 1), &phy->clk);
56009451 JS	200	mdelay(10);
	201	writel(0x00000001, &phy->unk3);
	202	setbits_le32(&phy->pll, BIT(25));
	203	mdelay(100);
	204	tmp = (readl(&phy->status) & 0x1f800) >> 11;
	205	setbits_le32(&phy->pll, BIT(31) \| BIT(30));
	206	setbits_le32(&phy->pll, tmp);
	207	writel(0x01FFFF7F, &phy->ctrl);
	208	writel(0x8063b000, &phy->unk1);
	209	writel(0x0F81C405, &phy->unk2);
	210	break;
	211	}
	212	}
	213
1feed358	214	static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
56009451	215	{
1feed358 JS	216	int value, n, m, div, diff;
1feed358 JS	217	int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
56009451 JS	218
	219	/*
	220	* Find the lowest divider resulting in a matching clock. If there
	221	* is no match, pick the closest lower clock, as monitors tend to
	222	* not sync to higher frequencies.
	223	*/
1feed358 JS	224	for (div = 1; div <= 16; div++) {
	225	int target = clk_khz * div;
	226
	227	if (target < 192000)
	228	continue;
	229	if (target > 912000)
	230	continue;
	231
	232	for (m = 1; m <= 16; m++) {
	233	n = (m * target) / 24000;
	234
	235	if (n >= 1 && n <= 128) {
	236	value = (24000 * n) / m / div;
	237	diff = clk_khz - value;
	238	if (diff < best_diff) {
	239	best_diff = diff;
	240	best_m = m;
	241	best_n = n;
	242	best_div = div;
	243	}
56009451 JS	244	}
	245	}
	246	}
	247
1feed358 JS	248	*phy_div = best_div;
1feed358 JS	249
56009451 JS	250	clock_set_pll3_factors(best_m, best_n);
56009451 JS	251	debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
1feed358 JS	252	clk_khz, (clock_get_pll3() / 1000) / best_div,
1feed358 JS	253	best_n, best_m, best_div);
56009451 JS	254	}
	255
	256	static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
	257	int bpp)
	258	{
	259	struct sunxi_ccm_reg * const ccm =
	260	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
f34e7fc2	261	int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
56009451 JS	262	struct sunxi_lcdc_reg *lcdc;
	263
	264	if (mux == 0) {
	265	lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
	266
	267	/* Reset off */
	268	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
	269
	270	/* Clock on */
	271	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
	272	writel(CCM_LCD0_CTRL_GATE \| CCM_LCD0_CTRL_M(div),
	273	&ccm->lcd0_clk_cfg);
	274	} else {
	275	lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
	276
	277	/* Reset off */
	278	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
	279
	280	/* Clock on */
	281	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
	282	writel(CCM_LCD1_CTRL_GATE \| CCM_LCD1_CTRL_M(div),
	283	&ccm->lcd1_clk_cfg);
	284	}
	285
	286	lcdc_init(lcdc);
	287	lcdc_tcon1_mode_set(lcdc, edid, false, false);
	288	lcdc_enable(lcdc, bpp);
	289	}
	290
	291	static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
	292	{
1feed358 JS	293	int phy_div;
	294
	295	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
	296	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
56009451 JS	297
	298	return 0;
	299	}
	300
	301	static int sunxi_dw_hdmi_read_edid(struct udevice dev, u8 buf, int buf_size)
	302	{
	303	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
	304
	305	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
	306	}
	307
	308	static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
	309	const struct display_timing *edid)
	310	{
	311	struct sunxi_hdmi_phy * const phy =
	312	(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
	313	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
	314	int ret;
	315
	316	ret = dw_hdmi_enable(&priv->hdmi, edid);
	317	if (ret)
	318	return ret;
	319
	320	sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
	321
c7cb17e8	322	if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
64089178 VK	323	setbits_le32(&phy->pol, 0x200);
64089178 VK	324
c7cb17e8	325	if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
64089178	326	setbits_le32(&phy->pol, 0x100);
56009451 JS	327
	328	setbits_le32(&phy->ctrl, 0xf << 12);
	329
	330	/*
	331	* This is last hdmi access before boot, so scramble addresses
	332	* again or othwerwise BSP driver won't work. Dummy read is
	333	* needed or otherwise last write doesn't get written correctly.
	334	*/
	335	(void)readb(SUNXI_HDMI_BASE);
	336	writel(0, &phy->unscramble);
	337
	338	return 0;
	339	}
	340
	341	static int sunxi_dw_hdmi_probe(struct udevice *dev)
	342	{
	343	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
	344	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
	345	struct sunxi_ccm_reg * const ccm =
	346	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	347	int ret;
	348
	349	/* Set pll3 to 297 MHz */
	350	clock_set_pll3(297000000);
	351
	352	/* Set hdmi parent to pll3 */
	353	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
	354	CCM_HDMI_CTRL_PLL3);
	355
	356	/* Set ahb gating to pass */
	357	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
	358	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
	359	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
	360	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
	361
	362	/* Clock on */
	363	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
	364
	365	sunxi_dw_hdmi_phy_init();
	366
	367	ret = sunxi_dw_hdmi_wait_for_hpd();
	368	if (ret < 0) {
	369	debug("hdmi can not get hpd signal\n");
	370	return -1;
	371	}
	372
	373	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
	374	priv->hdmi.i2c_clk_high = 0xd8;
	375	priv->hdmi.i2c_clk_low = 0xfe;
	376	priv->hdmi.reg_io_width = 1;
	377	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
	378	priv->mux = uc_plat->source_id;
	379
60a62acf NS	380	uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
	381	&priv->hdmi.ddc_bus);
	382
56009451 JS	383	dw_hdmi_init(&priv->hdmi);
	384
	385	return 0;
	386	}
	387
	388	static const struct dm_display_ops sunxi_dw_hdmi_ops = {
	389	.read_edid = sunxi_dw_hdmi_read_edid,
	390	.enable = sunxi_dw_hdmi_enable,
	391	};
	392
	393	U_BOOT_DRIVER(sunxi_dw_hdmi) = {
	394	.name = "sunxi_dw_hdmi",
	395	.id = UCLASS_DISPLAY,
	396	.ops = &sunxi_dw_hdmi_ops,
	397	.probe = sunxi_dw_hdmi_probe,
41575d8e	398	.priv_auto = sizeof(struct sunxi_dw_hdmi_priv),
56009451 JS	399	};
	400
	401	U_BOOT_DEVICE(sunxi_dw_hdmi) = {
	402	.name = "sunxi_dw_hdmi"
	403	};