[u-boot.git] / drivers / serial / serial_bcm6345.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
 *
 * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
 *	Copyright (C) 2008 Maxime Bizon <[email protected]>
 */

#include <clk.h>
#include <dm.h>
#include <debug_uart.h>
#include <errno.h>
#include <malloc.h>
#include <serial.h>
#include <asm/io.h>
#include <asm/types.h>

/* UART Control register */
#define UART_CTL_REG			0x0
#define UART_CTL_RXTIMEOUT_MASK		0x1f
#define UART_CTL_RXTIMEOUT_5		0x5
#define UART_CTL_RSTRXFIFO_SHIFT	6
#define UART_CTL_RSTRXFIFO_MASK		(1 << UART_CTL_RSTRXFIFO_SHIFT)
#define UART_CTL_RSTTXFIFO_SHIFT	7
#define UART_CTL_RSTTXFIFO_MASK		(1 << UART_CTL_RSTTXFIFO_SHIFT)
#define UART_CTL_STOPBITS_SHIFT		8
#define UART_CTL_STOPBITS_MASK		(0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_1		(0x7 << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_BITSPERSYM_SHIFT	12
#define UART_CTL_BITSPERSYM_MASK	(0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_BITSPERSYM_8		(0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_XMITBRK_SHIFT		14
#define UART_CTL_XMITBRK_MASK		(1 << UART_CTL_XMITBRK_SHIFT)
#define UART_CTL_RSVD_SHIFT		15
#define UART_CTL_RSVD_MASK		(1 << UART_CTL_RSVD_SHIFT)
#define UART_CTL_RXPAREVEN_SHIFT	16
#define UART_CTL_RXPAREVEN_MASK		(1 << UART_CTL_RXPAREVEN_SHIFT)
#define UART_CTL_RXPAREN_SHIFT		17
#define UART_CTL_RXPAREN_MASK		(1 << UART_CTL_RXPAREN_SHIFT)
#define UART_CTL_TXPAREVEN_SHIFT	18
#define UART_CTL_TXPAREVEN_MASK		(1 << UART_CTL_TXPAREVEN_SHIFT)
#define UART_CTL_TXPAREN_SHIFT		19
#define UART_CTL_TXPAREN_MASK		(1 << UART_CTL_TXPAREN_SHIFT)
#define UART_CTL_LOOPBACK_SHIFT		20
#define UART_CTL_LOOPBACK_MASK		(1 << UART_CTL_LOOPBACK_SHIFT)
#define UART_CTL_RXEN_SHIFT		21
#define UART_CTL_RXEN_MASK		(1 << UART_CTL_RXEN_SHIFT)
#define UART_CTL_TXEN_SHIFT		22
#define UART_CTL_TXEN_MASK		(1 << UART_CTL_TXEN_SHIFT)
#define UART_CTL_BRGEN_SHIFT		23
#define UART_CTL_BRGEN_MASK		(1 << UART_CTL_BRGEN_SHIFT)

/* UART Baudword register */
#define UART_BAUD_REG			0x4

/* UART FIFO Config register */
#define UART_FIFO_CFG_REG		0x8
#define UART_FIFO_CFG_RX_SHIFT		8
#define UART_FIFO_CFG_RX_MASK		(0xf << UART_FIFO_CFG_RX_SHIFT)
#define UART_FIFO_CFG_RX_4		(0x4 << UART_FIFO_CFG_RX_SHIFT)
#define UART_FIFO_CFG_TX_SHIFT		12
#define UART_FIFO_CFG_TX_MASK		(0xf << UART_FIFO_CFG_TX_SHIFT)
#define UART_FIFO_CFG_TX_4		(0x4 << UART_FIFO_CFG_TX_SHIFT)

/* UART Interrupt register */
#define UART_IR_REG			0x10
#define UART_IR_STAT(x)			(1 << (x))
#define UART_IR_TXEMPTY			5
#define UART_IR_RXOVER			7
#define UART_IR_RXNOTEMPTY		11

/* UART FIFO register */
#define UART_FIFO_REG			0x14
#define UART_FIFO_VALID_MASK		0xff
#define UART_FIFO_FRAMEERR_SHIFT	8
#define UART_FIFO_FRAMEERR_MASK		(1 << UART_FIFO_FRAMEERR_SHIFT)
#define UART_FIFO_PARERR_SHIFT		9
#define UART_FIFO_PARERR_MASK		(1 << UART_FIFO_PARERR_SHIFT)
#define UART_FIFO_BRKDET_SHIFT		10
#define UART_FIFO_BRKDET_MASK		(1 << UART_FIFO_BRKDET_SHIFT)
#define UART_FIFO_ANYERR_MASK		(UART_FIFO_FRAMEERR_MASK |	\
					UART_FIFO_PARERR_MASK |		\
					UART_FIFO_BRKDET_MASK)

struct bcm6345_serial_priv {
	void __iomem *base;
	ulong uartclk;
};

/* enable rx & tx operation on uart */
static void bcm6345_serial_enable(void __iomem *base)
{
	setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
		   UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}

/* disable rx & tx operation on uart */
static void bcm6345_serial_disable(void __iomem *base)
{
	clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
		   UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}

/* clear all unread data in rx fifo and unsent data in tx fifo */
static void bcm6345_serial_flush(void __iomem *base)
{
	/* empty rx and tx fifo */
	setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
		   UART_CTL_RSTTXFIFO_MASK);

	/* read any pending char to make sure all irq status are cleared */
	readl(base + UART_FIFO_REG);
}

static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
{
	u32 val;

	/* mask all irq and flush port */
	bcm6345_serial_disable(base);
	bcm6345_serial_flush(base);

	/* set uart control config */
	clrsetbits_32(base + UART_CTL_REG,
		      /* clear rx timeout */
		      UART_CTL_RXTIMEOUT_MASK |
		      /* clear stop bits */
		      UART_CTL_STOPBITS_MASK |
		      /* clear bits per symbol */
		      UART_CTL_BITSPERSYM_MASK |
		      /* clear xmit break */
		      UART_CTL_XMITBRK_MASK |
		      /* clear reserved bit */
		      UART_CTL_RSVD_MASK |
		      /* disable parity */
		      UART_CTL_RXPAREN_MASK |
		      UART_CTL_TXPAREN_MASK |
		      /* disable loopback */
		      UART_CTL_LOOPBACK_MASK,
		      /* set timeout to 5 */
		      UART_CTL_RXTIMEOUT_5 |
		      /* set 8 bits/symbol */
		      UART_CTL_BITSPERSYM_8 |
		      /* set 1 stop bit */
		      UART_CTL_STOPBITS_1 |
		      /* set parity to even */
		      UART_CTL_RXPAREVEN_MASK |
		      UART_CTL_TXPAREVEN_MASK);

	/* set uart fifo config */
	clrsetbits_32(base + UART_FIFO_CFG_REG,
		      /* clear fifo config */
		      UART_FIFO_CFG_RX_MASK |
		      UART_FIFO_CFG_TX_MASK,
		      /* set fifo config to 4 */
		      UART_FIFO_CFG_RX_4 |
		      UART_FIFO_CFG_TX_4);

	/* set baud rate */
	val = ((clk / baudrate) >> 4);
	if (val & 0x1)
		val = (val >> 1);
	else
		val = (val >> 1) - 1;
	writel(val, base + UART_BAUD_REG);

	/* clear interrupts */
	writel(0, base + UART_IR_REG);

	/* enable uart */
	bcm6345_serial_enable(base);

	return 0;
}

static int bcm6345_serial_pending(struct udevice *dev, bool input)
{
	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	u32 val = readl(priv->base + UART_IR_REG);

	if (input)
		return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
	else
		return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
}

static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct bcm6345_serial_priv *priv = dev_get_priv(dev);

	return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
}

static int bcm6345_serial_putc(struct udevice *dev, const char ch)
{
	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	u32 val;

	val = readl(priv->base + UART_IR_REG);
	if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
		return -EAGAIN;

	writel(ch, priv->base + UART_FIFO_REG);

	return 0;
}

static int bcm6345_serial_getc(struct udevice *dev)
{
	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	u32 val;

	val = readl(priv->base + UART_IR_REG);
	if (val & UART_IR_STAT(UART_IR_RXOVER))
		setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK);
	if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
		return -EAGAIN;

	val = readl(priv->base + UART_FIFO_REG);
	if (val & UART_FIFO_ANYERR_MASK)
		return -EAGAIN;

	return val & UART_FIFO_VALID_MASK;
}

static int bcm6345_serial_probe(struct udevice *dev)
{
	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	struct clk clk;
	int ret;

	/* get address */
	priv->base = dev_remap_addr(dev);
	if (!priv->base)
		return -EINVAL;

	/* get clock rate */
	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;
	priv->uartclk = clk_get_rate(&clk);
	clk_free(&clk);

	/* initialize serial */
	return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
}

static const struct dm_serial_ops bcm6345_serial_ops = {
	.putc = bcm6345_serial_putc,
	.pending = bcm6345_serial_pending,
	.getc = bcm6345_serial_getc,
	.setbrg = bcm6345_serial_setbrg,
};

static const struct udevice_id bcm6345_serial_ids[] = {
	{ .compatible = "brcm,bcm6345-uart" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(bcm6345_serial) = {
	.name = "bcm6345-uart",
	.id = UCLASS_SERIAL,
	.of_match = bcm6345_serial_ids,
	.probe = bcm6345_serial_probe,
	.priv_auto	= sizeof(struct bcm6345_serial_priv),
	.ops = &bcm6345_serial_ops,
};

#ifdef CONFIG_DEBUG_UART_BCM6345
static inline void _debug_uart_init(void)
{
	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;

	bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}

static inline void wait_xfered(void __iomem *base)
{
	do {
		u32 val = readl(base + UART_IR_REG);
		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
			break;
	} while (1);
}

static inline void _debug_uart_putc(int ch)
{
	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;

	wait_xfered(base);
	writel(ch, base + UART_FIFO_REG);
	wait_xfered(base);
}

DEBUG_UART_FUNCS
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
30581040 ÁFR	2	/*
	3	* Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
	4	*
	5	* Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
	6	* Copyright (C) 2008 Maxime Bizon <[email protected]>
30581040 ÁFR	7	*/
	8
	9	#include <clk.h>
9d922450	10	#include <dm.h>
30581040 ÁFR	11	#include <debug_uart.h>
30581040 ÁFR	12	#include <errno.h>
336d4615	13	#include <malloc.h>
30581040 ÁFR	14	#include <serial.h>
	15	#include <asm/io.h>
	16	#include <asm/types.h>
30581040 ÁFR	17
	18	/* UART Control register */
	19	#define UART_CTL_REG 0x0
	20	#define UART_CTL_RXTIMEOUT_MASK 0x1f
	21	#define UART_CTL_RXTIMEOUT_5 0x5
	22	#define UART_CTL_RSTRXFIFO_SHIFT 6
	23	#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
	24	#define UART_CTL_RSTTXFIFO_SHIFT 7
	25	#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
	26	#define UART_CTL_STOPBITS_SHIFT 8
	27	#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
	28	#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
	29	#define UART_CTL_BITSPERSYM_SHIFT 12
	30	#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
	31	#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT)
	32	#define UART_CTL_XMITBRK_SHIFT 14
	33	#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
	34	#define UART_CTL_RSVD_SHIFT 15
	35	#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
	36	#define UART_CTL_RXPAREVEN_SHIFT 16
	37	#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
	38	#define UART_CTL_RXPAREN_SHIFT 17
	39	#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
	40	#define UART_CTL_TXPAREVEN_SHIFT 18
	41	#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
	42	#define UART_CTL_TXPAREN_SHIFT 19
	43	#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
	44	#define UART_CTL_LOOPBACK_SHIFT 20
	45	#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
	46	#define UART_CTL_RXEN_SHIFT 21
	47	#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
	48	#define UART_CTL_TXEN_SHIFT 22
	49	#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
	50	#define UART_CTL_BRGEN_SHIFT 23
	51	#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
	52
	53	/* UART Baudword register */
	54	#define UART_BAUD_REG 0x4
	55
	56	/* UART FIFO Config register */
	57	#define UART_FIFO_CFG_REG 0x8
	58	#define UART_FIFO_CFG_RX_SHIFT 8
	59	#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
	60	#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT)
	61	#define UART_FIFO_CFG_TX_SHIFT 12
	62	#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
	63	#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT)
	64
	65	/* UART Interrupt register */
	66	#define UART_IR_REG 0x10
	67	#define UART_IR_STAT(x) (1 << (x))
	68	#define UART_IR_TXEMPTY 5
	69	#define UART_IR_RXOVER 7
	70	#define UART_IR_RXNOTEMPTY 11
	71
	72	/* UART FIFO register */
	73	#define UART_FIFO_REG 0x14
	74	#define UART_FIFO_VALID_MASK 0xff
	75	#define UART_FIFO_FRAMEERR_SHIFT 8
	76	#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
	77	#define UART_FIFO_PARERR_SHIFT 9
	78	#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
	79	#define UART_FIFO_BRKDET_SHIFT 10
	80	#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
81	#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK \| \
82	UART_FIFO_PARERR_MASK \| \
83	UART_FIFO_BRKDET_MASK)
84
85	struct bcm6345_serial_priv {
86	void __iomem *base;
87	ulong uartclk;
88	};
89
90	/* enable rx & tx operation on uart */
91	static void bcm6345_serial_enable(void __iomem *base)
92	{
09ace916 ÁFR	93	setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK \|
09ace916 ÁFR	94	UART_CTL_TXEN_MASK \| UART_CTL_RXEN_MASK);
30581040 ÁFR	95	}
	96
	97	/* disable rx & tx operation on uart */
	98	static void bcm6345_serial_disable(void __iomem *base)
	99	{
09ace916 ÁFR	100	clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK \|
09ace916 ÁFR	101	UART_CTL_TXEN_MASK \| UART_CTL_RXEN_MASK);
30581040 ÁFR	102	}
	103
	104	/* clear all unread data in rx fifo and unsent data in tx fifo */
	105	static void bcm6345_serial_flush(void __iomem *base)
	106	{
	107	/* empty rx and tx fifo */
09ace916 ÁFR	108	setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK \|
09ace916 ÁFR	109	UART_CTL_RSTTXFIFO_MASK);
30581040 ÁFR	110
30581040 ÁFR	111	/* read any pending char to make sure all irq status are cleared */
09ace916	112	readl(base + UART_FIFO_REG);
30581040 ÁFR	113	}
	114
	115	static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
	116	{
	117	u32 val;
	118
	119	/* mask all irq and flush port */
	120	bcm6345_serial_disable(base);
	121	bcm6345_serial_flush(base);
	122
	123	/* set uart control config */
09ace916 ÁFR	124	clrsetbits_32(base + UART_CTL_REG,
	125	/* clear rx timeout */
	126	UART_CTL_RXTIMEOUT_MASK \|
	127	/* clear stop bits */
	128	UART_CTL_STOPBITS_MASK \|
	129	/* clear bits per symbol */
	130	UART_CTL_BITSPERSYM_MASK \|
	131	/* clear xmit break */
	132	UART_CTL_XMITBRK_MASK \|
	133	/* clear reserved bit */
	134	UART_CTL_RSVD_MASK \|
	135	/* disable parity */
	136	UART_CTL_RXPAREN_MASK \|
	137	UART_CTL_TXPAREN_MASK \|
	138	/* disable loopback */
	139	UART_CTL_LOOPBACK_MASK,
	140	/* set timeout to 5 */
	141	UART_CTL_RXTIMEOUT_5 \|
	142	/* set 8 bits/symbol */
	143	UART_CTL_BITSPERSYM_8 \|
	144	/* set 1 stop bit */
	145	UART_CTL_STOPBITS_1 \|
	146	/* set parity to even */
	147	UART_CTL_RXPAREVEN_MASK \|
	148	UART_CTL_TXPAREVEN_MASK);
30581040 ÁFR	149
30581040 ÁFR	150	/* set uart fifo config */
09ace916 ÁFR	151	clrsetbits_32(base + UART_FIFO_CFG_REG,
	152	/* clear fifo config */
	153	UART_FIFO_CFG_RX_MASK \|
	154	UART_FIFO_CFG_TX_MASK,
	155	/* set fifo config to 4 */
	156	UART_FIFO_CFG_RX_4 \|
	157	UART_FIFO_CFG_TX_4);
30581040 ÁFR	158
30581040 ÁFR	159	/* set baud rate */
24f85482	160	val = ((clk / baudrate) >> 4);
30581040	161	if (val & 0x1)
24f85482	162	val = (val >> 1);
30581040	163	else
24f85482	164	val = (val >> 1) - 1;
09ace916	165	writel(val, base + UART_BAUD_REG);
30581040 ÁFR	166
30581040 ÁFR	167	/* clear interrupts */
09ace916	168	writel(0, base + UART_IR_REG);
30581040 ÁFR	169
	170	/* enable uart */
	171	bcm6345_serial_enable(base);
	172
	173	return 0;
	174	}
	175
	176	static int bcm6345_serial_pending(struct udevice *dev, bool input)
	177	{
	178	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
09ace916	179	u32 val = readl(priv->base + UART_IR_REG);
30581040 ÁFR	180
	181	if (input)
	182	return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
	183	else
	184	return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
	185	}
	186
	187	static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
	188	{
	189	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	190
	191	return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
	192	}
	193
	194	static int bcm6345_serial_putc(struct udevice *dev, const char ch)
	195	{
	196	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	197	u32 val;
	198
09ace916	199	val = readl(priv->base + UART_IR_REG);
30581040 ÁFR	200	if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
	201	return -EAGAIN;
	202
09ace916	203	writel(ch, priv->base + UART_FIFO_REG);
30581040 ÁFR	204
	205	return 0;
	206	}
	207
	208	static int bcm6345_serial_getc(struct udevice *dev)
	209	{
	210	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	211	u32 val;
	212
09ace916	213	val = readl(priv->base + UART_IR_REG);
30581040	214	if (val & UART_IR_STAT(UART_IR_RXOVER))
09ace916	215	setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK);
30581040 ÁFR	216	if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
	217	return -EAGAIN;
	218
09ace916	219	val = readl(priv->base + UART_FIFO_REG);
30581040 ÁFR	220	if (val & UART_FIFO_ANYERR_MASK)
	221	return -EAGAIN;
	222
	223	return val & UART_FIFO_VALID_MASK;
	224	}
	225
	226	static int bcm6345_serial_probe(struct udevice *dev)
	227	{
	228	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
	229	struct clk clk;
30581040 ÁFR	230	int ret;
	231
	232	/* get address */
0f569937 ÁFR	233	priv->base = dev_remap_addr(dev);
0f569937 ÁFR	234	if (!priv->base)
30581040 ÁFR	235	return -EINVAL;
30581040 ÁFR	236
30581040 ÁFR	237	/* get clock rate */
	238	ret = clk_get_by_index(dev, 0, &clk);
	239	if (ret < 0)
	240	return ret;
24f85482	241	priv->uartclk = clk_get_rate(&clk);
30581040 ÁFR	242	clk_free(&clk);
	243
	244	/* initialize serial */
	245	return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
	246	}
	247
	248	static const struct dm_serial_ops bcm6345_serial_ops = {
	249	.putc = bcm6345_serial_putc,
	250	.pending = bcm6345_serial_pending,
	251	.getc = bcm6345_serial_getc,
	252	.setbrg = bcm6345_serial_setbrg,
	253	};
	254
	255	static const struct udevice_id bcm6345_serial_ids[] = {
	256	{ .compatible = "brcm,bcm6345-uart" },
	257	{ /* sentinel */ }
	258	};
	259
	260	U_BOOT_DRIVER(bcm6345_serial) = {
	261	.name = "bcm6345-uart",
	262	.id = UCLASS_SERIAL,
	263	.of_match = bcm6345_serial_ids,
	264	.probe = bcm6345_serial_probe,
41575d8e	265	.priv_auto = sizeof(struct bcm6345_serial_priv),
30581040	266	.ops = &bcm6345_serial_ops,
30581040 ÁFR	267	};
	268
	269	#ifdef CONFIG_DEBUG_UART_BCM6345
	270	static inline void _debug_uart_init(void)
	271	{
	272	void __iomem base = (void __iomem )CONFIG_DEBUG_UART_BASE;
	273
	274	bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
	275	}
	276
	277	static inline void wait_xfered(void __iomem *base)
	278	{
	279	do {
09ace916	280	u32 val = readl(base + UART_IR_REG);
30581040 ÁFR	281	if (val & UART_IR_STAT(UART_IR_TXEMPTY))
	282	break;
	283	} while (1);
	284	}
	285
	286	static inline void _debug_uart_putc(int ch)
	287	{
	288	void __iomem base = (void __iomem )CONFIG_DEBUG_UART_BASE;
	289
	290	wait_xfered(base);
09ace916	291	writel(ch, base + UART_FIFO_REG);
30581040 ÁFR	292	wait_xfered(base);
	293	}
	294
	295	DEBUG_UART_FUNCS
	296	#endif