[u-boot.git] / drivers / i2c / davinci_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * TI DaVinci (TMS320DM644x) I2C driver.
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 * (C) Copyright 2007 Sergey Kubushyn <[email protected]>
 * --------------------------------------------------------
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.rst for instructions.
 */

#include <common.h>
#include <i2c.h>
#include <dm.h>
#include <log.h>
#include <asm/arch/hardware.h>
#include <asm/arch/i2c_defs.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "davinci_i2c.h"

#ifdef CONFIG_DM_I2C
/* Information about i2c controller */
struct i2c_bus {
	int			id;
	uint			speed;
	struct i2c_regs		*regs;
};
#endif

#define CHECK_NACK() \
	do {\
		if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
			REG(&(i2c_base->i2c_con)) = 0;\
			return 1;\
		} \
	} while (0)

static int _wait_for_bus(struct i2c_regs *i2c_base)
{
	int	stat, timeout;

	REG(&(i2c_base->i2c_stat)) = 0xffff;

	for (timeout = 0; timeout < 10; timeout++) {
		stat = REG(&(i2c_base->i2c_stat));
		if (!((stat) & I2C_STAT_BB)) {
			REG(&(i2c_base->i2c_stat)) = 0xffff;
			return 0;
		}

		REG(&(i2c_base->i2c_stat)) = stat;
		udelay(50000);
	}

	REG(&(i2c_base->i2c_stat)) = 0xffff;
	return 1;
}

static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
{
	int	stat, timeout;

	for (timeout = 0; timeout < 10; timeout++) {
		udelay(1000);
		stat = REG(&(i2c_base->i2c_stat));
		if (stat & mask)
			return stat;
	}

	REG(&(i2c_base->i2c_stat)) = 0xffff;
	return stat | I2C_TIMEOUT;
}

static void _flush_rx(struct i2c_regs *i2c_base)
{
	while (1) {
		if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
			break;

		REG(&(i2c_base->i2c_drr));
		REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
		udelay(1000);
	}
}

static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
				  uint speed)
{
	uint32_t	div, psc;

	psc = 2;
	/* SCLL + SCLH */
	div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
	REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
	REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
	REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));

	return 0;
}

static void _davinci_i2c_init(struct i2c_regs *i2c_base,
			      uint speed, int slaveadd)
{
	if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
		REG(&(i2c_base->i2c_con)) = 0;
		udelay(50000);
	}

	_davinci_i2c_setspeed(i2c_base, speed);

	REG(&(i2c_base->i2c_oa)) = slaveadd;
	REG(&(i2c_base->i2c_cnt)) = 0;

	/* Interrupts must be enabled or I2C module won't work */
	REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
		I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;

	/* Now enable I2C controller (get it out of reset) */
	REG(&(i2c_base->i2c_con)) = I2C_CON_EN;

	udelay(1000);
}

static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
			     uint32_t addr, int alen, uint8_t *buf, int len)
{
	uint32_t	tmp;
	int		i;

	if ((alen < 0) || (alen > 2)) {
		printf("%s(): bogus address length %x\n", __func__, alen);
		return 1;
	}

	if (_wait_for_bus(i2c_base))
		return 1;

	if (alen != 0) {
		/* Start address phase */
		tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
		REG(&(i2c_base->i2c_cnt)) = alen;
		REG(&(i2c_base->i2c_sa)) = chip;
		REG(&(i2c_base->i2c_con)) = tmp;

		tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		switch (alen) {
		case 2:
			/* Send address MSByte */
			if (tmp & I2C_STAT_XRDY) {
				REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
			} else {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}

			tmp = _poll_i2c_irq(i2c_base,
					    I2C_STAT_XRDY | I2C_STAT_NACK);

			CHECK_NACK();
			/* No break, fall through */
		case 1:
			/* Send address LSByte */
			if (tmp & I2C_STAT_XRDY) {
				REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
			} else {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}

			tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
					    I2C_STAT_NACK | I2C_STAT_ARDY);

			CHECK_NACK();

			if (!(tmp & I2C_STAT_ARDY)) {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}
		}
	}

	/* Address phase is over, now read 'len' bytes and stop */
	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
	REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
	REG(&(i2c_base->i2c_sa)) = chip;
	REG(&(i2c_base->i2c_con)) = tmp;

	for (i = 0; i < len; i++) {
		tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
				   I2C_STAT_ROVR);

		CHECK_NACK();

		if (tmp & I2C_STAT_RRDY) {
			buf[i] = REG(&(i2c_base->i2c_drr));
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
	}

	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);

	CHECK_NACK();

	if (!(tmp & I2C_STAT_SCD)) {
		REG(&(i2c_base->i2c_con)) = 0;
		return 1;
	}

	_flush_rx(i2c_base);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	REG(&(i2c_base->i2c_con)) = 0;

	return 0;
}

static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
			      uint32_t addr, int alen, uint8_t *buf, int len)
{
	uint32_t	tmp;
	int		i;

	if ((alen < 0) || (alen > 2)) {
		printf("%s(): bogus address length %x\n", __func__, alen);
		return 1;
	}
	if (len < 0) {
		printf("%s(): bogus length %x\n", __func__, len);
		return 1;
	}

	if (_wait_for_bus(i2c_base))
		return 1;

	/* Start address phase */
	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
		I2C_CON_TRX | I2C_CON_STP;
	REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
		len & 0xffff : (len & 0xffff) + alen;
	REG(&(i2c_base->i2c_sa)) = chip;
	REG(&(i2c_base->i2c_con)) = tmp;

	switch (alen) {
	case 2:
		/* Send address MSByte */
		tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY) {
			REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
		/* No break, fall through */
	case 1:
		/* Send address LSByte */
		tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY) {
			REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
	}

	for (i = 0; i < len; i++) {
		tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY)
			REG(&(i2c_base->i2c_dxr)) = buf[i];
		else
			return 1;
	}

	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);

	CHECK_NACK();

	if (!(tmp & I2C_STAT_SCD)) {
		REG(&(i2c_base->i2c_con)) = 0;
		return 1;
	}

	_flush_rx(i2c_base);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	REG(&(i2c_base->i2c_con)) = 0;

	return 0;
}

static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
{
	int	rc = 1;

	if (chip == REG(&(i2c_base->i2c_oa)))
		return rc;

	REG(&(i2c_base->i2c_con)) = 0;
	if (_wait_for_bus(i2c_base))
		return 1;

	/* try to read one byte from current (or only) address */
	REG(&(i2c_base->i2c_cnt)) = 1;
	REG(&(i2c_base->i2c_sa))  = chip;
	REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
				     I2C_CON_STP);
	udelay(50000);

	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
		rc = 0;
		_flush_rx(i2c_base);
		REG(&(i2c_base->i2c_stat)) = 0xffff;
	} else {
		REG(&(i2c_base->i2c_stat)) = 0xffff;
		REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
		udelay(20000);
		if (_wait_for_bus(i2c_base))
			return 1;
	}

	_flush_rx(i2c_base);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	return rc;
}

#ifndef CONFIG_DM_I2C
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)I2C2_BASE;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)I2C1_BASE;
#endif
	case 0:
		return (struct i2c_regs *)I2C_BASE;

	default:
		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	}

	return NULL;
}

static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	uint ret;

	adap->speed = speed;
	ret =  _davinci_i2c_setspeed(i2c_base, speed);

	return ret;
}

static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
			     int slaveadd)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);

	adap->speed = speed;
	_davinci_i2c_init(i2c_base, speed, slaveadd);

	return;
}

static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
			    uint32_t addr, int alen, uint8_t *buf, int len)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
}

static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
			     uint32_t addr, int alen, uint8_t *buf, int len)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);

	return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
}

static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);

	return _davinci_i2c_probe_chip(i2c_base, chip);
}

U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE,
			 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED1,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE1,
			 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED2,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE2,
			 2)
#endif

#else /* CONFIG_DM_I2C */

static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			  int nmsgs)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
				0, 0, msg->buf, msg->len);
		} else {
			ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
				0, 0, msg->buf, msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return ret;
}

static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->speed = speed;
	return _davinci_i2c_setspeed(i2c_bus->regs, speed);
}

static int davinci_i2c_probe(struct udevice *dev)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->id = dev->seq;
	i2c_bus->regs = dev_read_addr_ptr(dev);

	i2c_bus->speed = 100000;
	 _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);

	return 0;
}

static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				  uint chip_flags)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);

	return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
}

static const struct dm_i2c_ops davinci_i2c_ops = {
	.xfer		= davinci_i2c_xfer,
	.probe_chip	= davinci_i2c_probe_chip,
	.set_bus_speed	= davinci_i2c_set_speed,
};

static const struct udevice_id davinci_i2c_ids[] = {
	{ .compatible = "ti,davinci-i2c"},
	{ .compatible = "ti,keystone-i2c"},
	{ }
};

U_BOOT_DRIVER(i2c_davinci) = {
	.name	= "i2c_davinci",
	.id	= UCLASS_I2C,
	.of_match = davinci_i2c_ids,
	.probe	= davinci_i2c_probe,
	.priv_auto	= sizeof(struct i2c_bus),
	.ops	= &davinci_i2c_ops,
};

#endif /* CONFIG_DM_I2C */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c74b2108 SK	2	/*
	3	* TI DaVinci (TMS320DM644x) I2C driver.
	4	*
e8459dcc VA	5	* (C) Copyright 2012-2014
	6	* Texas Instruments Incorporated, <www.ti.com>
	7	* (C) Copyright 2007 Sergey Kubushyn <[email protected]>
c74b2108 SK	8	* --------------------------------------------------------
c74b2108 SK	9	*
28527096	10	* NOTE: This driver should be converted to driver model before June 2017.
2799a69e	11	* Please see doc/driver-model/i2c-howto.rst for instructions.
c74b2108 SK	12	*/
	13
	14	#include <common.h>
c74b2108	15	#include <i2c.h>
70f6f94c	16	#include <dm.h>
f7ae49fc	17	#include <log.h>
c74b2108 SK	18	#include <asm/arch/hardware.h>
c74b2108 SK	19	#include <asm/arch/i2c_defs.h>
e8459dcc	20	#include <asm/io.h>
c05ed00a	21	#include <linux/delay.h>
356d15eb	22	#include "davinci_i2c.h"
c74b2108	23
70f6f94c CJF	24	#ifdef CONFIG_DM_I2C
	25	/* Information about i2c controller */
	26	struct i2c_bus {
	27	int id;
	28	uint speed;
	29	struct i2c_regs *regs;
	30	};
	31	#endif
	32
c74b2108 SK	33	#define CHECK_NACK() \
	34	do {\
	35	if (tmp & (I2C_TIMEOUT \| I2C_STAT_NACK)) {\
e8459dcc VA	36	REG(&(i2c_base->i2c_con)) = 0;\
	37	return 1;\
	38	} \
c74b2108 SK	39	} while (0)
c74b2108 SK	40
60219101	41	static int _wait_for_bus(struct i2c_regs *i2c_base)
c74b2108 SK	42	{
	43	int stat, timeout;
	44
e8459dcc	45	REG(&(i2c_base->i2c_stat)) = 0xffff;
c74b2108 SK	46
c74b2108 SK	47	for (timeout = 0; timeout < 10; timeout++) {
e8459dcc VA	48	stat = REG(&(i2c_base->i2c_stat));
	49	if (!((stat) & I2C_STAT_BB)) {
	50	REG(&(i2c_base->i2c_stat)) = 0xffff;
	51	return 0;
c74b2108 SK	52	}
c74b2108 SK	53
e8459dcc	54	REG(&(i2c_base->i2c_stat)) = stat;
c74b2108 SK	55	udelay(50000);
	56	}
	57
e8459dcc VA	58	REG(&(i2c_base->i2c_stat)) = 0xffff;
e8459dcc VA	59	return 1;
c74b2108 SK	60	}
c74b2108 SK	61
60219101	62	static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
c74b2108 SK	63	{
	64	int stat, timeout;
	65
	66	for (timeout = 0; timeout < 10; timeout++) {
	67	udelay(1000);
e8459dcc VA	68	stat = REG(&(i2c_base->i2c_stat));
	69	if (stat & mask)
	70	return stat;
c74b2108 SK	71	}
c74b2108 SK	72
e8459dcc VA	73	REG(&(i2c_base->i2c_stat)) = 0xffff;
e8459dcc VA	74	return stat \| I2C_TIMEOUT;
c74b2108 SK	75	}
c74b2108 SK	76
60219101	77	static void _flush_rx(struct i2c_regs *i2c_base)
c74b2108	78	{
c74b2108	79	while (1) {
e8459dcc	80	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
c74b2108 SK	81	break;
c74b2108 SK	82
e8459dcc VA	83	REG(&(i2c_base->i2c_drr));
e8459dcc VA	84	REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
c74b2108 SK	85	udelay(1000);
	86	}
	87	}
	88
60219101 CJF	89	static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
60219101 CJF	90	uint speed)
e8459dcc	91	{
e8459dcc VA	92	uint32_t div, psc;
	93
	94	psc = 2;
	95	/* SCLL + SCLH */
	96	div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
	97	REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
	98	REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
	99	REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
	100
e8459dcc VA	101	return 0;
e8459dcc VA	102	}
c74b2108	103
60219101 CJF	104	static void _davinci_i2c_init(struct i2c_regs *i2c_base,
60219101 CJF	105	uint speed, int slaveadd)
c74b2108	106	{
e8459dcc VA	107	if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
	108	REG(&(i2c_base->i2c_con)) = 0;
	109	udelay(50000);
c74b2108 SK	110	}
c74b2108 SK	111
60219101	112	_davinci_i2c_setspeed(i2c_base, speed);
c74b2108	113
e8459dcc VA	114	REG(&(i2c_base->i2c_oa)) = slaveadd;
e8459dcc VA	115	REG(&(i2c_base->i2c_cnt)) = 0;
c74b2108 SK	116
c74b2108 SK	117	/* Interrupts must be enabled or I2C module won't work */
e8459dcc	118	REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE \| I2C_IE_XRDY_IE \|
c74b2108 SK	119	I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \| I2C_IE_NACK_IE;
	120
	121	/* Now enable I2C controller (get it out of reset) */
e8459dcc	122	REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
c74b2108 SK	123
	124	udelay(1000);
	125	}
	126
60219101 CJF	127	static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
60219101 CJF	128	uint32_t addr, int alen, uint8_t *buf, int len)
c74b2108	129	{
e8459dcc	130	uint32_t tmp;
c74b2108 SK	131	int i;
	132
	133	if ((alen < 0) \|\| (alen > 2)) {
e8459dcc VA	134	printf("%s(): bogus address length %x\n", __func__, alen);
e8459dcc VA	135	return 1;
c74b2108 SK	136	}
c74b2108 SK	137
60219101	138	if (_wait_for_bus(i2c_base))
e8459dcc	139	return 1;
c74b2108 SK	140
	141	if (alen != 0) {
	142	/* Start address phase */
	143	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX;
e8459dcc VA	144	REG(&(i2c_base->i2c_cnt)) = alen;
	145	REG(&(i2c_base->i2c_sa)) = chip;
	146	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108	147
60219101	148	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108 SK	149
	150	CHECK_NACK();
	151
	152	switch (alen) {
e8459dcc VA	153	case 2:
	154	/* Send address MSByte */
	155	if (tmp & I2C_STAT_XRDY) {
	156	REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
	157	} else {
	158	REG(&(i2c_base->i2c_con)) = 0;
	159	return 1;
	160	}
	161
60219101 CJF	162	tmp = _poll_i2c_irq(i2c_base,
60219101 CJF	163	I2C_STAT_XRDY \| I2C_STAT_NACK);
e8459dcc VA	164
	165	CHECK_NACK();
	166	/* No break, fall through */
	167	case 1:
	168	/* Send address LSByte */
	169	if (tmp & I2C_STAT_XRDY) {
	170	REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
	171	} else {
	172	REG(&(i2c_base->i2c_con)) = 0;
	173	return 1;
	174	}
	175
60219101 CJF	176	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY \|
60219101 CJF	177	I2C_STAT_NACK \| I2C_STAT_ARDY);
e8459dcc VA	178
	179	CHECK_NACK();
	180
	181	if (!(tmp & I2C_STAT_ARDY)) {
	182	REG(&(i2c_base->i2c_con)) = 0;
	183	return 1;
	184	}
c74b2108 SK	185	}
	186	}
	187
	188	/* Address phase is over, now read 'len' bytes and stop */
	189	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP;
e8459dcc VA	190	REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
	191	REG(&(i2c_base->i2c_sa)) = chip;
	192	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108 SK	193
c74b2108 SK	194	for (i = 0; i < len; i++) {
60219101	195	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY \| I2C_STAT_NACK \|
e8459dcc	196	I2C_STAT_ROVR);
c74b2108 SK	197
	198	CHECK_NACK();
	199
	200	if (tmp & I2C_STAT_RRDY) {
e8459dcc	201	buf[i] = REG(&(i2c_base->i2c_drr));
c74b2108	202	} else {
e8459dcc VA	203	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	204	return 1;
c74b2108 SK	205	}
	206	}
	207
60219101	208	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD \| I2C_STAT_NACK);
c74b2108 SK	209
	210	CHECK_NACK();
	211
	212	if (!(tmp & I2C_STAT_SCD)) {
e8459dcc VA	213	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	214	return 1;
c74b2108 SK	215	}
c74b2108 SK	216
60219101	217	_flush_rx(i2c_base);
e8459dcc VA	218	REG(&(i2c_base->i2c_stat)) = 0xffff;
	219	REG(&(i2c_base->i2c_cnt)) = 0;
	220	REG(&(i2c_base->i2c_con)) = 0;
c74b2108	221
e8459dcc	222	return 0;
c74b2108 SK	223	}
c74b2108 SK	224
60219101 CJF	225	static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
60219101 CJF	226	uint32_t addr, int alen, uint8_t *buf, int len)
c74b2108	227	{
e8459dcc	228	uint32_t tmp;
c74b2108 SK	229	int i;
	230
	231	if ((alen < 0) \|\| (alen > 2)) {
e8459dcc VA	232	printf("%s(): bogus address length %x\n", __func__, alen);
e8459dcc VA	233	return 1;
c74b2108 SK	234	}
c74b2108 SK	235	if (len < 0) {
e8459dcc VA	236	printf("%s(): bogus length %x\n", __func__, len);
e8459dcc VA	237	return 1;
c74b2108 SK	238	}
c74b2108 SK	239
60219101	240	if (_wait_for_bus(i2c_base))
e8459dcc	241	return 1;
c74b2108 SK	242
c74b2108 SK	243	/* Start address phase */
e8459dcc VA	244	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
	245	I2C_CON_TRX \| I2C_CON_STP;
	246	REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
	247	len & 0xffff : (len & 0xffff) + alen;
	248	REG(&(i2c_base->i2c_sa)) = chip;
	249	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108 SK	250
c74b2108 SK	251	switch (alen) {
e8459dcc VA	252	case 2:
e8459dcc VA	253	/* Send address MSByte */
60219101	254	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108	255
e8459dcc	256	CHECK_NACK();
c74b2108	257
e8459dcc VA	258	if (tmp & I2C_STAT_XRDY) {
	259	REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
	260	} else {
	261	REG(&(i2c_base->i2c_con)) = 0;
	262	return 1;
	263	}
	264	/* No break, fall through */
	265	case 1:
	266	/* Send address LSByte */
60219101	267	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108	268
e8459dcc	269	CHECK_NACK();
c74b2108	270
e8459dcc VA	271	if (tmp & I2C_STAT_XRDY) {
	272	REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
	273	} else {
	274	REG(&(i2c_base->i2c_con)) = 0;
	275	return 1;
	276	}
c74b2108 SK	277	}
	278
	279	for (i = 0; i < len; i++) {
60219101	280	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108 SK	281
	282	CHECK_NACK();
	283
e8459dcc VA	284	if (tmp & I2C_STAT_XRDY)
	285	REG(&(i2c_base->i2c_dxr)) = buf[i];
	286	else
	287	return 1;
c74b2108 SK	288	}
c74b2108 SK	289
60219101	290	tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD \| I2C_STAT_NACK);
c74b2108 SK	291
	292	CHECK_NACK();
	293
	294	if (!(tmp & I2C_STAT_SCD)) {
e8459dcc VA	295	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	296	return 1;
c74b2108 SK	297	}
c74b2108 SK	298
60219101	299	_flush_rx(i2c_base);
e8459dcc VA	300	REG(&(i2c_base->i2c_stat)) = 0xffff;
	301	REG(&(i2c_base->i2c_cnt)) = 0;
	302	REG(&(i2c_base->i2c_con)) = 0;
	303
	304	return 0;
	305	}
	306
60219101 CJF	307	static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
	308	{
	309	int rc = 1;
	310
	311	if (chip == REG(&(i2c_base->i2c_oa)))
	312	return rc;
	313
	314	REG(&(i2c_base->i2c_con)) = 0;
	315	if (_wait_for_bus(i2c_base))
	316	return 1;
	317
	318	/* try to read one byte from current (or only) address */
	319	REG(&(i2c_base->i2c_cnt)) = 1;
	320	REG(&(i2c_base->i2c_sa)) = chip;
	321	REG(&(i2c_base->i2c_con)) = (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
	322	I2C_CON_STP);
	323	udelay(50000);
	324
	325	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
	326	rc = 0;
	327	_flush_rx(i2c_base);
	328	REG(&(i2c_base->i2c_stat)) = 0xffff;
	329	} else {
	330	REG(&(i2c_base->i2c_stat)) = 0xffff;
	331	REG(&(i2c_base->i2c_con)) \|= I2C_CON_STP;
	332	udelay(20000);
	333	if (_wait_for_bus(i2c_base))
	334	return 1;
	335	}
	336
	337	_flush_rx(i2c_base);
	338	REG(&(i2c_base->i2c_stat)) = 0xffff;
	339	REG(&(i2c_base->i2c_cnt)) = 0;
	340	return rc;
	341	}
	342
70f6f94c	343	#ifndef CONFIG_DM_I2C
e8459dcc VA	344	static struct i2c_regs davinci_get_base(struct i2c_adapter adap)
	345	{
	346	switch (adap->hwadapnr) {
ac1d8ac8	347	#if CONFIG_SYS_I2C_BUS_MAX >= 3
e8459dcc VA	348	case 2:
	349	return (struct i2c_regs *)I2C2_BASE;
	350	#endif
ac1d8ac8	351	#if CONFIG_SYS_I2C_BUS_MAX >= 2
e8459dcc VA	352	case 1:
	353	return (struct i2c_regs *)I2C1_BASE;
	354	#endif
	355	case 0:
	356	return (struct i2c_regs *)I2C_BASE;
	357
	358	default:
	359	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	360	}
c74b2108	361
e8459dcc	362	return NULL;
c74b2108	363	}
e8459dcc	364
60219101 CJF	365	static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
	366	{
	367	struct i2c_regs *i2c_base = davinci_get_base(adap);
	368	uint ret;
	369
	370	adap->speed = speed;
	371	ret = _davinci_i2c_setspeed(i2c_base, speed);
	372
	373	return ret;
	374	}
	375
	376	static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
	377	int slaveadd)
	378	{
	379	struct i2c_regs *i2c_base = davinci_get_base(adap);
	380
	381	adap->speed = speed;
	382	_davinci_i2c_init(i2c_base, speed, slaveadd);
	383
	384	return;
	385	}
	386
	387	static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
	388	uint32_t addr, int alen, uint8_t *buf, int len)
	389	{
	390	struct i2c_regs *i2c_base = davinci_get_base(adap);
	391	return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
	392	}
	393
	394	static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
	395	uint32_t addr, int alen, uint8_t *buf, int len)
	396	{
	397	struct i2c_regs *i2c_base = davinci_get_base(adap);
	398
	399	return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
	400	}
	401
	402	static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
	403	{
	404	struct i2c_regs *i2c_base = davinci_get_base(adap);
	405
	406	return _davinci_i2c_probe_chip(i2c_base, chip);
	407	}
	408
	409	U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
e8459dcc VA	410	davinci_i2c_read, davinci_i2c_write,
	411	davinci_i2c_setspeed,
	412	CONFIG_SYS_DAVINCI_I2C_SPEED,
	413	CONFIG_SYS_DAVINCI_I2C_SLAVE,
	414	0)
	415
ac1d8ac8	416	#if CONFIG_SYS_I2C_BUS_MAX >= 2
60219101	417	U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
e8459dcc VA	418	davinci_i2c_read, davinci_i2c_write,
	419	davinci_i2c_setspeed,
	420	CONFIG_SYS_DAVINCI_I2C_SPEED1,
	421	CONFIG_SYS_DAVINCI_I2C_SLAVE1,
	422	1)
	423	#endif
	424
ac1d8ac8	425	#if CONFIG_SYS_I2C_BUS_MAX >= 3
60219101	426	U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
e8459dcc VA	427	davinci_i2c_read, davinci_i2c_write,
	428	davinci_i2c_setspeed,
	429	CONFIG_SYS_DAVINCI_I2C_SPEED2,
	430	CONFIG_SYS_DAVINCI_I2C_SLAVE2,
	431	2)
	432	#endif
70f6f94c CJF	433
	434	#else /* CONFIG_DM_I2C */
	435
	436	static int davinci_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	437	int nmsgs)
	438	{
	439	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	440	int ret;
	441
	442	debug("i2c_xfer: %d messages\n", nmsgs);
	443	for (; nmsgs > 0; nmsgs--, msg++) {
	444	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	445	if (msg->flags & I2C_M_RD) {
	446	ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
	447	0, 0, msg->buf, msg->len);
	448	} else {
	449	ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
	450	0, 0, msg->buf, msg->len);
	451	}
	452	if (ret) {
	453	debug("i2c_write: error sending\n");
	454	return -EREMOTEIO;
	455	}
	456	}
	457
	458	return ret;
	459	}
	460
	461	static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
	462	{
	463	struct i2c_bus *i2c_bus = dev_get_priv(dev);
	464
	465	i2c_bus->speed = speed;
	466	return _davinci_i2c_setspeed(i2c_bus->regs, speed);
	467	}
	468
	469	static int davinci_i2c_probe(struct udevice *dev)
	470	{
	471	struct i2c_bus *i2c_bus = dev_get_priv(dev);
	472
	473	i2c_bus->id = dev->seq;
8613c8d8	474	i2c_bus->regs = dev_read_addr_ptr(dev);
70f6f94c CJF	475
	476	i2c_bus->speed = 100000;
	477	_davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
	478
	479	return 0;
	480	}
	481
	482	static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
	483	uint chip_flags)
	484	{
	485	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	486
	487	return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
	488	}
	489
	490	static const struct dm_i2c_ops davinci_i2c_ops = {
	491	.xfer = davinci_i2c_xfer,
	492	.probe_chip = davinci_i2c_probe_chip,
	493	.set_bus_speed = davinci_i2c_set_speed,
	494	};
	495
	496	static const struct udevice_id davinci_i2c_ids[] = {
	497	{ .compatible = "ti,davinci-i2c"},
	498	{ .compatible = "ti,keystone-i2c"},
	499	{ }
	500	};
	501
	502	U_BOOT_DRIVER(i2c_davinci) = {
	503	.name = "i2c_davinci",
	504	.id = UCLASS_I2C,
	505	.of_match = davinci_i2c_ids,
	506	.probe = davinci_i2c_probe,
41575d8e	507	.priv_auto = sizeof(struct i2c_bus),
70f6f94c CJF	508	.ops = &davinci_i2c_ops,
	509	};
	510
	511	#endif /* CONFIG_DM_I2C */