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[u-boot.git] / drivers / clk / mediatek / clk-mt7623.c
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c7466515
RL		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek clock driver for MT7623 SoC
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <[email protected]>
7 */
8
9#include <common.h>
10#include <dm.h>
f7ae49fc 11#include <log.h>
2dca3cc2 12#include <asm/arch-mediatek/reset.h>
c7466515
RL		 13#include <asm/io.h>
14#include <dt-bindings/clock/mt7623-clk.h>
cd93d625 15#include <linux/bitops.h>
c7466515
RL		 16
17#include "clk-mtk.h"
18
19#define MT7623_CLKSQ_STB_CON0 0x18
20#define MT7623_PLL_ISO_CON0 0x24
21#define MT7623_PLL_FMAX (2000UL * MHZ)
22#define MT7623_CON0_RST_BAR BIT(27)
23
24#define MCU_AXI_DIV 0x60
25#define AXI_DIV_MSK GENMASK(4, 0)
26#define AXI_DIV_SEL(x) (x)
27
28/* apmixedsys */
29#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
30 _pd_shift, _pcw_reg, _pcw_shift) { \
31 .id = _id, \
32 .reg = _reg, \
33 .pwr_reg = _pwr_reg, \
34 .en_mask = _en_mask, \
35 .rst_bar_mask = MT7623_CON0_RST_BAR, \
36 .fmax = MT7623_PLL_FMAX, \
37 .flags = _flags, \
38 .pcwbits = _pcwbits, \
39 .pd_reg = _pd_reg, \
40 .pd_shift = _pd_shift, \
41 .pcw_reg = _pcw_reg, \
42 .pcw_shift = _pcw_shift, \
43 }
44
45static const struct mtk_pll_data apmixed_plls[] = {
46 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
47 21, 0x204, 24, 0x204, 0),
48 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
49 21, 0x210, 4, 0x214, 0),
50 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
51 7, 0x220, 4, 0x224, 14),
52 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
53 21, 0x230, 4, 0x234, 0),
54 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
55 21, 0x240, 4, 0x244, 0),
56 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
57 21, 0x250, 4, 0x254, 0),
58 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
59 31, 0x270, 4, 0x274, 0),
60 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
61 31, 0x280, 4, 0x284, 0),
62 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
63 31, 0x290, 4, 0x294, 0),
64 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
65 31, 0x2a0, 4, 0x2a4, 0),
66 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
67 31, 0x2b0, 4, 0x2b4, 0),
68 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
69 31, 0x2c0, 4, 0x2c4, 0),
70 PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
71 21, 0x2d0, 4, 0x2d4, 0),
72};
73
74/* topckgen */
75#define FACTOR0(_id, _parent, _mult, _div) \
76 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
77
78#define FACTOR1(_id, _parent, _mult, _div) \
79 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
80
81#define FACTOR2(_id, _parent, _mult, _div) \
82 FACTOR(_id, _parent, _mult, _div, 0)
83
84static const struct mtk_fixed_clk top_fixed_clks[] = {
85 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
86 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
87 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
90 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
91 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
92 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
93 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
94 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
95 FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
96 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
97 FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
98 FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
99 FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
100};
101
102static const struct mtk_fixed_factor top_fixed_divs[] = {
103 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
104 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
105 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
106 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
107 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
108 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
109 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
110 FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
111 FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
112 FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
113 FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
114 FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
115 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
116 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
117 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
118 FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
119
120 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
121 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
122 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
123 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
124 FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
125 FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
126 FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
127 FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
128 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
129 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
130 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
131 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
132 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
133 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
134 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
135 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
136 FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
137 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
138 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
139 FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
140
141 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
142 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
143 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
144 FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
145
146 FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
147 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
148
149 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
150 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
151 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
152
153 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
154 FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
155 FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
156
157 FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
158 FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
159 FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
160
161 FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
162 FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
163 FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
164
165 FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
166 FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
167 FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
168
169 FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
170
171 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
172 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
173 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
174 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
175 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
176
177 FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
178 FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
179 FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
180 FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
181 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
182 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
183 FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
184 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
185 FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
186};
187
188static const int axi_parents[] = {
189 CLK_XTAL,
190 CLK_TOP_SYSPLL1_D2,
191 CLK_TOP_SYSPLL_D5,
192 CLK_TOP_SYSPLL1_D4,
193 CLK_TOP_UNIVPLL_D5,
194 CLK_TOP_UNIVPLL2_D2,
195 CLK_TOP_MMPLL_D2,
196 CLK_TOP_DMPLL_D2
197};
198
199static const int mem_parents[] = {
200 CLK_XTAL,
201 CLK_TOP_DMPLL
202};
203
204static const int ddrphycfg_parents[] = {
205 CLK_XTAL,
206 CLK_TOP_SYSPLL1_D8
207};
208
209static const int mm_parents[] = {
210 CLK_XTAL,
211 CLK_TOP_VENCPLL,
212 CLK_TOP_SYSPLL1_D2,
213 CLK_TOP_SYSPLL1_D4,
214 CLK_TOP_UNIVPLL_D5,
215 CLK_TOP_UNIVPLL1_D2,
216 CLK_TOP_UNIVPLL2_D2,
217 CLK_TOP_DMPLL
218};
219
220static const int pwm_parents[] = {
221 CLK_XTAL,
222 CLK_TOP_UNIVPLL2_D4,
223 CLK_TOP_UNIVPLL3_D2,
224 CLK_TOP_UNIVPLL1_D4
225};
226
227static const int vdec_parents[] = {
228 CLK_XTAL,
229 CLK_TOP_VDECPLL,
230 CLK_TOP_SYSPLL_D5,
231 CLK_TOP_SYSPLL1_D4,
232 CLK_TOP_UNIVPLL_D5,
233 CLK_TOP_UNIVPLL2_D2,
234 CLK_TOP_VENCPLL,
235 CLK_TOP_MSDCPLL_D2,
236 CLK_TOP_MMPLL_D2
237};
238
239static const int mfg_parents[] = {
240 CLK_XTAL,
241 CLK_TOP_MMPLL,
242 CLK_TOP_DMPLL_X2,
243 CLK_TOP_MSDCPLL,
244 CLK_XTAL,
245 CLK_TOP_SYSPLL_D3,
246 CLK_TOP_UNIVPLL_D3,
247 CLK_TOP_UNIVPLL1_D2
248};
249
250static const int camtg_parents[] = {
251 CLK_XTAL,
252 CLK_TOP_UNIVPLL_D26,
253 CLK_TOP_UNIVPLL2_D2,
254 CLK_TOP_SYSPLL3_D2,
255 CLK_TOP_SYSPLL3_D4,
256 CLK_TOP_MSDCPLL_D2,
257 CLK_TOP_MMPLL_D2
258};
259
260static const int uart_parents[] = {
261 CLK_XTAL,
262 CLK_TOP_UNIVPLL2_D8
263};
264
265static const int spi_parents[] = {
266 CLK_XTAL,
267 CLK_TOP_SYSPLL3_D2,
268 CLK_TOP_SYSPLL4_D2,
269 CLK_TOP_UNIVPLL2_D4,
270 CLK_TOP_UNIVPLL1_D8
271};
272
273static const int usb20_parents[] = {
274 CLK_XTAL,
275 CLK_TOP_UNIVPLL1_D8,
276 CLK_TOP_UNIVPLL3_D4
277};
278
279static const int msdc30_parents[] = {
280 CLK_XTAL,
281 CLK_TOP_MSDCPLL_D2,
282 CLK_TOP_SYSPLL2_D2,
283 CLK_TOP_SYSPLL1_D4,
284 CLK_TOP_UNIVPLL1_D4,
285 CLK_TOP_UNIVPLL2_D4,
286};
287
288static const int aud_intbus_parents[] = {
289 CLK_XTAL,
290 CLK_TOP_SYSPLL1_D4,
291 CLK_TOP_SYSPLL3_D2,
292 CLK_TOP_SYSPLL4_D2,
293 CLK_TOP_UNIVPLL3_D2,
294 CLK_TOP_UNIVPLL2_D4
295};
296
297static const int pmicspi_parents[] = {
298 CLK_XTAL,
299 CLK_TOP_SYSPLL1_D8,
300 CLK_TOP_SYSPLL2_D4,
301 CLK_TOP_SYSPLL4_D2,
302 CLK_TOP_SYSPLL3_D4,
303 CLK_TOP_SYSPLL2_D8,
304 CLK_TOP_SYSPLL1_D16,
305 CLK_TOP_UNIVPLL3_D4,
306 CLK_TOP_UNIVPLL_D26,
307 CLK_TOP_DMPLL_D2,
308 CLK_TOP_DMPLL_D4
309};
310
311static const int scp_parents[] = {
312 CLK_XTAL,
313 CLK_TOP_SYSPLL1_D8,
314 CLK_TOP_DMPLL_D2,
315 CLK_TOP_DMPLL_D4
316};
317
318static const int dpi0_tve_parents[] = {
319 CLK_XTAL,
320 CLK_TOP_MIPIPLL,
321 CLK_TOP_MIPIPLL_D2,
322 CLK_TOP_MIPIPLL_D4,
323 CLK_XTAL,
324 CLK_TOP_TVDPLL,
325 CLK_TOP_TVDPLL_D2,
326 CLK_TOP_TVDPLL_D4
327};
328
329static const int dpi1_parents[] = {
330 CLK_XTAL,
331 CLK_TOP_TVDPLL,
332 CLK_TOP_TVDPLL_D2,
333 CLK_TOP_TVDPLL_D4
334};
335
336static const int hdmi_parents[] = {
337 CLK_XTAL,
338 CLK_TOP_HDMIPLL,
339 CLK_TOP_HDMIPLL_D2,
340 CLK_TOP_HDMIPLL_D3
341};
342
343static const int apll_parents[] = {
344 CLK_XTAL,
345 CLK_TOP_AUDPLL,
346 CLK_TOP_AUDPLL_D4,
347 CLK_TOP_AUDPLL_D8,
348 CLK_TOP_AUDPLL_D16,
349 CLK_TOP_AUDPLL_D24,
350 CLK_XTAL,
351 CLK_XTAL
352};
353
354static const int rtc_parents[] = {
355 CLK_TOP_32K_INTERNAL,
356 CLK_TOP_32K_EXTERNAL,
357 CLK_XTAL,
358 CLK_TOP_UNIVPLL3_D8
359};
360
361static const int nfi2x_parents[] = {
362 CLK_XTAL,
363 CLK_TOP_SYSPLL2_D2,
364 CLK_TOP_SYSPLL_D7,
365 CLK_TOP_UNIVPLL3_D2,
366 CLK_TOP_SYSPLL2_D4,
367 CLK_TOP_UNIVPLL3_D4,
368 CLK_TOP_SYSPLL4_D4,
369 CLK_XTAL
370};
371
372static const int emmc_hclk_parents[] = {
373 CLK_XTAL,
374 CLK_TOP_SYSPLL1_D2,
375 CLK_TOP_SYSPLL1_D4,
376 CLK_TOP_SYSPLL2_D2
377};
378
379static const int flash_parents[] = {
380 CLK_TOP_CLK26M_D8,
381 CLK_XTAL,
382 CLK_TOP_SYSPLL2_D8,
383 CLK_TOP_SYSPLL3_D4,
384 CLK_TOP_UNIVPLL3_D4,
385 CLK_TOP_SYSPLL4_D2,
386 CLK_TOP_SYSPLL2_D4,
387 CLK_TOP_UNIVPLL2_D4
388};
389
390static const int di_parents[] = {
391 CLK_XTAL,
392 CLK_TOP_TVD2PLL,
393 CLK_TOP_TVD2PLL_D2,
394 CLK_XTAL
395};
396
397static const int nr_osd_parents[] = {
398 CLK_XTAL,
399 CLK_TOP_VENCPLL,
400 CLK_TOP_SYSPLL1_D2,
401 CLK_TOP_SYSPLL1_D4,
402 CLK_TOP_UNIVPLL_D5,
403 CLK_TOP_UNIVPLL1_D2,
404 CLK_TOP_UNIVPLL2_D2,
405 CLK_TOP_DMPLL
406};
407
408static const int hdmirx_bist_parents[] = {
409 CLK_XTAL,
410 CLK_TOP_SYSPLL_D3,
411 CLK_XTAL,
412 CLK_TOP_SYSPLL1_D16,
413 CLK_TOP_SYSPLL4_D2,
414 CLK_TOP_SYSPLL1_D4,
415 CLK_TOP_VENCPLL,
416 CLK_XTAL
417};
418
419static const int intdir_parents[] = {
420 CLK_XTAL,
421 CLK_TOP_MMPLL,
422 CLK_TOP_SYSPLL_D2,
423 CLK_TOP_UNIVPLL_D2
424};
425
426static const int asm_parents[] = {
427 CLK_XTAL,
428 CLK_TOP_UNIVPLL2_D4,
429 CLK_TOP_UNIVPLL2_D2,
430 CLK_TOP_SYSPLL_D5
431};
432
433static const int ms_card_parents[] = {
434 CLK_XTAL,
435 CLK_TOP_UNIVPLL3_D8,
436 CLK_TOP_SYSPLL4_D4
437};
438
439static const int ethif_parents[] = {
440 CLK_XTAL,
441 CLK_TOP_SYSPLL1_D2,
442 CLK_TOP_SYSPLL_D5,
443 CLK_TOP_SYSPLL1_D4,
444 CLK_TOP_UNIVPLL_D5,
445 CLK_TOP_UNIVPLL1_D2,
446 CLK_TOP_DMPLL,
447 CLK_TOP_DMPLL_D2
448};
449
450static const int hdmirx_parents[] = {
451 CLK_XTAL,
452 CLK_TOP_UNIVPLL_D52
453};
454
455static const int cmsys_parents[] = {
456 CLK_XTAL,
457 CLK_TOP_SYSPLL1_D2,
458 CLK_TOP_UNIVPLL1_D2,
459 CLK_TOP_UNIVPLL_D5,
460 CLK_TOP_SYSPLL_D5,
461 CLK_TOP_SYSPLL2_D2,
462 CLK_TOP_SYSPLL1_D4,
463 CLK_TOP_SYSPLL3_D2,
464 CLK_TOP_SYSPLL2_D4,
465 CLK_TOP_SYSPLL1_D8,
466 CLK_XTAL,
467 CLK_XTAL,
468 CLK_XTAL,
469 CLK_XTAL,
470 CLK_XTAL
471};
472
473static const int clk_8bdac_parents[] = {
474 CLK_TOP_32K_INTERNAL,
475 CLK_TOP_8BDAC,
476 CLK_XTAL,
477 CLK_XTAL
478};
479
480static const int aud2dvd_parents[] = {
481 CLK_TOP_AUD_48K_TIMING,
482 CLK_TOP_AUD_44K_TIMING
483};
484
485static const int padmclk_parents[] = {
486 CLK_XTAL,
487 CLK_TOP_UNIVPLL_D26,
488 CLK_TOP_UNIVPLL_D52,
489 CLK_TOP_UNIVPLL_D108,
490 CLK_TOP_UNIVPLL2_D8,
491 CLK_TOP_UNIVPLL2_D16,
492 CLK_TOP_UNIVPLL2_D32
493};
494
495static const int aud_mux_parents[] = {
496 CLK_XTAL,
497 CLK_TOP_AUD1PLL_98M,
498 CLK_TOP_AUD2PLL_90M,
499 CLK_TOP_HADDS2PLL_98M,
500 CLK_TOP_AUD_EXTCK1_DIV,
501 CLK_TOP_AUD_EXTCK2_DIV
502};
503
504static const int aud_src_parents[] = {
505 CLK_TOP_AUD_MUX1_SEL,
506 CLK_TOP_AUD_MUX2_SEL
507};
508
509static const struct mtk_composite top_muxes[] = {
510 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
511 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
512 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
513 MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
514 CLK_DOMAIN_SCPSYS),
515
516 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
517 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
518 MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
519 CLK_DOMAIN_SCPSYS),
520 MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
521
522 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
523 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
524 MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
525 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
526
527 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
528 MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
529 MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
530 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
531
532 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
533 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
534 MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
535 MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
536
537 MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
538 MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
540
541 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
542 MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
543 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
544
545 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
546 MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
547 MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
548 MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
549
550 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
551 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
552 MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
553 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
554
555 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
556 MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
557 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
558 CLK_DOMAIN_SCPSYS),
559
560 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
561 MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
562 MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
563
564 MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
565 MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
566 MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
567 MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
568
569 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
570
571 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
572 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
573 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
574
575 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
576 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
577 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
578 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
579 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
580 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
581};
582
583/* infracfg */
584static const struct mtk_gate_regs infra_cg_regs = {
585 .set_ofs = 0x40,
586 .clr_ofs = 0x44,
587 .sta_ofs = 0x48,
588};
589
590#define GATE_INFRA(_id, _parent, _shift) { \
591 .id = _id, \
592 .parent = _parent, \
593 .regs = &infra_cg_regs, \
594 .shift = _shift, \
595 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
596 }
597
598static const struct mtk_gate infra_cgs[] = {
599 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
600 GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
601 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
602 GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
603 GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
604 GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
605 GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
606 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
607 GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
608 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
609 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
610 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
611 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
612 GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
613 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
614 GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
615 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
616 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
617};
618
619/* pericfg */
620static const struct mtk_gate_regs peri0_cg_regs = {
621 .set_ofs = 0x8,
622 .clr_ofs = 0x10,
623 .sta_ofs = 0x18,
624};
625
626static const struct mtk_gate_regs peri1_cg_regs = {
627 .set_ofs = 0xC,
628 .clr_ofs = 0x14,
629 .sta_ofs = 0x1C,
630};
631
632#define GATE_PERI0(_id, _parent, _shift) { \
633 .id = _id, \
634 .parent = _parent, \
635 .regs = &peri0_cg_regs, \
636 .shift = _shift, \
637 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
638 }
639
640#define GATE_PERI1(_id, _parent, _shift) { \
641 .id = _id, \
642 .parent = _parent, \
643 .regs = &peri1_cg_regs, \
644 .shift = _shift, \
645 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
646 }
647
648static const struct mtk_gate peri_cgs[] = {
649 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
650 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
651 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
652 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
653 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
654 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
655 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
656 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
657 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
658 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
659 GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
660 GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
661 GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
662 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
663 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
664 GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
665 GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
666 GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
667 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
668 GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
669 GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
670 GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
671 GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
672 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
673 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
674 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
675 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
676 GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
677 GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
678 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
679 GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
680 GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
681
682 GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
683 GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
684 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
685 GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
686 GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
687 GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
688 GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
689 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
690 GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
691 GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
692 GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
693 GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
694};
695
2d88b5a3
RL		 696/* ethsys and hifsys */
697static const struct mtk_gate_regs eth_hif_cg_regs = {
c7466515
RL		 698 .sta_ofs = 0x30,
699};
700
2d88b5a3 701#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
c7466515
RL		 702 .id = _id, \
703 .parent = _parent, \
2d88b5a3 704 .regs = &eth_hif_cg_regs, \
c7466515
RL		 705 .shift = _shift, \
706 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
707 }
708
2d88b5a3
RL		 709#define GATE_ETH_HIF0(_id, _parent, _shift) \
710 GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
c7466515 711
2d88b5a3
RL		 712#define GATE_ETH_HIF1(_id, _parent, _shift) \
713 GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
c7466515
RL		 714
715static const struct mtk_gate eth_cgs[] = {
2d88b5a3
RL		 716 GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
717 GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
718 GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
719 GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
720 GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
721 GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
722 GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
723 GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
724};
725
726static const struct mtk_gate hif_cgs[] = {
727 GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
728 GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
729 GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
730 GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
731 GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
c7466515
RL		 732};
733
734static const struct mtk_clk_tree mt7623_clk_tree = {
735 .xtal_rate = 26 * MHZ,
736 .xtal2_rate = 26 * MHZ,
737 .fdivs_offs = CLK_TOP_SYSPLL,
738 .muxes_offs = CLK_TOP_AXI_SEL,
739 .plls = apmixed_plls,
740 .fclks = top_fixed_clks,
741 .fdivs = top_fixed_divs,
742 .muxes = top_muxes,
743};
744
745static int mt7623_mcucfg_probe(struct udevice *dev)
746{
747 void __iomem *base;
748
749 base = dev_read_addr_ptr(dev);
750 if (!base)
751 return -ENOENT;
752
753 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
754 AXI_DIV_SEL(0x12));
755
756 return 0;
757}
758
759static int mt7623_apmixedsys_probe(struct udevice *dev)
760{
761 struct mtk_clk_priv *priv = dev_get_priv(dev);
762 int ret;
763
764 ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
765 if (ret)
766 return ret;
767
768 /* reduce clock square disable time */
769 writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
770 /* extend control timing to 1us */
771 writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
772
773 return 0;
774}
775
776static int mt7623_topckgen_probe(struct udevice *dev)
777{
778 return mtk_common_clk_init(dev, &mt7623_clk_tree);
779}
780
781static int mt7623_infracfg_probe(struct udevice *dev)
782{
783 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
784}
785
786static int mt7623_pericfg_probe(struct udevice *dev)
787{
788 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
789}
790
2d88b5a3
RL		 791static int mt7623_hifsys_probe(struct udevice *dev)
792{
793 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
794}
795
c7466515
RL		 796static int mt7623_ethsys_probe(struct udevice *dev)
797{
798 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
799}
800
2d88b5a3 801static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
2dca3cc2
WG		 802{
803 int ret = 0;
804
805#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
2d88b5a3 806 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
2dca3cc2 807 if (ret)
2d88b5a3 808 debug("Warning: failed to bind reset controller\n");
2dca3cc2
WG		 809#endif
810
811 return ret;
812}
813
c7466515
RL		 814static const struct udevice_id mt7623_apmixed_compat[] = {
815 { .compatible = "mediatek,mt7623-apmixedsys" },
816 { }
817};
818
819static const struct udevice_id mt7623_topckgen_compat[] = {
820 { .compatible = "mediatek,mt7623-topckgen" },
821 { }
822};
823
824static const struct udevice_id mt7623_infracfg_compat[] = {
825 { .compatible = "mediatek,mt7623-infracfg", },
826 { }
827};
828
829static const struct udevice_id mt7623_pericfg_compat[] = {
830 { .compatible = "mediatek,mt7623-pericfg", },
831 { }
832};
833
834static const struct udevice_id mt7623_ethsys_compat[] = {
835 { .compatible = "mediatek,mt7623-ethsys" },
836 { }
837};
838
2d88b5a3
RL		 839static const struct udevice_id mt7623_hifsys_compat[] = {
840 { .compatible = "mediatek,mt7623-hifsys" },
841 { }
842};
843
c7466515
RL		 844static const struct udevice_id mt7623_mcucfg_compat[] = {
845 { .compatible = "mediatek,mt7623-mcucfg" },
846 { }
847};
848
849U_BOOT_DRIVER(mtk_mcucfg) = {
850 .name = "mt7623-mcucfg",
851 .id = UCLASS_SYSCON,
852 .of_match = mt7623_mcucfg_compat,
853 .probe = mt7623_mcucfg_probe,
854 .flags = DM_FLAG_PRE_RELOC,
855};
856
857U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
858 .name = "mt7623-clock-apmixedsys",
859 .id = UCLASS_CLK,
860 .of_match = mt7623_apmixed_compat,
861 .probe = mt7623_apmixedsys_probe,
41575d8e 862 .priv_auto = sizeof(struct mtk_clk_priv),
c7466515
RL		 863 .ops = &mtk_clk_apmixedsys_ops,
864 .flags = DM_FLAG_PRE_RELOC,
865};
866
867U_BOOT_DRIVER(mtk_clk_topckgen) = {
868 .name = "mt7623-clock-topckgen",
869 .id = UCLASS_CLK,
870 .of_match = mt7623_topckgen_compat,
871 .probe = mt7623_topckgen_probe,
41575d8e 872 .priv_auto = sizeof(struct mtk_clk_priv),
c7466515
RL		 873 .ops = &mtk_clk_topckgen_ops,
874 .flags = DM_FLAG_PRE_RELOC,
875};
876
877U_BOOT_DRIVER(mtk_clk_infracfg) = {
878 .name = "mt7623-infracfg",
879 .id = UCLASS_CLK,
880 .of_match = mt7623_infracfg_compat,
881 .probe = mt7623_infracfg_probe,
41575d8e 882 .priv_auto = sizeof(struct mtk_cg_priv),
c7466515
RL		 883 .ops = &mtk_clk_gate_ops,
884 .flags = DM_FLAG_PRE_RELOC,
885};
886
887U_BOOT_DRIVER(mtk_clk_pericfg) = {
888 .name = "mt7623-pericfg",
889 .id = UCLASS_CLK,
890 .of_match = mt7623_pericfg_compat,
891 .probe = mt7623_pericfg_probe,
41575d8e 892 .priv_auto = sizeof(struct mtk_cg_priv),
c7466515
RL		 893 .ops = &mtk_clk_gate_ops,
894 .flags = DM_FLAG_PRE_RELOC,
895};
896
2d88b5a3
RL		 897U_BOOT_DRIVER(mtk_clk_hifsys) = {
898 .name = "mt7623-clock-hifsys",
899 .id = UCLASS_CLK,
900 .of_match = mt7623_hifsys_compat,
901 .probe = mt7623_hifsys_probe,
902 .bind = mt7623_ethsys_hifsys_bind,
41575d8e 903 .priv_auto = sizeof(struct mtk_cg_priv),
2d88b5a3
RL		 904 .ops = &mtk_clk_gate_ops,
905};
906
c7466515
RL		 907U_BOOT_DRIVER(mtk_clk_ethsys) = {
908 .name = "mt7623-clock-ethsys",
909 .id = UCLASS_CLK,
910 .of_match = mt7623_ethsys_compat,
911 .probe = mt7623_ethsys_probe,
2d88b5a3 912 .bind = mt7623_ethsys_hifsys_bind,
41575d8e 913 .priv_auto = sizeof(struct mtk_cg_priv),
c7466515
RL		 914 .ops = &mtk_clk_gate_ops,
915};
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