[u-boot.git] / drivers / usb / host / ehci-omap.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Derived from Beagle Board code by
 *	Sunil Kumar <[email protected]>
 *	Shashi Ranjan <[email protected]>
 *
 */

#include <common.h>
#include <log.h>
#include <usb.h>
#include <linux/delay.h>
#include <usb/ulpi.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <power/regulator.h>

#include "ehci.h"

static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;

static int omap_uhh_reset(void)
{
	int timeout = 0;
	u32 rev;

	rev = readl(&uhh->rev);

	/* Soft RESET */
	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);

	switch (rev) {
	case OMAP_USBHS_REV1:
		/* Wait for soft RESET to complete */
		while (!(readl(&uhh->syss) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		/* Set No-Idle, No-Standby */
		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;

	default:	/* Rev. 2 onwards */

		udelay(2); /* Need to wait before accessing SYSCONFIG back */

		/* Wait for soft RESET to complete */
		while ((readl(&uhh->sysc) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;
	}

	return 0;
}

static int omap_ehci_tll_reset(void)
{
	unsigned long init = get_timer(0);

	/* perform TLL soft reset, and wait until reset is complete */
	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);

	/* Wait for TLL reset to complete */
	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
		if (get_timer(init) > CONFIG_SYS_HZ) {
			debug("OMAP EHCI error: timeout resetting TLL\n");
			return -EL3RST;
	}

	return 0;
}

static void omap_usbhs_hsic_init(int port)
{
	unsigned int reg;

	/* Enable channels now */
	reg = readl(&usbtll->channel_conf + port);

	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
		| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
		| OMAP_TLL_CHANNEL_CONF_DRVVBUS
		| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
		| OMAP_TLL_CHANNEL_CONF_CHANEN));

	writel(reg, &usbtll->channel_conf + port);
}

#ifdef CONFIG_USB_ULPI
static void omap_ehci_soft_phy_reset(int port)
{
	struct ulpi_viewport ulpi_vp;

	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	ulpi_vp.port_num = port;

	ulpi_reset(&ulpi_vp);
}
#else
static void omap_ehci_soft_phy_reset(int port)
{
	return;
}
#endif

#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
static inline void omap_ehci_phy_reset(int on, int delay)
{
	/*
	 * Refer ISSUE1:
	 * Hold the PHY in RESET for enough time till
	 * PHY is settled and ready
	 */
	if (delay && !on)
		udelay(delay);
#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
#endif
#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
#endif
#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
#endif

	/* Hold the PHY in RESET for enough time till DIR is high */
	/* Refer: ISSUE1 */
	if (delay && on)
		udelay(delay);
}
#else
#define omap_ehci_phy_reset(on, delay)	do {} while (0)
#endif

/* Reset is needed otherwise the kernel-driver will throw an error. */
int omap_ehci_hcd_stop(void)
{
	debug("Resetting OMAP EHCI\n");
	omap_ehci_phy_reset(1, 0);

	if (omap_uhh_reset() < 0)
		return -1;

	if (omap_ehci_tll_reset() < 0)
		return -1;

	return 0;
}

/*
 * Initialize the OMAP EHCI controller and PHY.
 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
 * See there for additional Copyrights.
 */
#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)

int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
		       struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	*hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
	*hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
#else
int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
{
#endif
	int ret;
	unsigned int i, reg = 0, rev = 0;

	debug("Initializing OMAP EHCI\n");

	ret = board_usb_init(index, USB_INIT_HOST);
	if (ret < 0)
		return ret;

	/* Put the PHY in RESET */
	omap_ehci_phy_reset(1, 10);

	ret = omap_uhh_reset();
	if (ret < 0)
		return ret;

	ret = omap_ehci_tll_reset();
	if (ret)
		return ret;

	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
		OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
		OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);

	/* Put UHH in NoIdle/NoStandby mode */
	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);

	/* setup ULPI bypass and burst configurations */
	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
		(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));

	rev = readl(&uhh->rev);
	if (rev == OMAP_USBHS_REV1) {
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	} else if (rev == OMAP_USBHS_REV2) {

		clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
					OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

	} else if (rev == OMAP_USBHS_REV2_1) {

		clrsetbits_le32(&reg,
				(OMAP_P1_MODE_CLEAR |
				 OMAP_P2_MODE_CLEAR |
				 OMAP_P3_MODE_CLEAR),
				OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
			setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	}

	debug("OMAP UHH_REVISION 0x%x\n", rev);
	writel(reg, &uhh->hostconfig);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
			omap_usbhs_hsic_init(i);

	omap_ehci_phy_reset(0, 10);

	/*
	 * An undocumented "feature" in the OMAP3 EHCI controller,
	 * causes suspended ports to be taken out of suspend when
	 * the USBCMD.Run/Stop bit is cleared (for example when
	 * we do ehci_bus_suspend).
	 * This breaks suspend-resume if the root-hub is allowed
	 * to suspend. Writing 1 to this undocumented register bit
	 * disables this feature and restores normal behavior.
	 */
	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
			omap_ehci_soft_phy_reset(i);

	debug("OMAP EHCI init done\n");
	return 0;
}

#if CONFIG_IS_ENABLED(DM_USB)

static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};

static void omap_usbhs_set_mode(u8 index, const char *mode)
{
	if (!strcmp(mode, "ehci-phy"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
	else if (!strcmp(mode, "ehci-tll"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
	else if (!strcmp(mode, "ehci-hsic"))
		usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
}

static int omap_usbhs_probe(struct udevice *dev)
{
	u8 i;
	const char *mode;
	char prop[11];

	/* Go through each port portX-mode to determing phy mode */
	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
		snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
		mode = dev_read_string(dev, prop);

		/* If the portX-mode exists, set the mode */
		if (mode)
			omap_usbhs_set_mode(i, mode);
	}

	return omap_ehci_hcd_init(0, &usbhs_bdata);
}

static const struct udevice_id omap_usbhs_dt_ids[] = {
	{ .compatible = "ti,usbhs-host" },
	{ }
};

U_BOOT_DRIVER(usb_omaphs_host) = {
	.name	= "usbhs-host",
	.id	= UCLASS_SIMPLE_BUS,
	.of_match = omap_usbhs_dt_ids,
	.probe	= omap_usbhs_probe,
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};

struct ehci_omap_priv_data {
	struct ehci_ctrl ctrl;
	struct omap_ehci *ehci;
#ifdef CONFIG_DM_REGULATOR
	struct udevice *vbus_supply;
#endif
	enum usb_init_type init_type;
	int portnr;
	struct phy phy[OMAP_HS_USB_PORTS];
	int nports;
};

static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);

	plat->init_type = USB_INIT_HOST;

	return 0;
}

static int omap_ehci_probe(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;

	priv->ehci = dev_read_addr_ptr(dev);
	priv->portnr = dev->seq;
	priv->init_type = plat->init_type;

	hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
	hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;

	return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}

static const struct udevice_id omap_ehci_dt_ids[] = {
	{ .compatible = "ti,ehci-omap" },
	{ }
};

U_BOOT_DRIVER(usb_omap_ehci) = {
	.name	= "omap-ehci",
	.id	= UCLASS_USB,
	.of_match = omap_ehci_dt_ids,
	.probe = omap_ehci_probe,
	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
	.platdata_auto	= sizeof(struct usb_platdata),
	.priv_auto	= sizeof(struct ehci_omap_priv_data),
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};

#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
29321c05 IY	2	/*
	3	* (C) Copyright 2011 Ilya Yanok, Emcraft Systems
	4	* (C) Copyright 2004-2008
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* Derived from Beagle Board code by
	8	* Sunil Kumar <[email protected]>
	9	* Shashi Ranjan <[email protected]>
	10	*
29321c05	11	*/
1a459660	12
29321c05	13	#include <common.h>
f7ae49fc	14	#include <log.h>
29321c05	15	#include <usb.h>
c05ed00a	16	#include <linux/delay.h>
43b62393 G	17	#include <usb/ulpi.h>
43b62393 G	18	#include <errno.h>
29321c05 IY	19	#include <asm/io.h>
29321c05 IY	20	#include <asm/gpio.h>
43b62393 G	21	#include <asm/arch/ehci.h>
43b62393 G	22	#include <asm/ehci-omap.h>
94ed6619 AF	23	#include <dm.h>
	24	#include <dm/device-internal.h>
	25	#include <dm/lists.h>
	26	#include <power/regulator.h>
676ae068 LS	27
676ae068 LS	28	#include "ehci.h"
29321c05	29
43b62393 G	30	static struct omap_uhh const uhh = (struct omap_uhh )OMAP_UHH_BASE;
	31	static struct omap_usbtll const usbtll = (struct omap_usbtll )OMAP_USBTLL_BASE;
	32	static struct omap_ehci const ehci = (struct omap_ehci )OMAP_EHCI_BASE;
	33
	34	static int omap_uhh_reset(void)
	35	{
835a5559 RQ	36	int timeout = 0;
	37	u32 rev;
	38
	39	rev = readl(&uhh->rev);
	40
	41	/* Soft RESET */
	42	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
	43
	44	switch (rev) {
	45	case OMAP_USBHS_REV1:
	46	/* Wait for soft RESET to complete */
	47	while (!(readl(&uhh->syss) & 0x1)) {
	48	if (timeout > 100) {
	49	printf("%s: RESET timeout\n", __func__);
	50	return -1;
	51	}
	52	udelay(10);
	53	timeout++;
	54	}
	55
	56	/* Set No-Idle, No-Standby */
	57	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	58	break;
	59
	60	default: /* Rev. 2 onwards */
	61
	62	udelay(2); /* Need to wait before accessing SYSCONFIG back */
	63
	64	/* Wait for soft RESET to complete */
	65	while ((readl(&uhh->sysc) & 0x1)) {
	66	if (timeout > 100) {
	67	printf("%s: RESET timeout\n", __func__);
	68	return -1;
	69	}
	70	udelay(10);
	71	timeout++;
	72	}
	73
	74	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	75	break;
	76	}
	77
43b62393 G	78	return 0;
	79	}
	80
	81	static int omap_ehci_tll_reset(void)
	82	{
	83	unsigned long init = get_timer(0);
	84
	85	/* perform TLL soft reset, and wait until reset is complete */
	86	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
	87
	88	/* Wait for TLL reset to complete */
	89	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
	90	if (get_timer(init) > CONFIG_SYS_HZ) {
	91	debug("OMAP EHCI error: timeout resetting TLL\n");
	92	return -EL3RST;
	93	}
	94
	95	return 0;
	96	}
	97
	98	static void omap_usbhs_hsic_init(int port)
	99	{
	100	unsigned int reg;
	101
	102	/* Enable channels now */
	103	reg = readl(&usbtll->channel_conf + port);
	104
	105	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
	106	\| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
	107	\| OMAP_TLL_CHANNEL_CONF_DRVVBUS
	108	\| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
	109	\| OMAP_TLL_CHANNEL_CONF_CHANEN));
	110
	111	writel(reg, &usbtll->channel_conf + port);
	112	}
	113
120503f3	114	#ifdef CONFIG_USB_ULPI
43b62393 G	115	static void omap_ehci_soft_phy_reset(int port)
	116	{
	117	struct ulpi_viewport ulpi_vp;
	118
	119	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	120	ulpi_vp.port_num = port;
	121
	122	ulpi_reset(&ulpi_vp);
	123	}
120503f3 DM	124	#else
	125	static void omap_ehci_soft_phy_reset(int port)
	126	{
	127	return;
	128	}
	129	#endif
43b62393	130
29321c05	131	#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) \|\| \
d3d037ae DM	132	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) \|\| \
d3d037ae DM	133	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
29321c05 IY	134	/* controls PHY(s) reset signal(s) */
	135	static inline void omap_ehci_phy_reset(int on, int delay)
	136	{
	137	/*
	138	* Refer ISSUE1:
	139	* Hold the PHY in RESET for enough time till
	140	* PHY is settled and ready
	141	*/
	142	if (delay && !on)
	143	udelay(delay);
	144	#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
	145	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
	146	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
	147	#endif
	148	#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
	149	gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
	150	gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
	151	#endif
d3d037ae DM	152	#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
	153	gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
	154	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
	155	#endif
29321c05 IY	156
	157	/* Hold the PHY in RESET for enough time till DIR is high */
	158	/* Refer: ISSUE1 */
	159	if (delay && on)
	160	udelay(delay);
	161	}
	162	#else
	163	#define omap_ehci_phy_reset(on, delay) do {} while (0)
	164	#endif
	165
	166	/* Reset is needed otherwise the kernel-driver will throw an error. */
43b62393	167	int omap_ehci_hcd_stop(void)
29321c05	168	{
43b62393	169	debug("Resetting OMAP EHCI\n");
29321c05	170	omap_ehci_phy_reset(1, 0);
43b62393 G	171
	172	if (omap_uhh_reset() < 0)
	173	return -1;
	174
	175	if (omap_ehci_tll_reset() < 0)
	176	return -1;
	177
29321c05 IY	178	return 0;
	179	}
	180
	181	/*
43b62393 G	182	* Initialize the OMAP EHCI controller and PHY.
43b62393 G	183	* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
29321c05 IY	184	* See there for additional Copyrights.
29321c05 IY	185	*/
94ed6619 AF	186	#if !CONFIG_IS_ENABLED(DM_USB) \|\| !CONFIG_IS_ENABLED(OF_CONTROL)
94ed6619 AF	187
16297cfb MZ	188	int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
16297cfb MZ	189	struct ehci_hccr hccr, struct ehci_hcor hcor)
29321c05	190	{
94ed6619 AF	191	hccr = (struct ehci_hccr )(OMAP_EHCI_BASE);
	192	hcor = (struct ehci_hcor )(OMAP_EHCI_BASE + 0x10);
	193	#else
	194	int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
	195	{
	196	#endif
29321c05	197	int ret;
43b62393	198	unsigned int i, reg = 0, rev = 0;
29321c05	199
43b62393	200	debug("Initializing OMAP EHCI\n");
29321c05	201
16297cfb	202	ret = board_usb_init(index, USB_INIT_HOST);
29321c05 IY	203	if (ret < 0)
	204	return ret;
	205
	206	/* Put the PHY in RESET */
	207	omap_ehci_phy_reset(1, 10);
	208
43b62393 G	209	ret = omap_uhh_reset();
	210	if (ret < 0)
	211	return ret;
29321c05	212
43b62393 G	213	ret = omap_ehci_tll_reset();
	214	if (ret)
	215	return ret;
29321c05 IY	216
	217	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP \|
	218	OMAP_USBTLL_SYSCONFIG_SIDLEMODE \|
43b62393	219	OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
29321c05 IY	220
29321c05 IY	221	/* Put UHH in NoIdle/NoStandby mode */
43b62393 G	222	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	223
	224	/* setup ULPI bypass and burst configurations */
	225	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
	226	(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN \|
	227	OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN \|
	228	OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
	229
	230	rev = readl(&uhh->rev);
	231	if (rev == OMAP_USBHS_REV1) {
	232	if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
	233	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	234	else
	235	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	236
	237	if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
	238	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
	239	else
90579fdd	240	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
43b62393 G	241
	242	if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
	243	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	244	else
90579fdd	245	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
43b62393	246	} else if (rev == OMAP_USBHS_REV2) {
d3d037ae	247
43b62393 G	248	clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR \| OMAP_P2_MODE_CLEAR),
	249	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	250
d3d037ae DM	251	/* Clear port mode fields for PHY mode */
	252
	253	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	254	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	255
	256	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	257	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	258
	259	} else if (rev == OMAP_USBHS_REV2_1) {
	260
	261	clrsetbits_le32(&reg,
	262	(OMAP_P1_MODE_CLEAR \|
	263	OMAP_P2_MODE_CLEAR \|
	264	OMAP_P3_MODE_CLEAR),
	265	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	266
	267	/* Clear port mode fields for PHY mode */
43b62393 G	268
	269	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	270	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	271
	272	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	273	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	274
	275	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
	276	setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	277	}
	278
	279	debug("OMAP UHH_REVISION 0x%x\n", rev);
	280	writel(reg, &uhh->hostconfig);
	281
	282	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	283	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
	284	omap_usbhs_hsic_init(i);
29321c05 IY	285
	286	omap_ehci_phy_reset(0, 10);
	287
43b62393 G	288	/*
	289	* An undocumented "feature" in the OMAP3 EHCI controller,
	290	* causes suspended ports to be taken out of suspend when
	291	* the USBCMD.Run/Stop bit is cleared (for example when
	292	* we do ehci_bus_suspend).
	293	* This breaks suspend-resume if the root-hub is allowed
	294	* to suspend. Writing 1 to this undocumented register bit
	295	* disables this feature and restores normal behavior.
	296	*/
	297	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
	298
	299	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	300	if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
	301	omap_ehci_soft_phy_reset(i);
	302
43b62393	303	debug("OMAP EHCI init done\n");
29321c05 IY	304	return 0;
29321c05 IY	305	}
94ed6619 AF	306
	307	#if CONFIG_IS_ENABLED(DM_USB)
	308
	309	static struct omap_usbhs_board_data usbhs_bdata = {
	310	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	311	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	312	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	313	};
	314
	315	static void omap_usbhs_set_mode(u8 index, const char *mode)
	316	{
	317	if (!strcmp(mode, "ehci-phy"))
	318	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
	319	else if (!strcmp(mode, "ehci-tll"))
	320	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
	321	else if (!strcmp(mode, "ehci-hsic"))
	322	usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
	323	}
	324
	325	static int omap_usbhs_probe(struct udevice *dev)
	326	{
	327	u8 i;
	328	const char *mode;
	329	char prop[11];
	330
	331	/* Go through each port portX-mode to determing phy mode */
	332	for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
	333	snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
	334	mode = dev_read_string(dev, prop);
	335
	336	/* If the portX-mode exists, set the mode */
	337	if (mode)
	338	omap_usbhs_set_mode(i, mode);
	339	}
	340
	341	return omap_ehci_hcd_init(0, &usbhs_bdata);
	342	}
	343
	344	static const struct udevice_id omap_usbhs_dt_ids[] = {
	345	{ .compatible = "ti,usbhs-host" },
	346	{ }
	347	};
	348
	349	U_BOOT_DRIVER(usb_omaphs_host) = {
	350	.name = "usbhs-host",
	351	.id = UCLASS_SIMPLE_BUS,
	352	.of_match = omap_usbhs_dt_ids,
	353	.probe = omap_usbhs_probe,
	354	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	355	};
	356
	357	struct ehci_omap_priv_data {
	358	struct ehci_ctrl ctrl;
	359	struct omap_ehci *ehci;
	360	#ifdef CONFIG_DM_REGULATOR
	361	struct udevice *vbus_supply;
	362	#endif
	363	enum usb_init_type init_type;
	364	int portnr;
	365	struct phy phy[OMAP_HS_USB_PORTS];
	366	int nports;
	367	};
	368
	369	static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
370	{
371	struct usb_platdata *plat = dev_get_platdata(dev);
372
373	plat->init_type = USB_INIT_HOST;
374
375	return 0;
376	}
377
378	static int omap_ehci_probe(struct udevice *dev)
379	{
380	struct usb_platdata *plat = dev_get_platdata(dev);
381	struct ehci_omap_priv_data *priv = dev_get_priv(dev);
382	struct ehci_hccr *hccr;
383	struct ehci_hcor *hcor;
384
8613c8d8	385	priv->ehci = dev_read_addr_ptr(dev);
94ed6619 AF	386	priv->portnr = dev->seq;
	387	priv->init_type = plat->init_type;
	388
	389	hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
	390	hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
	391
	392	return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
	393	}
	394
	395	static const struct udevice_id omap_ehci_dt_ids[] = {
	396	{ .compatible = "ti,ehci-omap" },
	397	{ }
	398	};
	399
	400	U_BOOT_DRIVER(usb_omap_ehci) = {
	401	.name = "omap-ehci",
	402	.id = UCLASS_USB,
	403	.of_match = omap_ehci_dt_ids,
	404	.probe = omap_ehci_probe,
	405	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
41575d8e SG	406	.platdata_auto = sizeof(struct usb_platdata),
41575d8e SG	407	.priv_auto = sizeof(struct ehci_omap_priv_data),
94ed6619 AF	408	.remove = ehci_deregister,
	409	.ops = &ehci_usb_ops,
	410	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	411	};
	412
	413	#endif