[u-boot.git] / drivers / usb / host / ehci-mx5.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2009 Daniel Mack <[email protected]>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <log.h>
#include <usb.h>
#include <errno.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <power/regulator.h>

#include "ehci.h"

#define MX5_USBOTHER_REGS_OFFSET 0x800


#define MXC_OTG_OFFSET			0
#define MXC_H1_OFFSET			0x200
#define MXC_H2_OFFSET			0x400
#define MXC_H3_OFFSET			0x600

#define MXC_USBCTRL_OFFSET		0
#define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
#define MXC_USB_CTRL_1_OFFSET		0x10
#define MXC_USBH2CTRL_OFFSET		0x14
#define MXC_USBH3CTRL_OFFSET		0x18

/* USB_CTRL */
/* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
/* OTG power mask */
#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
/* OTG power pin polarity */
#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)
/* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
/* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
/* HOST1 power mask */
#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
/* HOST1 power pin polarity */
#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)

/* USB_PHY_CTRL_FUNC */
/* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)
/* OTG Disable Overcurrent Event */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
/* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_POL_BIT		(1 << 6)
/* UH1 Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT		(1 << 5)
/* OTG Power Pin Polarity */
#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)

/* USBH2CTRL */
#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)

/* USBH3CTRL */
#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)

/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

int mxc_set_usbcontrol(int port, unsigned int flags)
{
	unsigned int v;
	void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
	void __iomem *usbother_base;
	int ret = 0;

	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	switch (port) {
	case 0:	/* OTG port */
		if (flags & MXC_EHCI_INTERNAL_PHY) {
			v = __raw_readl(usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);
			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				/* OC/USBPWR is used */
				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
			else
				/* OC/USBPWR is not used */
				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);

			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				v &= ~MXC_OTG_UCTRL_OPM_BIT;
			else
				v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
#ifdef CONFIG_MX53
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
		}
		break;
	case 1:	/* Host 1 ULPI */
#ifdef CONFIG_MX51
		/* The clock for the USBH1 ULPI port will come externally
		   from the PHY. */
		v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
		__raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
				MXC_USB_CTRL_1_OFFSET);
#endif

		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
		else
			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
		else
			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H1_OC_POL_BIT;
		else
			v &= ~MXC_H1_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
		__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

		break;
	case 2: /* Host 2 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
		else
			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
		break;
#ifdef CONFIG_MX53
	case 3: /* Host 3 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
		break;
#endif
	}

	return ret;
}

int __weak board_ehci_hcd_init(int port)
{
	return 0;
}

void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
{
}

__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
				   uint32_t *reg)
{
	mdelay(50);
}

#if !CONFIG_IS_ENABLED(DM_USB)
static const struct ehci_ops mx5_ehci_ops = {
	.powerup_fixup		= mx5_ehci_powerup_fixup,
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;

	/* The only user for this is efikamx-usb */
	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
	set_usboh3_clk();
	enable_usboh3_clk(true);
	set_usb_phy_clk();
	enable_usb_phy1_clk(true);
	enable_usb_phy2_clk(true);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * CONFIG_MXC_USB_PORT));
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);

	return 0;
}

int ehci_hcd_stop(int index)
{
	return 0;
}
#else /* CONFIG_IS_ENABLED(DM_USB) */
struct ehci_mx5_priv_data {
	struct ehci_ctrl ctrl;
	struct usb_ehci *ehci;
	struct udevice *vbus_supply;
	enum usb_init_type init_type;
	int portnr;
};

static const struct ehci_ops mx5_ehci_ops = {
	.powerup_fixup		= mx5_ehci_powerup_fixup,
};

static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	const char *mode;

	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
	if (mode) {
		if (strcmp(mode, "peripheral") == 0)
			plat->init_type = USB_INIT_DEVICE;
		else if (strcmp(mode, "host") == 0)
			plat->init_type = USB_INIT_HOST;
		else
			return -EINVAL;
	}

	return 0;
}

static int ehci_usb_probe(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
	struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
	enum usb_init_type type = plat->init_type;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	int ret;

	set_usboh3_clk();
	enable_usboh3_clk(true);
	set_usb_phy_clk();
	enable_usb_phy1_clk(true);
	enable_usb_phy2_clk(true);
	mdelay(1);

	priv->ehci = ehci;
	priv->portnr = dev->seq;
	priv->init_type = type;

	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &priv->vbus_supply);
	if (ret)
		debug("%s: No vbus supply\n", dev->name);

	if (!ret && priv->vbus_supply) {
		ret = regulator_set_enable(priv->vbus_supply,
					   (type == USB_INIT_DEVICE) ?
					   false : true);
		if (ret) {
			puts("Error enabling VBUS supply\n");
			return ret;
		}
	}

	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	hcor = (struct ehci_hcor *)((uint32_t)hccr +
			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
			     priv->init_type);
}

static const struct udevice_id mx5_usb_ids[] = {
	{ .compatible = "fsl,imx53-usb" },
	{ }
};

U_BOOT_DRIVER(usb_mx5) = {
	.name	= "ehci_mx5",
	.id	= UCLASS_USB,
	.of_match = mx5_usb_ids,
	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
	.probe	= ehci_usb_probe,
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.platdata_auto	= sizeof(struct usb_platdata),
	.priv_auto	= sizeof(struct ehci_mx5_priv_data),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* !CONFIG_IS_ENABLED(DM_USB) */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1ca56202 WG	2	/*
	3	* Copyright (c) 2009 Daniel Mack <[email protected]>
	4	* Copyright (C) 2010 Freescale Semiconductor, Inc.
1ca56202 WG	5	*/
	6
	7	#include <common.h>
f7ae49fc	8	#include <log.h>
1ca56202 WG	9	#include <usb.h>
	10	#include <errno.h>
	11	#include <linux/compiler.h>
c05ed00a	12	#include <linux/delay.h>
e162c6b1	13	#include <usb/ehci-ci.h>
1ca56202 WG	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/clock.h>
22988766 LM	17	#include <dm.h>
22988766 LM	18	#include <power/regulator.h>
1ca56202 WG	19
1ca56202 WG	20	#include "ehci.h"
1ca56202 WG	21
	22	#define MX5_USBOTHER_REGS_OFFSET 0x800
	23
	24
bdc52020 BT	25	#define MXC_OTG_OFFSET 0
	26	#define MXC_H1_OFFSET 0x200
	27	#define MXC_H2_OFFSET 0x400
2cfe0b8f	28	#define MXC_H3_OFFSET 0x600
1ca56202 WG	29
	30	#define MXC_USBCTRL_OFFSET 0
	31	#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
	32	#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
	33	#define MXC_USB_CTRL_1_OFFSET 0x10
	34	#define MXC_USBH2CTRL_OFFSET 0x14
2cfe0b8f	35	#define MXC_USBH3CTRL_OFFSET 0x18
1ca56202 WG	36
1ca56202 WG	37	/* USB_CTRL */
bdc52020 BT	38	/* OTG wakeup intr enable */
	39	#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
	40	/* OTG power mask */
	41	#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
31ac2d0c BT	42	/* OTG power pin polarity */
31ac2d0c BT	43	#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
bdc52020 BT	44	/* Host1 ULPI interrupt enable */
	45	#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
	46	/* HOST1 wakeup intr enable */
	47	#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
	48	/* HOST1 power mask */
	49	#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
31ac2d0c BT	50	/* HOST1 power pin polarity */
31ac2d0c BT	51	#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
1ca56202 WG	52
1ca56202 WG	53	/* USB_PHY_CTRL_FUNC */
31ac2d0c BT	54	/* OTG Polarity of Overcurrent */
31ac2d0c BT	55	#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
bdc52020 BT	56	/* OTG Disable Overcurrent Event */
bdc52020 BT	57	#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
31ac2d0c BT	58	/* UH1 Polarity of Overcurrent */
31ac2d0c BT	59	#define MXC_H1_OC_POL_BIT (1 << 6)
bdc52020 BT	60	/* UH1 Disable Overcurrent Event */
bdc52020 BT	61	#define MXC_H1_OC_DIS_BIT (1 << 5)
31ac2d0c BT	62	/* OTG Power Pin Polarity */
31ac2d0c BT	63	#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
1ca56202 WG	64
1ca56202 WG	65	/* USBH2CTRL */
31ac2d0c	66	#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
2cfe0b8f	67	#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
bdc52020 BT	68	#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
	69	#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
	70	#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
31ac2d0c	71	#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
1ca56202	72
2cfe0b8f	73	/* USBH3CTRL */
31ac2d0c	74	#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
2cfe0b8f BT	75	#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
	76	#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
	77	#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
31ac2d0c	78	#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
2cfe0b8f	79
1ca56202	80	/* USB_CTRL_1 */
bdc52020	81	#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
1ca56202 WG	82
	83	int mxc_set_usbcontrol(int port, unsigned int flags)
	84	{
	85	unsigned int v;
	86	void __iomem usb_base = (void __iomem )OTG_BASE_ADDR;
	87	void __iomem *usbother_base;
	88	int ret = 0;
	89
	90	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	91
	92	switch (port) {
	93	case 0: /* OTG port */
	94	if (flags & MXC_EHCI_INTERNAL_PHY) {
	95	v = __raw_readl(usbother_base +
	96	MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	97	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	98	v \|= MXC_OTG_PHYCTRL_OC_POL_BIT;
	99	else
	100	v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
1ca56202	101	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202 WG	102	/* OC/USBPWR is used */
1ca56202 WG	103	v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
7d42432d BT	104	else
	105	/* OC/USBPWR is not used */
	106	v \|= MXC_OTG_PHYCTRL_OC_DIS_BIT;
31ac2d0c BT	107	#ifdef CONFIG_MX51
	108	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	109	v \|= MXC_OTG_PHYCTRL_PWR_POL_BIT;
	110	else
	111	v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
	112	#endif
1ca56202 WG	113	__raw_writel(v, usbother_base +
	114	MXC_USB_PHY_CTR_FUNC_OFFSET);
	115
	116	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	117	#ifdef CONFIG_MX51
1ca56202	118	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202	119	v &= ~MXC_OTG_UCTRL_OPM_BIT;
394c00dc BT	120	else
394c00dc BT	121	v \|= MXC_OTG_UCTRL_OPM_BIT;
31ac2d0c BT	122	#endif
	123	#ifdef CONFIG_MX53
	124	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	125	v \|= MXC_OTG_UCTRL_O_PWR_POL_BIT;
	126	else
	127	v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
661052f4	128	#endif
1ca56202 WG	129	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	130	}
	131	break;
bdc52020	132	case 1: /* Host 1 ULPI */
1ca56202 WG	133	#ifdef CONFIG_MX51
	134	/* The clock for the USBH1 ULPI port will come externally
	135	from the PHY. */
	136	v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
	137	__raw_writel(v \| MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
	138	MXC_USB_CTRL_1_OFFSET);
	139	#endif
	140
	141	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	142	#ifdef CONFIG_MX51
1ca56202	143	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	144	v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
1ca56202	145	else
bdc52020	146	v \|= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
31ac2d0c BT	147	#endif
	148	#ifdef CONFIG_MX53
	149	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	150	v \|= MXC_H1_UCTRL_H1_PWR_POL_BIT;
	151	else
	152	v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
661052f4	153	#endif
1ca56202 WG	154	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	155
	156	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	157	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	158	v \|= MXC_H1_OC_POL_BIT;
	159	else
	160	v &= ~MXC_H1_OC_POL_BIT;
1ca56202 WG	161	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	162	v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
	163	else
	164	v \|= MXC_H1_OC_DIS_BIT; /* OC is not used */
	165	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	166
	167	break;
	168	case 2: /* Host 2 ULPI */
	169	v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
661052f4	170	#ifdef CONFIG_MX51
1ca56202	171	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	172	v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
1ca56202	173	else
bdc52020	174	v \|= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
2cfe0b8f BT	175	#endif
2cfe0b8f BT	176	#ifdef CONFIG_MX53
31ac2d0c BT	177	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	178	v \|= MXC_H2_UCTRL_H2_OC_POL_BIT;
	179	else
	180	v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
2cfe0b8f BT	181	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	182	v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
	183	else
	184	v \|= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	185	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	186	v \|= MXC_H2_UCTRL_H2_PWR_POL_BIT;
	187	else
	188	v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
661052f4	189	#endif
1ca56202 WG	190	__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
1ca56202 WG	191	break;
2cfe0b8f BT	192	#ifdef CONFIG_MX53
	193	case 3: /* Host 3 ULPI */
	194	v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
31ac2d0c BT	195	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	196	v \|= MXC_H3_UCTRL_H3_OC_POL_BIT;
	197	else
	198	v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
2cfe0b8f BT	199	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	200	v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
	201	else
	202	v \|= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	203	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	204	v \|= MXC_H3_UCTRL_H3_PWR_POL_BIT;
	205	else
	206	v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
2cfe0b8f BT	207	__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
	208	break;
	209	#endif
1ca56202 WG	210	}
	211
	212	return ret;
	213	}
	214
f22e4fae	215	int __weak board_ehci_hcd_init(int port)
1b80f270	216	{
f22e4fae	217	return 0;
1b80f270 MV	218	}
1b80f270 MV	219
f22e4fae BT	220	void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
	221	{
	222	}
1b80f270	223
deb8508c SG	224	__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl ctrl, uint32_t status_reg,
	225	uint32_t *reg)
	226	{
	227	mdelay(50);
	228	}
	229
22988766	230	#if !CONFIG_IS_ENABLED(DM_USB)
deb8508c SG	231	static const struct ehci_ops mx5_ehci_ops = {
	232	.powerup_fixup = mx5_ehci_powerup_fixup,
	233	};
	234
127efc4f TK	235	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	236	struct ehci_hccr hccr, struct ehci_hcor hcor)
1ca56202 WG	237	{
1ca56202 WG	238	struct usb_ehci *ehci;
1ca56202	239
deb8508c SG	240	/* The only user for this is efikamx-usb */
deb8508c SG	241	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
1ca56202	242	set_usboh3_clk();
76b6b196	243	enable_usboh3_clk(true);
414e1660	244	set_usb_phy_clk();
76b6b196 FE	245	enable_usb_phy1_clk(true);
76b6b196 FE	246	enable_usb_phy2_clk(true);
1ca56202 WG	247	mdelay(1);
1ca56202 WG	248
1b80f270	249	/* Do board specific initialization */
1ca56202 WG	250	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
	251
	252	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
	253	(0x200 * CONFIG_MXC_USB_PORT));
676ae068 LS	254	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	255	hcor = (struct ehci_hcor )((uint32_t)*hccr +
	256	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
1ca56202 WG	257	setbits_le32(&ehci->usbmode, CM_HOST);
	258
	259	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	260	setbits_le32(&ehci->portsc, USB_EN);
	261
	262	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
1ca56202 WG	263	mdelay(10);
1ca56202 WG	264
1b80f270 MV	265	/* Do board specific post-initialization */
	266	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
	267
1ca56202 WG	268	return 0;
	269	}
	270
676ae068	271	int ehci_hcd_stop(int index)
1ca56202 WG	272	{
	273	return 0;
	274	}
22988766 LM	275	#else /* CONFIG_IS_ENABLED(DM_USB) */
	276	struct ehci_mx5_priv_data {
	277	struct ehci_ctrl ctrl;
	278	struct usb_ehci *ehci;
	279	struct udevice *vbus_supply;
	280	enum usb_init_type init_type;
	281	int portnr;
	282	};
	283
	284	static const struct ehci_ops mx5_ehci_ops = {
	285	.powerup_fixup = mx5_ehci_powerup_fixup,
	286	};
	287
	288	static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
	289	{
	290	struct usb_platdata *plat = dev_get_platdata(dev);
	291	const char *mode;
	292
	293	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
	294	if (mode) {
	295	if (strcmp(mode, "peripheral") == 0)
	296	plat->init_type = USB_INIT_DEVICE;
	297	else if (strcmp(mode, "host") == 0)
	298	plat->init_type = USB_INIT_HOST;
	299	else
	300	return -EINVAL;
	301	}
	302
	303	return 0;
	304	}
	305
	306	static int ehci_usb_probe(struct udevice *dev)
	307	{
	308	struct usb_platdata *plat = dev_get_platdata(dev);
8613c8d8	309	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
22988766 LM	310	struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
	311	enum usb_init_type type = plat->init_type;
	312	struct ehci_hccr *hccr;
	313	struct ehci_hcor *hcor;
	314	int ret;
	315
	316	set_usboh3_clk();
	317	enable_usboh3_clk(true);
	318	set_usb_phy_clk();
	319	enable_usb_phy1_clk(true);
	320	enable_usb_phy2_clk(true);
	321	mdelay(1);
	322
	323	priv->ehci = ehci;
	324	priv->portnr = dev->seq;
	325	priv->init_type = type;
	326
	327	ret = device_get_supply_regulator(dev, "vbus-supply",
	328	&priv->vbus_supply);
	329	if (ret)
	330	debug("%s: No vbus supply\n", dev->name);
	331
	332	if (!ret && priv->vbus_supply) {
	333	ret = regulator_set_enable(priv->vbus_supply,
	334	(type == USB_INIT_DEVICE) ?
	335	false : true);
	336	if (ret) {
	337	puts("Error enabling VBUS supply\n");
	338	return ret;
	339	}
	340	}
	341
	342	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	343	hcor = (struct ehci_hcor *)((uint32_t)hccr +
	344	HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
	345	setbits_le32(&ehci->usbmode, CM_HOST);
	346
	347	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	348	setbits_le32(&ehci->portsc, USB_EN);
	349
	350	mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
	351	mdelay(10);
	352
	353	return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
	354	priv->init_type);
	355	}
	356
	357	static const struct udevice_id mx5_usb_ids[] = {
	358	{ .compatible = "fsl,imx53-usb" },
	359	{ }
	360	};
	361
	362	U_BOOT_DRIVER(usb_mx5) = {
	363	.name = "ehci_mx5",
	364	.id = UCLASS_USB,
	365	.of_match = mx5_usb_ids,
	366	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
	367	.probe = ehci_usb_probe,
	368	.remove = ehci_deregister,
	369	.ops = &ehci_usb_ops,
41575d8e SG	370	.platdata_auto = sizeof(struct usb_platdata),
41575d8e SG	371	.priv_auto = sizeof(struct ehci_mx5_priv_data),
22988766 LM	372	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	373	};
	374	#endif /* !CONFIG_IS_ENABLED(DM_USB) */