[u-boot.git] / drivers / mailbox / stm32-ipcc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <mailbox-uclass.h>
#include <malloc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>

/*
 * IPCC has one set of registers per CPU
 * IPCC_PROC_OFFST allows to define cpu registers set base address
 * according to the assigned proc_id.
 */

#define IPCC_PROC_OFFST		0x010

#define IPCC_XSCR		0x008
#define IPCC_XTOYSR		0x00c

#define IPCC_HWCFGR		0x3f0
#define IPCFGR_CHAN_MASK	GENMASK(7, 0)

#define RX_BIT_CHAN(chan)	BIT(chan)
#define TX_BIT_SHIFT		16
#define TX_BIT_CHAN(chan)	BIT(TX_BIT_SHIFT + (chan))

#define STM32_MAX_PROCS		2

struct stm32_ipcc {
	void __iomem *reg_base;
	void __iomem *reg_proc;
	u32 proc_id;
	u32 n_chans;
};

static int stm32_ipcc_request(struct mbox_chan *chan)
{
	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);

	debug("%s(chan=%p)\n", __func__, chan);

	if (chan->id >= ipcc->n_chans) {
		debug("%s failed to request channel: %ld\n",
		      __func__, chan->id);
		return -EINVAL;
	}

	return 0;
}

static int stm32_ipcc_free(struct mbox_chan *chan)
{
	debug("%s(chan=%p)\n", __func__, chan);

	return 0;
}

static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
{
	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);

	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);

	if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
		return -EBUSY;

	/* set channel n occupied */
	setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));

	return 0;
}

static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
{
	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
	u32 val;
	int proc_offset;

	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);

	/* read 'channel occupied' status from other proc */
	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
	val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);

	if (!(val & BIT(chan->id)))
		return -ENODATA;

	setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));

	return 0;
}

static int stm32_ipcc_probe(struct udevice *dev)
{
	struct stm32_ipcc *ipcc = dev_get_priv(dev);
	fdt_addr_t addr;
	struct clk clk;
	int ret;

	debug("%s(dev=%p)\n", __func__, dev);

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	ipcc->reg_base = (void __iomem *)addr;

	/* proc_id */
	ret = dev_read_u32_index(dev, "st,proc_id", 1, &ipcc->proc_id);
	if (ret) {
		dev_dbg(dev, "Missing st,proc_id\n");
		return -EINVAL;
	}

	if (ipcc->proc_id >= STM32_MAX_PROCS) {
		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
		return -EINVAL;
	}

	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return ret;

	ret = clk_enable(&clk);
	if (ret)
		goto clk_free;

	/* get channel number */
	ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
	ipcc->n_chans &= IPCFGR_CHAN_MASK;

	return 0;

clk_free:
	clk_free(&clk);

	return ret;
}

static const struct udevice_id stm32_ipcc_ids[] = {
	{ .compatible = "st,stm32mp1-ipcc" },
	{ }
};

struct mbox_ops stm32_ipcc_mbox_ops = {
	.request = stm32_ipcc_request,
	.rfree = stm32_ipcc_free,
	.send = stm32_ipcc_send,
	.recv = stm32_ipcc_recv,
};

U_BOOT_DRIVER(stm32_ipcc) = {
	.name = "stm32_ipcc",
	.id = UCLASS_MAILBOX,
	.of_match = stm32_ipcc_ids,
	.probe = stm32_ipcc_probe,
	.priv_auto	= sizeof(struct stm32_ipcc),
	.ops = &stm32_ipcc_mbox_ops,
};
Commit	Line	Data
01964d8e FD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
	8	#include <dm.h>
f7ae49fc	9	#include <log.h>
01964d8e	10	#include <mailbox-uclass.h>
336d4615	11	#include <malloc.h>
01964d8e	12	#include <asm/io.h>
336d4615	13	#include <dm/device_compat.h>
cd93d625	14	#include <linux/bitops.h>
01964d8e FD	15
	16	/*
	17	* IPCC has one set of registers per CPU
	18	* IPCC_PROC_OFFST allows to define cpu registers set base address
	19	* according to the assigned proc_id.
	20	*/
	21
	22	#define IPCC_PROC_OFFST 0x010
	23
	24	#define IPCC_XSCR 0x008
	25	#define IPCC_XTOYSR 0x00c
	26
	27	#define IPCC_HWCFGR 0x3f0
	28	#define IPCFGR_CHAN_MASK GENMASK(7, 0)
	29
	30	#define RX_BIT_CHAN(chan) BIT(chan)
	31	#define TX_BIT_SHIFT 16
	32	#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
	33
	34	#define STM32_MAX_PROCS 2
	35
	36	struct stm32_ipcc {
	37	void __iomem *reg_base;
	38	void __iomem *reg_proc;
	39	u32 proc_id;
	40	u32 n_chans;
	41	};
	42
	43	static int stm32_ipcc_request(struct mbox_chan *chan)
	44	{
	45	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
	46
	47	debug("%s(chan=%p)\n", __func__, chan);
	48
	49	if (chan->id >= ipcc->n_chans) {
	50	debug("%s failed to request channel: %ld\n",
	51	__func__, chan->id);
	52	return -EINVAL;
	53	}
	54
	55	return 0;
	56	}
	57
	58	static int stm32_ipcc_free(struct mbox_chan *chan)
	59	{
	60	debug("%s(chan=%p)\n", __func__, chan);
	61
	62	return 0;
	63	}
	64
	65	static int stm32_ipcc_send(struct mbox_chan chan, const void data)
	66	{
	67	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
	68
	69	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
	70
	71	if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
	72	return -EBUSY;
	73
	74	/* set channel n occupied */
	75	setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
	76
	77	return 0;
	78	}
79
80	static int stm32_ipcc_recv(struct mbox_chan chan, void data)
81	{
82	struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
83	u32 val;
84	int proc_offset;
85
86	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
87
88	/* read 'channel occupied' status from other proc */
89	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
90	val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
91
92	if (!(val & BIT(chan->id)))
93	return -ENODATA;
94
95	setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
96
97	return 0;
98	}
99
100	static int stm32_ipcc_probe(struct udevice *dev)
101	{
102	struct stm32_ipcc *ipcc = dev_get_priv(dev);
103	fdt_addr_t addr;
01964d8e	104	struct clk clk;
04e29ca5	105	int ret;
01964d8e FD	106
	107	debug("%s(dev=%p)\n", __func__, dev);
	108
	109	addr = dev_read_addr(dev);
	110	if (addr == FDT_ADDR_T_NONE)
	111	return -EINVAL;
	112
	113	ipcc->reg_base = (void __iomem *)addr;
	114
	115	/* proc_id */
04e29ca5 PD	116	ret = dev_read_u32_index(dev, "st,proc_id", 1, &ipcc->proc_id);
04e29ca5 PD	117	if (ret) {
01964d8e FD	118	dev_dbg(dev, "Missing st,proc_id\n");
	119	return -EINVAL;
	120	}
	121
01964d8e FD	122	if (ipcc->proc_id >= STM32_MAX_PROCS) {
	123	dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
	124	return -EINVAL;
	125	}
	126
	127	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
	128
	129	ret = clk_get_by_index(dev, 0, &clk);
	130	if (ret)
	131	return ret;
	132
	133	ret = clk_enable(&clk);
	134	if (ret)
	135	goto clk_free;
	136
	137	/* get channel number */
	138	ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
	139	ipcc->n_chans &= IPCFGR_CHAN_MASK;
	140
	141	return 0;
	142
	143	clk_free:
	144	clk_free(&clk);
	145
	146	return ret;
	147	}
	148
	149	static const struct udevice_id stm32_ipcc_ids[] = {
	150	{ .compatible = "st,stm32mp1-ipcc" },
	151	{ }
	152	};
	153
	154	struct mbox_ops stm32_ipcc_mbox_ops = {
	155	.request = stm32_ipcc_request,
cc92c3cc	156	.rfree = stm32_ipcc_free,
01964d8e FD	157	.send = stm32_ipcc_send,
	158	.recv = stm32_ipcc_recv,
	159	};
	160
	161	U_BOOT_DRIVER(stm32_ipcc) = {
	162	.name = "stm32_ipcc",
	163	.id = UCLASS_MAILBOX,
	164	.of_match = stm32_ipcc_ids,
	165	.probe = stm32_ipcc_probe,
41575d8e	166	.priv_auto = sizeof(struct stm32_ipcc),
01964d8e FD	167	.ops = &stm32_ipcc_mbox_ops,
01964d8e FD	168	};