[u-boot.git] / arch / arm / dts / zynq-7000.dtsi

/*
 * Xilinx Zynq 7000 DTSI
 * Describes the hardware common to all Zynq 7000-based boards.
 *
 * Copyright (C) 2013 Xilinx, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/include/ "skeleton.dtsi"

/ {
	compatible = "xlnx,zynq-7000";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			clocks = <&clkc 3>;
			clock-latency = <1000>;
			cpu0-supply = <&regulator_vccpint>;
			operating-points = <
				/* kHz    uV */
				666667  1000000
				333334  1000000
			>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			clocks = <&clkc 3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 5 4>, <0 6 4>;
		interrupt-parent = <&intc>;
		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
	};

	regulator_vccpint: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		adc: adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0 7 4>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 12>;
		};

		can0: can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 19>, <&clkc 36>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0 28 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can1: can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 20>, <&clkc 37>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0 51 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		gpio0: gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <2>;
			clocks = <&clkc 42>;
			gpio-controller;
			interrupt-parent = <&intc>;
			interrupts = <0 20 4>;
			reg = <0xe000a000 0x1000>;
		};

		i2c0: i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 38>;
			interrupt-parent = <&intc>;
			interrupts = <0 25 4>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 39>;
			interrupt-parent = <&intc>;
			interrupts = <0 48 4>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		L2: cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			arm,data-latency = <3 2 2>;
			arm,tag-latency = <2 2 2>;
			cache-unified;
			cache-level = <2>;
		};

		mc: memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		uart0: serial@e0000000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 23>, <&clkc 40>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0000000 0x1000>;
			interrupts = <0 27 4>;
		};

		uart1: serial@e0001000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 24>, <&clkc 41>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0001000 0x1000>;
			interrupts = <0 50 4>;
		};

		spi0: spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 26 4>;
			clocks = <&clkc 25>, <&clkc 34>;
			clock-names = "ref_clk", "pclk";
			spi-max-frequency = <166666700>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 49 4>;
			clocks = <&clkc 26>, <&clkc 35>;
			clock-names = "ref_clk", "pclk";
			spi-max-frequency = <166666700>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem0: ethernet@e000b000 {
			compatible = "cdns,gem";
			reg = <0xe000b000 0x4000>;
			status = "disabled";
			interrupts = <0 22 4>;
			clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
			clock-names = "pclk", "hclk", "tx_clk";
		};

		gem1: ethernet@e000c000 {
			compatible = "cdns,gem";
			reg = <0xe000c000 0x4000>;
			status = "disabled";
			interrupts = <0 45 4>;
			clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
			clock-names = "pclk", "hclk", "tx_clk";
		};

		sdhci0: sdhci@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 21>, <&clkc 32>;
			interrupt-parent = <&intc>;
			interrupts = <0 24 4>;
			reg = <0xe0100000 0x1000>;
		} ;

		sdhci1: sdhci@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 22>, <&clkc 33>;
			interrupt-parent = <&intc>;
			interrupts = <0 47 4>;
			reg = <0xe0101000 0x1000>;
		} ;

		slcr: slcr@f8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,zynq-slcr", "syscon";
			reg = <0xF8000000 0x1000>;
			ranges;
			clkc: clkc@100 {
				#clock-cells = <1>;
				compatible = "xlnx,ps7-clkc";
				ps-clk-frequency = <33333333>;
				fclk-enable = <0>;
				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
						"gem1_aper", "sdio0_aper", "sdio1_aper",
						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
						"dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
			};
		};

		dmac_s: dmac@f8003000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <&intc>;
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
				"dma4", "dma5", "dma6", "dma7";
			interrupts = <0 13 4>,
			             <0 14 4>, <0 15 4>,
			             <0 16 4>, <0 17 4>,
			             <0 40 4>, <0 41 4>,
			             <0 42 4>, <0 43 4>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <4>;
			clocks = <&clkc 27>;
			clock-names = "apb_pclk";
		};

		devcfg: devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			reg = <0xf8007000 0x100>;
		};

		global_timer: timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <1 11 0x301>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 4>;
		};

		ttc0: timer@f8001000 {
			interrupt-parent = <&intc>;
			interrupts = < 0 10 4 0 11 4 0 12 4 >;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8001000 0x1000>;
		};

		ttc1: timer@f8002000 {
			interrupt-parent = <&intc>;
			interrupts = < 0 37 4 0 38 4 0 39 4 >;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8002000 0x1000>;
		};

		scutimer: timer@f8f00600 {
			interrupt-parent = <&intc>;
			interrupts = < 1 13 0x301 >;
			compatible = "arm,cortex-a9-twd-timer";
			reg = < 0xf8f00600 0x20 >;
			clocks = <&clkc 4>;
		} ;

		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 28>;
			interrupt-parent = <&intc>;
			interrupts = <0 21 4>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
		};

		usb1: usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 29>;
			interrupt-parent = <&intc>;
			interrupts = <0 44 4>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog0: watchdog@f8005000 {
			clocks = <&clkc 45>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <&intc>;
			interrupts = <0 9 1>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <10>;
		};
	};
};
Commit	Line	Data
f8f36c5d JT	1	/*
	2	* Xilinx Zynq 7000 DTSI
	3	* Describes the hardware common to all Zynq 7000-based boards.
	4	*
	5	* Copyright (C) 2013 Xilinx, Inc.
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	/include/ "skeleton.dtsi"
	10
	11	/ {
	12	compatible = "xlnx,zynq-7000";
580a54c5 MY	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	compatible = "arm,cortex-a9";
	20	device_type = "cpu";
	21	reg = <0>;
	22	clocks = <&clkc 3>;
	23	clock-latency = <1000>;
bece06ce	24	cpu0-supply = <&regulator_vccpint>;
580a54c5 MY	25	operating-points = <
	26	/* kHz uV */
	27	666667 1000000
	28	333334 1000000
580a54c5 MY	29	>;
	30	};
	31
	32	cpu@1 {
	33	compatible = "arm,cortex-a9";
	34	device_type = "cpu";
	35	reg = <1>;
	36	clocks = <&clkc 3>;
	37	};
	38	};
	39
	40	pmu {
	41	compatible = "arm,cortex-a9-pmu";
	42	interrupts = <0 5 4>, <0 6 4>;
	43	interrupt-parent = <&intc>;
	44	reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
	45	};
	46
bece06ce MS	47	regulator_vccpint: fixedregulator@0 {
	48	compatible = "regulator-fixed";
	49	regulator-name = "VCCPINT";
	50	regulator-min-microvolt = <1000000>;
	51	regulator-max-microvolt = <1000000>;
	52	regulator-boot-on;
	53	regulator-always-on;
	54	};
	55
580a54c5 MY	56	amba {
	57	compatible = "simple-bus";
	58	#address-cells = <1>;
	59	#size-cells = <1>;
	60	interrupt-parent = <&intc>;
	61	ranges;
	62
fb1a5061 MS	63	adc: adc@f8007100 {
	64	compatible = "xlnx,zynq-xadc-1.00.a";
	65	reg = <0xf8007100 0x20>;
	66	interrupts = <0 7 4>;
	67	interrupt-parent = <&intc>;
	68	clocks = <&clkc 12>;
	69	};
	70
	71	can0: can@e0008000 {
	72	compatible = "xlnx,zynq-can-1.0";
	73	status = "disabled";
	74	clocks = <&clkc 19>, <&clkc 36>;
	75	clock-names = "can_clk", "pclk";
	76	reg = <0xe0008000 0x1000>;
	77	interrupts = <0 28 4>;
	78	interrupt-parent = <&intc>;
	79	tx-fifo-depth = <0x40>;
	80	rx-fifo-depth = <0x40>;
	81	};
	82
	83	can1: can@e0009000 {
	84	compatible = "xlnx,zynq-can-1.0";
	85	status = "disabled";
	86	clocks = <&clkc 20>, <&clkc 37>;
	87	clock-names = "can_clk", "pclk";
	88	reg = <0xe0009000 0x1000>;
	89	interrupts = <0 51 4>;
	90	interrupt-parent = <&intc>;
	91	tx-fifo-depth = <0x40>;
	92	rx-fifo-depth = <0x40>;
	93	};
	94
	95	gpio0: gpio@e000a000 {
	96	compatible = "xlnx,zynq-gpio-1.0";
	97	#gpio-cells = <2>;
	98	clocks = <&clkc 42>;
	99	gpio-controller;
	100	interrupt-parent = <&intc>;
	101	interrupts = <0 20 4>;
	102	reg = <0xe000a000 0x1000>;
	103	};
	104
a0cb47f1	105	i2c0: i2c@e0004000 {
580a54c5 MY	106	compatible = "cdns,i2c-r1p10";
	107	status = "disabled";
	108	clocks = <&clkc 38>;
	109	interrupt-parent = <&intc>;
	110	interrupts = <0 25 4>;
	111	reg = <0xe0004000 0x1000>;
	112	#address-cells = <1>;
	113	#size-cells = <0>;
	114	};
	115
a0cb47f1	116	i2c1: i2c@e0005000 {
580a54c5 MY	117	compatible = "cdns,i2c-r1p10";
	118	status = "disabled";
	119	clocks = <&clkc 39>;
	120	interrupt-parent = <&intc>;
	121	interrupts = <0 48 4>;
	122	reg = <0xe0005000 0x1000>;
	123	#address-cells = <1>;
	124	#size-cells = <0>;
	125	};
	126
	127	intc: interrupt-controller@f8f01000 {
	128	compatible = "arm,cortex-a9-gic";
	129	#interrupt-cells = <3>;
	130	#address-cells = <1>;
	131	interrupt-controller;
	132	reg = <0xF8F01000 0x1000>,
	133	<0xF8F00100 0x100>;
	134	};
	135
a0cb47f1	136	L2: cache-controller@f8f02000 {
580a54c5 MY	137	compatible = "arm,pl310-cache";
	138	reg = <0xF8F02000 0x1000>;
	139	arm,data-latency = <3 2 2>;
	140	arm,tag-latency = <2 2 2>;
	141	cache-unified;
	142	cache-level = <2>;
	143	};
	144
fb1a5061 MS	145	mc: memory-controller@f8006000 {
	146	compatible = "xlnx,zynq-ddrc-a05";
	147	reg = <0xf8006000 0x1000>;
	148	};
	149
a0cb47f1	150	uart0: serial@e0000000 {
8a8c46a6	151	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
580a54c5 MY	152	status = "disabled";
580a54c5 MY	153	clocks = <&clkc 23>, <&clkc 40>;
8a8c46a6	154	clock-names = "uart_clk", "pclk";
580a54c5 MY	155	reg = <0xE0000000 0x1000>;
	156	interrupts = <0 27 4>;
	157	};
	158
a0cb47f1	159	uart1: serial@e0001000 {
8a8c46a6	160	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
580a54c5 MY	161	status = "disabled";
580a54c5 MY	162	clocks = <&clkc 24>, <&clkc 41>;
8a8c46a6	163	clock-names = "uart_clk", "pclk";
580a54c5 MY	164	reg = <0xE0001000 0x1000>;
	165	interrupts = <0 50 4>;
	166	};
	167
a8a8fc9c	168	spi0: spi@e0006000 {
40b383fa	169	compatible = "xlnx,zynq-spi-r1p6";
a8a8fc9c JT	170	reg = <0xe0006000 0x1000>;
	171	status = "disabled";
	172	interrupt-parent = <&intc>;
	173	interrupts = <0 26 4>;
	174	clocks = <&clkc 25>, <&clkc 34>;
	175	clock-names = "ref_clk", "pclk";
cdc9dd07	176	spi-max-frequency = <166666700>;
a8a8fc9c JT	177	#address-cells = <1>;
	178	#size-cells = <0>;
	179	};
	180
	181	spi1: spi@e0007000 {
40b383fa	182	compatible = "xlnx,zynq-spi-r1p6";
a8a8fc9c JT	183	reg = <0xe0007000 0x1000>;
	184	status = "disabled";
	185	interrupt-parent = <&intc>;
	186	interrupts = <0 49 4>;
	187	clocks = <&clkc 26>, <&clkc 35>;
	188	clock-names = "ref_clk", "pclk";
cdc9dd07	189	spi-max-frequency = <166666700>;
a8a8fc9c JT	190	#address-cells = <1>;
	191	#size-cells = <0>;
	192	};
	193
580a54c5 MY	194	gem0: ethernet@e000b000 {
	195	compatible = "cdns,gem";
	196	reg = <0xe000b000 0x4000>;
	197	status = "disabled";
	198	interrupts = <0 22 4>;
	199	clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
	200	clock-names = "pclk", "hclk", "tx_clk";
	201	};
	202
	203	gem1: ethernet@e000c000 {
	204	compatible = "cdns,gem";
	205	reg = <0xe000c000 0x4000>;
	206	status = "disabled";
	207	interrupts = <0 45 4>;
	208	clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
	209	clock-names = "pclk", "hclk", "tx_clk";
	210	};
	211
a0cb47f1	212	sdhci0: sdhci@e0100000 {
580a54c5 MY	213	compatible = "arasan,sdhci-8.9a";
	214	status = "disabled";
	215	clock-names = "clk_xin", "clk_ahb";
	216	clocks = <&clkc 21>, <&clkc 32>;
	217	interrupt-parent = <&intc>;
	218	interrupts = <0 24 4>;
	219	reg = <0xe0100000 0x1000>;
	220	} ;
	221
a0cb47f1	222	sdhci1: sdhci@e0101000 {
580a54c5 MY	223	compatible = "arasan,sdhci-8.9a";
	224	status = "disabled";
	225	clock-names = "clk_xin", "clk_ahb";
	226	clocks = <&clkc 22>, <&clkc 33>;
	227	interrupt-parent = <&intc>;
	228	interrupts = <0 47 4>;
	229	reg = <0xe0101000 0x1000>;
	230	} ;
	231
	232	slcr: slcr@f8000000 {
	233	#address-cells = <1>;
	234	#size-cells = <1>;
	235	compatible = "xlnx,zynq-slcr", "syscon";
	236	reg = <0xF8000000 0x1000>;
	237	ranges;
	238	clkc: clkc@100 {
	239	#clock-cells = <1>;
	240	compatible = "xlnx,ps7-clkc";
	241	ps-clk-frequency = <33333333>;
	242	fclk-enable = <0>;
	243	clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
	244	"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
	245	"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
	246	"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
	247	"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
	248	"dma", "usb0_aper", "usb1_aper", "gem0_aper",
	249	"gem1_aper", "sdio0_aper", "sdio1_aper",
	250	"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
	251	"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
	252	"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
	253	"dbg_trc", "dbg_apb";
	254	reg = <0x100 0x100>;
	255	};
	256	};
	257
fb1a5061 MS	258	dmac_s: dmac@f8003000 {
	259	compatible = "arm,pl330", "arm,primecell";
	260	reg = <0xf8003000 0x1000>;
	261	interrupt-parent = <&intc>;
	262	interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
	263	"dma4", "dma5", "dma6", "dma7";
	264	interrupts = <0 13 4>,
	265	<0 14 4>, <0 15 4>,
	266	<0 16 4>, <0 17 4>,
	267	<0 40 4>, <0 41 4>,
	268	<0 42 4>, <0 43 4>;
	269	#dma-cells = <1>;
	270	#dma-channels = <8>;
	271	#dma-requests = <4>;
	272	clocks = <&clkc 27>;
	273	clock-names = "apb_pclk";
	274	};
	275
	276	devcfg: devcfg@f8007000 {
	277	compatible = "xlnx,zynq-devcfg-1.0";
	278	reg = <0xf8007000 0x100>;
	279	};
	280
580a54c5 MY	281	global_timer: timer@f8f00200 {
	282	compatible = "arm,cortex-a9-global-timer";
	283	reg = <0xf8f00200 0x20>;
	284	interrupts = <1 11 0x301>;
	285	interrupt-parent = <&intc>;
	286	clocks = <&clkc 4>;
	287	};
	288
a0cb47f1	289	ttc0: timer@f8001000 {
580a54c5 MY	290	interrupt-parent = <&intc>;
	291	interrupts = < 0 10 4 0 11 4 0 12 4 >;
	292	compatible = "cdns,ttc";
	293	clocks = <&clkc 6>;
	294	reg = <0xF8001000 0x1000>;
	295	};
	296
a0cb47f1	297	ttc1: timer@f8002000 {
580a54c5 MY	298	interrupt-parent = <&intc>;
	299	interrupts = < 0 37 4 0 38 4 0 39 4 >;
	300	compatible = "cdns,ttc";
	301	clocks = <&clkc 6>;
	302	reg = <0xF8002000 0x1000>;
	303	};
fb1a5061	304
a0cb47f1	305	scutimer: timer@f8f00600 {
580a54c5 MY	306	interrupt-parent = <&intc>;
	307	interrupts = < 1 13 0x301 >;
	308	compatible = "arm,cortex-a9-twd-timer";
	309	reg = < 0xf8f00600 0x20 >;
	310	clocks = <&clkc 4>;
	311	} ;
fb1a5061 MS	312
	313	usb0: usb@e0002000 {
	314	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	315	status = "disabled";
	316	clocks = <&clkc 28>;
	317	interrupt-parent = <&intc>;
	318	interrupts = <0 21 4>;
	319	reg = <0xe0002000 0x1000>;
	320	phy_type = "ulpi";
	321	};
	322
	323	usb1: usb@e0003000 {
	324	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	325	status = "disabled";
	326	clocks = <&clkc 29>;
	327	interrupt-parent = <&intc>;
	328	interrupts = <0 44 4>;
	329	reg = <0xe0003000 0x1000>;
	330	phy_type = "ulpi";
	331	};
	332
	333	watchdog0: watchdog@f8005000 {
	334	clocks = <&clkc 45>;
	335	compatible = "cdns,wdt-r1p2";
	336	interrupt-parent = <&intc>;
	337	interrupts = <0 9 1>;
	338	reg = <0xf8005000 0x1000>;
	339	timeout-sec = <10>;
	340	};
580a54c5	341	};
f8f36c5d	342	};