[u-boot.git] / drivers / video / rockchip / rk_vop.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 */

#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
#include <log.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/edp_rk3288.h>
#include <asm/arch-rockchip/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/regulator.h>
#include "rk_vop.h"

DECLARE_GLOBAL_DATA_PTR;

enum vop_pol {
	HSYNC_POSITIVE = 0,
	VSYNC_POSITIVE = 1,
	DEN_NEGATIVE   = 2,
	DCLK_INVERT    = 3
};

static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
			 int fb_bits_per_pixel,
			 const struct display_timing *edid)
{
	u32 lb_mode;
	u32 rgb_mode;
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;

	writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
	       &regs->win0_act_info);

	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
	       V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	       &regs->win0_dsp_st);

	writel(V_DSP_WIDTH(hactive - 1) |
		V_DSP_HEIGHT(vactive - 1),
		&regs->win0_dsp_info);

	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
			V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));

	switch (fb_bits_per_pixel) {
	case 16:
		rgb_mode = RGB565;
		writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 24:
		rgb_mode = RGB888;
		writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 32:
	default:
		rgb_mode = ARGB8888;
		writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	}

	if (hactive > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (hactive > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (hactive > 1280)
		lb_mode = LB_RGB_1920X5;
	else
		lb_mode = LB_RGB_1280X8;

	clrsetbits_le32(&regs->win0_ctrl0,
			M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
			V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
			V_WIN0_EN(1));

	writel(fbbase, &regs->win0_yrgb_mst);
	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

static void rkvop_set_pin_polarity(struct udevice *dev,
				   enum vop_modes mode, u32 polarity)
{
	struct rkvop_driverdata *ops =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	if (ops->set_pin_polarity)
		ops->set_pin_polarity(dev, mode, polarity);
}

static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;

	/* remove from standby */
	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));

	switch (mode) {
	case VOP_MODE_HDMI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_HDMI_OUT_EN(1));
		break;

	case VOP_MODE_EDP:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_EDP_OUT_EN(1));
		break;

#if defined(CONFIG_ROCKCHIP_RK3288)
	case VOP_MODE_LVDS:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_RGB_OUT_EN(1));
		break;
#endif

	case VOP_MODE_MIPI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_MIPI_OUT_EN(1));
		break;

	default:
		debug("%s: unsupported output mode %x\n", __func__, mode);
	}
}

static void rkvop_mode_set(struct udevice *dev,
			   const struct display_timing *edid,
			   enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;
	struct rkvop_driverdata *data =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	u32 hsync_len = edid->hsync_len.typ;
	u32 hback_porch = edid->hback_porch.typ;
	u32 vsync_len = edid->vsync_len.typ;
	u32 vback_porch = edid->vback_porch.typ;
	u32 hfront_porch = edid->hfront_porch.typ;
	u32 vfront_porch = edid->vfront_porch.typ;
	int mode_flags;
	u32 pin_polarity;

	pin_polarity = BIT(DCLK_INVERT);
	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
		pin_polarity |= BIT(HSYNC_POSITIVE);
	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
		pin_polarity |= BIT(VSYNC_POSITIVE);

	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	rkvop_enable_output(dev, mode);

	mode_flags = 0;  /* RGB888 */
	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	    (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
		mode_flags = 15;  /* RGBaaa */

	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
			V_DSP_OUT_MODE(mode_flags));

	writel(V_HSYNC(hsync_len) |
	       V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
			&regs->dsp_htotal_hs_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->dsp_hact_st_end);

	writel(V_VSYNC(vsync_len) |
	       V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	       &regs->dsp_vtotal_vs_end);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->dsp_vact_st_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->post_dsp_hact_info);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->post_dsp_vact_info);

	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

/**
 * rk_display_init() - Try to enable the given display device
 *
 * This function performs many steps:
 * - Finds the display device being referenced by @ep_node
 * - Puts the VOP's ID into its uclass platform data
 * - Probes the device to set it up
 * - Reads the EDID timing information
 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 * - Enables the display (the display device handles this and will do different
 *     things depending on the display type)
 * - Tells the uclass about the display resolution so that the console will
 *     appear correctly
 *
 * @dev:	VOP device that we want to connect to the display
 * @fbbase:	Frame buffer address
 * @ep_node:	Device tree node to process - this is the offset of an endpoint
 *		node within the VOP's 'port' list.
 * @return 0 if OK, -ve if something went wrong
 */
static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int vop_id, remote_vop_id;
	struct rk3288_vop *regs = priv->regs;
	struct display_timing timing;
	struct udevice *disp;
	int ret;
	u32 remote_phandle;
	struct display_plat *disp_uc_plat;
	struct clk clk;
	enum video_log2_bpp l2bpp;
	ofnode remote;

	debug("%s(%s, %lu, %s)\n", __func__,
	      dev_read_name(dev), fbbase, ofnode_get_name(ep_node));

	vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
	debug("vop_id=%d\n", vop_id);
	ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
	if (ret)
		return ret;

	remote = ofnode_get_by_phandle(remote_phandle);
	if (!ofnode_valid(remote))
		return -EINVAL;
	remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
	debug("remote vop_id=%d\n", remote_vop_id);

	/*
	 * The remote-endpoint references into a subnode of the encoder
	 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
	 * the following (assume 'hdmi_in_vopl' to be referenced):
	 *
	 * hdmi: hdmi@ff940000 {
	 *   ports {
	 *     hdmi_in: port {
	 *       hdmi_in_vopb: endpoint@0 { ... };
	 *       hdmi_in_vopl: endpoint@1 { ... };
	 *     }
	 *   }
	 * }
	 *
	 * The original code had 3 steps of "walking the parent", but
	 * a much better (as in: less likely to break if the DTS
	 * changes) way of doing this is to "find the enclosing device
	 * of UCLASS_DISPLAY".
	 */
	while (ofnode_valid(remote)) {
		remote = ofnode_get_parent(remote);
		if (!ofnode_valid(remote)) {
			debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
			      __func__, dev_read_name(dev));
			return -EINVAL;
		}

		uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
		if (disp)
			break;
	};

	disp_uc_plat = dev_get_uclass_plat(disp);
	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	if (display_in_use(disp)) {
		debug("   - device in use\n");
		return -EBUSY;
	}

	disp_uc_plat->source_id = remote_vop_id;
	disp_uc_plat->src_dev = dev;

	ret = device_probe(disp);
	if (ret) {
		debug("%s: device '%s' display won't probe (ret=%d)\n",
		      __func__, dev->name, ret);
		return ret;
	}

	ret = display_read_timing(disp, &timing);
	if (ret) {
		debug("%s: Failed to read timings\n", __func__);
		return ret;
	}

	ret = clk_get_by_index(dev, 1, &clk);
	if (!ret)
		ret = clk_set_rate(&clk, timing.pixelclock.typ);
	if (IS_ERR_VALUE(ret)) {
		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
		return ret;
	}

	/* Set bitwidth for vop display according to vop mode */
	switch (vop_id) {
	case VOP_MODE_EDP:
#if defined(CONFIG_ROCKCHIP_RK3288)
	case VOP_MODE_LVDS:
#endif
		l2bpp = VIDEO_BPP16;
		break;
	case VOP_MODE_HDMI:
	case VOP_MODE_MIPI:
		l2bpp = VIDEO_BPP32;
		break;
	default:
		l2bpp = VIDEO_BPP16;
	}

	rkvop_mode_set(dev, &timing, vop_id);
	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);

	ret = display_enable(disp, 1 << l2bpp, &timing);
	if (ret)
		return ret;

	uc_priv->xsize = timing.hactive.typ;
	uc_priv->ysize = timing.vactive.typ;
	uc_priv->bpix = l2bpp;
	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

void rk_vop_probe_regulators(struct udevice *dev,
			     const char * const *names, int cnt)
{
	int i, ret;
	const char *name;
	struct udevice *reg;

	for (i = 0; i < cnt; ++i) {
		name = names[i];
		debug("%s: probing regulator '%s'\n", dev->name, name);

		ret = regulator_autoset_by_name(name, &reg);
		if (!ret)
			ret = regulator_set_enable(reg, true);
	}
}

int rk_vop_probe(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int ret = 0;
	ofnode port, node;

	/* Before relocation we don't need to do anything */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	priv->regs = (struct rk3288_vop *)dev_read_addr(dev);

	/*
	 * Try all the ports until we find one that works. In practice this
	 * tries EDP first if available, then HDMI.
	 *
	 * Note that rockchip_vop_set_clk() always uses NPLL as the source
	 * clock so it is currently not possible to use more than one display
	 * device simultaneously.
	 */
	port = dev_read_subnode(dev, "port");
	if (!ofnode_valid(port)) {
		debug("%s(%s): 'port' subnode not found\n",
		      __func__, dev_read_name(dev));
		return -EINVAL;
	}

	for (node = ofnode_first_subnode(port);
	     ofnode_valid(node);
	     node = dev_read_next_subnode(node)) {
		ret = rk_display_init(dev, plat->base, node);
		if (ret)
			debug("Device failed: ret=%d\n", ret);
		if (!ret)
			break;
	}
	video_set_flush_dcache(dev, 1);

	return ret;
}

int rk_vop_bind(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);

	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
			  CONFIG_VIDEO_ROCKCHIP_MAX_YRES);

	return 0;
}
Commit	Line	Data
a355ece8	1	// SPDX-License-Identifier: GPL-2.0
7b7ad5c3 SG	2	/*
	3	* Copyright (c) 2015 Google, Inc
	4	* Copyright 2014 Rockchip Inc.
7b7ad5c3 SG	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <display.h>
	10	#include <dm.h>
	11	#include <edid.h>
f7ae49fc	12	#include <log.h>
7b7ad5c3 SG	13	#include <regmap.h>
	14	#include <syscon.h>
	15	#include <video.h>
401d1c4f	16	#include <asm/global_data.h>
7b7ad5c3	17	#include <asm/gpio.h>
7b7ad5c3	18	#include <asm/io.h>
15f09a1a KY	19	#include <asm/arch-rockchip/clock.h>
	20	#include <asm/arch-rockchip/edp_rk3288.h>
	21	#include <asm/arch-rockchip/vop_rk3288.h>
7b7ad5c3 SG	22	#include <dm/device-internal.h>
7b7ad5c3 SG	23	#include <dm/uclass-internal.h>
cd93d625	24	#include <linux/bitops.h>
61b29b82	25	#include <linux/err.h>
7b7ad5c3	26	#include <power/regulator.h>
d46d4047	27	#include "rk_vop.h"
7b7ad5c3 SG	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
d46d4047 PT	31	enum vop_pol {
	32	HSYNC_POSITIVE = 0,
	33	VSYNC_POSITIVE = 1,
	34	DEN_NEGATIVE = 2,
	35	DCLK_INVERT = 3
7b7ad5c3 SG	36	};
7b7ad5c3 SG	37
d46d4047 PT	38	static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
	39	int fb_bits_per_pixel,
	40	const struct display_timing *edid)
7b7ad5c3 SG	41	{
	42	u32 lb_mode;
	43	u32 rgb_mode;
	44	u32 hactive = edid->hactive.typ;
	45	u32 vactive = edid->vactive.typ;
	46
	47	writel(V_ACT_WIDTH(hactive - 1) \| V_ACT_HEIGHT(vactive - 1),
	48	&regs->win0_act_info);
	49
	50	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) \|
	51	V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	52	&regs->win0_dsp_st);
	53
	54	writel(V_DSP_WIDTH(hactive - 1) \|
	55	V_DSP_HEIGHT(vactive - 1),
	56	&regs->win0_dsp_info);
	57
	58	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN \| M_WIN0_KEY_COLOR,
	59	V_WIN0_KEY_EN(0) \| V_WIN0_KEY_COLOR(0));
	60
	61	switch (fb_bits_per_pixel) {
	62	case 16:
	63	rgb_mode = RGB565;
	64	writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
	65	break;
	66	case 24:
	67	rgb_mode = RGB888;
	68	writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
	69	break;
	70	case 32:
	71	default:
	72	rgb_mode = ARGB8888;
	73	writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
	74	break;
	75	}
	76
	77	if (hactive > 2560)
	78	lb_mode = LB_RGB_3840X2;
	79	else if (hactive > 1920)
	80	lb_mode = LB_RGB_2560X4;
	81	else if (hactive > 1280)
	82	lb_mode = LB_RGB_1920X5;
	83	else
	84	lb_mode = LB_RGB_1280X8;
	85
	86	clrsetbits_le32(&regs->win0_ctrl0,
	87	M_WIN0_LB_MODE \| M_WIN0_DATA_FMT \| M_WIN0_EN,
	88	V_WIN0_LB_MODE(lb_mode) \| V_WIN0_DATA_FMT(rgb_mode) \|
	89	V_WIN0_EN(1));
	90
	91	writel(fbbase, &regs->win0_yrgb_mst);
	92	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	93	}
	94
d46d4047 PT	95	static void rkvop_set_pin_polarity(struct udevice *dev,
d46d4047 PT	96	enum vop_modes mode, u32 polarity)
7b7ad5c3	97	{
d46d4047 PT	98	struct rkvop_driverdata *ops =
	99	(struct rkvop_driverdata *)dev_get_driver_data(dev);
	100
	101	if (ops->set_pin_polarity)
	102	ops->set_pin_polarity(dev, mode, polarity);
	103	}
	104
	105	static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
	106	{
	107	struct rk_vop_priv *priv = dev_get_priv(dev);
	108	struct rk3288_vop *regs = priv->regs;
7b7ad5c3	109
6b5a09aa SG	110	/* remove from standby */
	111	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
	112
7b7ad5c3 SG	113	switch (mode) {
	114	case VOP_MODE_HDMI:
	115	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	116	V_HDMI_OUT_EN(1));
	117	break;
d46d4047	118
7b7ad5c3	119	case VOP_MODE_EDP:
7b7ad5c3 SG	120	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	121	V_EDP_OUT_EN(1));
	122	break;
d46d4047	123
e67243f1	124	#if defined(CONFIG_ROCKCHIP_RK3288)
85307835 JC	125	case VOP_MODE_LVDS:
	126	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	127	V_RGB_OUT_EN(1));
	128	break;
e67243f1	129	#endif
d46d4047	130
9f819931 EG	131	case VOP_MODE_MIPI:
	132	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	133	V_MIPI_OUT_EN(1));
d46d4047 PT	134	break;
	135
	136	default:
	137	debug("%s: unsupported output mode %x\n", __func__, mode);
7b7ad5c3	138	}
d46d4047	139	}
7b7ad5c3	140
d46d4047 PT	141	static void rkvop_mode_set(struct udevice *dev,
	142	const struct display_timing *edid,
	143	enum vop_modes mode)
	144	{
	145	struct rk_vop_priv *priv = dev_get_priv(dev);
	146	struct rk3288_vop *regs = priv->regs;
	147	struct rkvop_driverdata *data =
	148	(struct rkvop_driverdata *)dev_get_driver_data(dev);
85307835	149
d46d4047 PT	150	u32 hactive = edid->hactive.typ;
	151	u32 vactive = edid->vactive.typ;
	152	u32 hsync_len = edid->hsync_len.typ;
	153	u32 hback_porch = edid->hback_porch.typ;
	154	u32 vsync_len = edid->vsync_len.typ;
	155	u32 vback_porch = edid->vback_porch.typ;
	156	u32 hfront_porch = edid->hfront_porch.typ;
	157	u32 vfront_porch = edid->vfront_porch.typ;
	158	int mode_flags;
	159	u32 pin_polarity;
	160
	161	pin_polarity = BIT(DCLK_INVERT);
	162	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
	163	pin_polarity \|= BIT(HSYNC_POSITIVE);
	164	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
	165	pin_polarity \|= BIT(VSYNC_POSITIVE);
	166
	167	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	168	rkvop_enable_output(dev, mode);
7b7ad5c3	169
d46d4047 PT	170	mode_flags = 0; /* RGB888 */
	171	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	172	(mode == VOP_MODE_HDMI \|\| mode == VOP_MODE_EDP))
	173	mode_flags = 15; /* RGBaaa */
	174
	175	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
	176	V_DSP_OUT_MODE(mode_flags));
7b7ad5c3 SG	177
	178	writel(V_HSYNC(hsync_len) \|
	179	V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
	180	&regs->dsp_htotal_hs_end);
	181
	182	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	183	V_HASP(hsync_len + hback_porch),
	184	&regs->dsp_hact_st_end);
	185
	186	writel(V_VSYNC(vsync_len) \|
	187	V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	188	&regs->dsp_vtotal_vs_end);
	189
	190	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	191	V_VASP(vsync_len + vback_porch),
	192	&regs->dsp_vact_st_end);
	193
	194	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	195	V_HASP(hsync_len + hback_porch),
	196	&regs->post_dsp_hact_info);
	197
	198	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	199	V_VASP(vsync_len + vback_porch),
	200	&regs->post_dsp_vact_info);
	201
	202	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	203	}
	204
	205	/**
	206	* rk_display_init() - Try to enable the given display device
	207	*
	208	* This function performs many steps:
	209	* - Finds the display device being referenced by @ep_node
	210	* - Puts the VOP's ID into its uclass platform data
	211	* - Probes the device to set it up
	212	* - Reads the EDID timing information
	213	* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
	214	* - Enables the display (the display device handles this and will do different
	215	* things depending on the display type)
	216	* - Tells the uclass about the display resolution so that the console will
	217	* appear correctly
	218	*
	219	* @dev: VOP device that we want to connect to the display
	220	* @fbbase: Frame buffer address
7b7ad5c3 SG	221	* @ep_node: Device tree node to process - this is the offset of an endpoint
	222	* node within the VOP's 'port' list.
	223	* @return 0 if OK, -ve if something went wrong
	224	*/
5de0b5a3	225	static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
7b7ad5c3 SG	226	{
7b7ad5c3 SG	227	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
7b7ad5c3 SG	228	struct rk_vop_priv *priv = dev_get_priv(dev);
	229	int vop_id, remote_vop_id;
	230	struct rk3288_vop *regs = priv->regs;
	231	struct display_timing timing;
	232	struct udevice *disp;
5de0b5a3 PT	233	int ret;
5de0b5a3 PT	234	u32 remote_phandle;
7b7ad5c3	235	struct display_plat *disp_uc_plat;
135aa950	236	struct clk clk;
8aed0d77	237	enum video_log2_bpp l2bpp;
5de0b5a3	238	ofnode remote;
7b7ad5c3	239
5de0b5a3 PT	240	debug("%s(%s, %lu, %s)\n", __func__,
	241	dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
	242
	243	vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
7b7ad5c3	244	debug("vop_id=%d\n", vop_id);
5de0b5a3 PT	245	ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
	246	if (ret)
	247	return ret;
7b7ad5c3	248
5de0b5a3 PT	249	remote = ofnode_get_by_phandle(remote_phandle);
5de0b5a3 PT	250	if (!ofnode_valid(remote))
7b7ad5c3	251	return -EINVAL;
5de0b5a3 PT	252	remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
5de0b5a3 PT	253	debug("remote vop_id=%d\n", remote_vop_id);
7b7ad5c3	254
5de0b5a3 PT	255	/*
	256	* The remote-endpoint references into a subnode of the encoder
	257	* (i.e. HDMI, MIPI, etc.) with the DTS looking something like
	258	* the following (assume 'hdmi_in_vopl' to be referenced):
	259	*
	260	* hdmi: hdmi@ff940000 {
	261	* ports {
	262	* hdmi_in: port {
	263	* hdmi_in_vopb: endpoint@0 { ... };
	264	* hdmi_in_vopl: endpoint@1 { ... };
	265	* }
	266	* }
	267	* }
	268	*
	269	* The original code had 3 steps of "walking the parent", but
	270	* a much better (as in: less likely to break if the DTS
	271	* changes) way of doing this is to "find the enclosing device
	272	* of UCLASS_DISPLAY".
	273	*/
	274	while (ofnode_valid(remote)) {
	275	remote = ofnode_get_parent(remote);
	276	if (!ofnode_valid(remote)) {
	277	debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
	278	__func__, dev_read_name(dev));
	279	return -EINVAL;
	280	}
	281
	282	uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
	283	if (disp)
	284	break;
	285	};
7b7ad5c3	286
caa4daa2	287	disp_uc_plat = dev_get_uclass_plat(disp);
7b7ad5c3	288	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
987a404a SG	289	if (display_in_use(disp)) {
	290	debug(" - device in use\n");
	291	return -EBUSY;
	292	}
	293
7b7ad5c3 SG	294	disp_uc_plat->source_id = remote_vop_id;
	295	disp_uc_plat->src_dev = dev;
	296
	297	ret = device_probe(disp);
	298	if (ret) {
	299	debug("%s: device '%s' display won't probe (ret=%d)\n",
	300	__func__, dev->name, ret);
	301	return ret;
	302	}
	303
	304	ret = display_read_timing(disp, &timing);
	305	if (ret) {
	306	debug("%s: Failed to read timings\n", __func__);
	307	return ret;
	308	}
	309
9ed68260	310	ret = clk_get_by_index(dev, 1, &clk);
135aa950 SW	311	if (!ret)
135aa950 SW	312	ret = clk_set_rate(&clk, timing.pixelclock.typ);
e07e5bde	313	if (IS_ERR_VALUE(ret)) {
7b7ad5c3 SG	314	debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
	315	return ret;
	316	}
	317
8aed0d77 EG	318	/* Set bitwidth for vop display according to vop mode */
	319	switch (vop_id) {
	320	case VOP_MODE_EDP:
e67243f1	321	#if defined(CONFIG_ROCKCHIP_RK3288)
8aed0d77	322	case VOP_MODE_LVDS:
e67243f1	323	#endif
8aed0d77 EG	324	l2bpp = VIDEO_BPP16;
8aed0d77 EG	325	break;
d46d4047	326	case VOP_MODE_HDMI:
8aed0d77 EG	327	case VOP_MODE_MIPI:
	328	l2bpp = VIDEO_BPP32;
	329	break;
	330	default:
	331	l2bpp = VIDEO_BPP16;
	332	}
7b7ad5c3	333
d46d4047	334	rkvop_mode_set(dev, &timing, vop_id);
7b7ad5c3 SG	335	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
	336
	337	ret = display_enable(disp, 1 << l2bpp, &timing);
	338	if (ret)
	339	return ret;
	340
	341	uc_priv->xsize = timing.hactive.typ;
	342	uc_priv->ysize = timing.vactive.typ;
	343	uc_priv->bpix = l2bpp;
	344	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
	345
	346	return 0;
	347	}
	348
d46d4047 PT	349	void rk_vop_probe_regulators(struct udevice *dev,
	350	const char * const *names, int cnt)
	351	{
	352	int i, ret;
	353	const char *name;
	354	struct udevice *reg;
	355
	356	for (i = 0; i < cnt; ++i) {
	357	name = names[i];
	358	debug("%s: probing regulator '%s'\n", dev->name, name);
	359
	360	ret = regulator_autoset_by_name(name, &reg);
	361	if (!ret)
	362	ret = regulator_set_enable(reg, true);
	363	}
	364	}
	365
	366	int rk_vop_probe(struct udevice *dev)
7b7ad5c3	367	{
8a8d24bd	368	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
7b7ad5c3	369	struct rk_vop_priv *priv = dev_get_priv(dev);
d46d4047	370	int ret = 0;
5de0b5a3	371	ofnode port, node;
7b7ad5c3 SG	372
	373	/* Before relocation we don't need to do anything */
	374	if (!(gd->flags & GD_FLG_RELOC))
	375	return 0;
	376
5de0b5a3	377	priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
7b7ad5c3	378
7b7ad5c3 SG	379	/*
	380	* Try all the ports until we find one that works. In practice this
	381	* tries EDP first if available, then HDMI.
987a404a SG	382	*
	383	* Note that rockchip_vop_set_clk() always uses NPLL as the source
	384	* clock so it is currently not possible to use more than one display
	385	* device simultaneously.
7b7ad5c3	386	*/
5de0b5a3 PT	387	port = dev_read_subnode(dev, "port");
	388	if (!ofnode_valid(port)) {
	389	debug("%s(%s): 'port' subnode not found\n",
	390	__func__, dev_read_name(dev));
7b7ad5c3	391	return -EINVAL;
5de0b5a3 PT	392	}
	393
	394	for (node = ofnode_first_subnode(port);
	395	ofnode_valid(node);
	396	node = dev_read_next_subnode(node)) {
8aed0d77	397	ret = rk_display_init(dev, plat->base, node);
7b7ad5c3 SG	398	if (ret)
	399	debug("Device failed: ret=%d\n", ret);
	400	if (!ret)
	401	break;
	402	}
b55e04a0	403	video_set_flush_dcache(dev, 1);
7b7ad5c3 SG	404
	405	return ret;
	406	}
	407
d46d4047	408	int rk_vop_bind(struct udevice *dev)
7b7ad5c3	409	{
8a8d24bd	410	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
7b7ad5c3	411
89b2b618 PT	412	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
89b2b618 PT	413	CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
7b7ad5c3 SG	414
	415	return 0;
	416	}