[u-boot.git] / drivers / video / fsl_dcu_fb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2019 Toradex AG
 *
 * FSL DCU Framebuffer driver
 */

#include <init.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <linux/fb.h>
#include <malloc.h>
#include <video.h>
#include <video_fb.h>
#include "videomodes.h"

/* Convert the X,Y resolution pair into a single number */
#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))

#ifdef CONFIG_SYS_FSL_DCU_LE
#define	dcu_read32	in_le32
#define	dcu_write32	out_le32
#elif defined(CONFIG_SYS_FSL_DCU_BE)
#define	dcu_read32	in_be32
#define	dcu_write32	out_be32
#endif

#define DCU_MODE_BLEND_ITER(x)          ((x) << 20)
#define DCU_MODE_RASTER_EN		(1 << 14)
#define DCU_MODE_NORMAL			1
#define DCU_MODE_COLORBAR               3
#define DCU_BGND_R(x)			((x) << 16)
#define DCU_BGND_G(x)			((x) << 8)
#define DCU_BGND_B(x)			(x)
#define DCU_DISP_SIZE_DELTA_Y(x)	((x) << 16)
#define DCU_DISP_SIZE_DELTA_X(x)	(x)
#define DCU_HSYN_PARA_BP(x)		((x) << 22)
#define DCU_HSYN_PARA_PW(x)		((x) << 11)
#define DCU_HSYN_PARA_FP(x)		(x)
#define DCU_VSYN_PARA_BP(x)		((x) << 22)
#define DCU_VSYN_PARA_PW(x)		((x) << 11)
#define DCU_VSYN_PARA_FP(x)		(x)
#define DCU_SYN_POL_INV_PXCK_FALL	(1 << 6)
#define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
#define DCU_SYN_POL_INV_VS_LOW		(1 << 1)
#define DCU_SYN_POL_INV_HS_LOW		(1)
#define DCU_THRESHOLD_LS_BF_VS(x)	((x) << 16)
#define DCU_THRESHOLD_OUT_BUF_HIGH(x)	((x) << 8)
#define DCU_THRESHOLD_OUT_BUF_LOW(x)	(x)
#define DCU_UPDATE_MODE_MODE            (1 << 31)
#define DCU_UPDATE_MODE_READREG         (1 << 30)

#define DCU_CTRLDESCLN_1_HEIGHT(x)	((x) << 16)
#define DCU_CTRLDESCLN_1_WIDTH(x)	(x)
#define DCU_CTRLDESCLN_2_POSY(x)	((x) << 16)
#define DCU_CTRLDESCLN_2_POSX(x)	(x)
#define DCU_CTRLDESCLN_4_EN		(1 << 31)
#define DCU_CTRLDESCLN_4_TILE_EN	(1 << 30)
#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT	(1 << 29)
#define DCU_CTRLDESCLN_4_SAFETY_EN	(1 << 28)
#define DCU_CTRLDESCLN_4_TRANS(x)	((x) << 20)
#define DCU_CTRLDESCLN_4_BPP(x)		((x) << 16)
#define DCU_CTRLDESCLN_4_RLE_EN		(1 << 15)
#define DCU_CTRLDESCLN_4_LUOFFS(x)	((x) << 4)
#define DCU_CTRLDESCLN_4_BB_ON		(1 << 2)
#define DCU_CTRLDESCLN_4_AB(x)		(x)
#define DCU_CTRLDESCLN_5_CKMAX_R(x)	((x) << 16)
#define DCU_CTRLDESCLN_5_CKMAX_G(x)	((x) << 8)
#define DCU_CTRLDESCLN_5_CKMAX_B(x)	(x)
#define DCU_CTRLDESCLN_6_CKMIN_R(x)	((x) << 16)
#define DCU_CTRLDESCLN_6_CKMIN_G(x)	((x) << 8)
#define DCU_CTRLDESCLN_6_CKMIN_B(x)	(x)
#define DCU_CTRLDESCLN_7_TILE_VER(x)	((x) << 16)
#define DCU_CTRLDESCLN_7_TILE_HOR(x)	(x)
#define DCU_CTRLDESCLN_8_FG_FCOLOR(x)	(x)
#define DCU_CTRLDESCLN_9_BG_BCOLOR(x)	(x)

#define BPP_16_RGB565			4
#define BPP_24_RGB888			5
#define BPP_32_ARGB8888			6

DECLARE_GLOBAL_DATA_PTR;

/*
 * This setting is used for the TWR_LCD_RGB card
 */
static struct fb_videomode fsl_dcu_mode_480_272 = {
	.name		= "480x272-60",
	.refresh	= 60,
	.xres		= 480,
	.yres		= 272,
	.pixclock	= 91996,
	.left_margin	= 2,
	.right_margin	= 2,
	.upper_margin	= 1,
	.lower_margin	= 1,
	.hsync_len	= 41,
	.vsync_len	= 2,
	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	.vmode		= FB_VMODE_NONINTERLACED
};

/*
 * This setting is used for Siliconimage SiI9022A HDMI
 */
static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
	.name		= "640x480-60",
	.refresh	= 60,
	.xres		= 640,
	.yres		= 480,
	.pixclock	= 39722,
	.left_margin	= 48,
	.right_margin	= 16,
	.upper_margin	= 33,
	.lower_margin	= 10,
	.hsync_len	= 96,
	.vsync_len	= 2,
	.sync		= 0,
	.vmode		= FB_VMODE_NONINTERLACED,
};

static struct fb_videomode fsl_dcu_mode_640_480 = {
	.name		= "640x480-60",
	.refresh	= 60,
	.xres		= 640,
	.yres		= 480,
	.pixclock	= 25175,
	.left_margin	= 40,
	.right_margin	= 24,
	.upper_margin	= 32,
	.lower_margin	= 11,
	.hsync_len	= 96,
	.vsync_len	= 2,
	.sync		= 0,
	.vmode		= FB_VMODE_NONINTERLACED,
};

static struct fb_videomode fsl_dcu_mode_800_480 = {
	.name		= "800x480-60",
	.refresh	= 60,
	.xres		= 800,
	.yres		= 480,
	.pixclock	= 33260,
	.left_margin	= 216,
	.right_margin	= 40,
	.upper_margin	= 35,
	.lower_margin	= 10,
	.hsync_len	= 128,
	.vsync_len	= 2,
	.sync		= 0,
	.vmode		= FB_VMODE_NONINTERLACED,
};

static struct fb_videomode fsl_dcu_mode_1024_600 = {
	.name		= "1024x600-60",
	.refresh	= 60,
	.xres		= 1024,
	.yres		= 600,
	.pixclock	= 48000,
	.left_margin	= 104,
	.right_margin	= 43,
	.upper_margin	= 24,
	.lower_margin	= 20,
	.hsync_len	= 5,
	.vsync_len	= 5,
	.sync		= 0,
	.vmode		= FB_VMODE_NONINTERLACED,
};

/*
 * DCU register map
 */
struct dcu_reg {
	u32 desc_cursor[4];
	u32 mode;
	u32 bgnd;
	u32 disp_size;
	u32 hsyn_para;
	u32 vsyn_para;
	u32 synpol;
	u32 threshold;
	u32 int_status;
	u32 int_mask;
	u32 colbar[8];
	u32 div_ratio;
	u32 sign_calc[2];
	u32 crc_val;
	u8 res_064[0x6c-0x64];
	u32 parr_err_status1;
	u8 res_070[0x7c-0x70];
	u32 parr_err_status3;
	u32 mparr_err_status1;
	u8 res_084[0x90-0x84];
	u32 mparr_err_status3;
	u32 threshold_inp_buf[2];
	u8 res_09c[0xa0-0x9c];
	u32 luma_comp;
	u32 chroma_red;
	u32 chroma_green;
	u32 chroma_blue;
	u32 crc_pos;
	u32 lyr_intpol_en;
	u32 lyr_luma_comp;
	u32 lyr_chrm_red;
	u32 lyr_chrm_grn;
	u32 lyr_chrm_blue;
	u8 res_0c4[0xcc-0xc8];
	u32 update_mode;
	u32 underrun;
	u8 res_0d4[0x100-0xd4];
	u32 gpr;
	u32 slr_l[2];
	u32 slr_disp_size;
	u32 slr_hvsync_para;
	u32 slr_pol;
	u32 slr_l_transp[2];
	u8 res_120[0x200-0x120];
	u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
};

static void reset_total_layers(void)
{
	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
	int i;

	for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
		dcu_write32(&regs->ctrldescl[i][0], 0);
		dcu_write32(&regs->ctrldescl[i][1], 0);
		dcu_write32(&regs->ctrldescl[i][2], 0);
		dcu_write32(&regs->ctrldescl[i][3], 0);
		dcu_write32(&regs->ctrldescl[i][4], 0);
		dcu_write32(&regs->ctrldescl[i][5], 0);
		dcu_write32(&regs->ctrldescl[i][6], 0);
		dcu_write32(&regs->ctrldescl[i][7], 0);
		dcu_write32(&regs->ctrldescl[i][8], 0);
		dcu_write32(&regs->ctrldescl[i][9], 0);
		dcu_write32(&regs->ctrldescl[i][10], 0);
	}
}

static int layer_ctrldesc_init(struct fb_info fbinfo,
			       int index, u32 pixel_format)
{
	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
	unsigned int bpp = BPP_24_RGB888;

	dcu_write32(&regs->ctrldescl[index][0],
		    DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
		    DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));

	dcu_write32(&regs->ctrldescl[index][1],
		    DCU_CTRLDESCLN_2_POSY(0) |
		    DCU_CTRLDESCLN_2_POSX(0));

	dcu_write32(&regs->ctrldescl[index][2],
		    (unsigned int)fbinfo.screen_base);

	switch (pixel_format) {
	case 16:
		bpp = BPP_16_RGB565;
		break;
	case 24:
		bpp = BPP_24_RGB888;
		break;
	case 32:
		bpp = BPP_32_ARGB8888;
		break;
	default:
		printf("unsupported color depth: %u\n", pixel_format);
	}

	dcu_write32(&regs->ctrldescl[index][3],
		    DCU_CTRLDESCLN_4_EN |
		    DCU_CTRLDESCLN_4_TRANS(0xff) |
		    DCU_CTRLDESCLN_4_BPP(bpp) |
		    DCU_CTRLDESCLN_4_AB(0));

	dcu_write32(&regs->ctrldescl[index][4],
		    DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
		    DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
		    DCU_CTRLDESCLN_5_CKMAX_B(0xff));
	dcu_write32(&regs->ctrldescl[index][5],
		    DCU_CTRLDESCLN_6_CKMIN_R(0) |
		    DCU_CTRLDESCLN_6_CKMIN_G(0) |
		    DCU_CTRLDESCLN_6_CKMIN_B(0));

	dcu_write32(&regs->ctrldescl[index][6],
		    DCU_CTRLDESCLN_7_TILE_VER(0) |
		    DCU_CTRLDESCLN_7_TILE_HOR(0));

	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));

	return 0;
}

int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
		 unsigned int yres, unsigned int pixel_format)
{
	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
	unsigned int div, mode;
/*
 * When DM_VIDEO is enabled reservation of framebuffer is done
 * in advance during bind() call.
 */
#if !CONFIG_IS_ENABLED(DM_VIDEO)
	fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
			     (fbinfo->var.bits_per_pixel / 8);

	if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
		fbinfo->screen_size = 0;
		return -ENOMEM;
	}
	/* Reserve framebuffer at the end of memory */
	gd->fb_base = gd->bd->bi_dram[0].start +
			gd->bd->bi_dram[0].size - fbinfo->screen_size;
	fbinfo->screen_base = (char *)gd->fb_base;

	memset(fbinfo->screen_base, 0, fbinfo->screen_size);
#endif

	reset_total_layers();

	dcu_write32(&regs->disp_size,
		    DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
		    DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));

	dcu_write32(&regs->hsyn_para,
		    DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
		    DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
		    DCU_HSYN_PARA_FP(fbinfo->var.right_margin));

	dcu_write32(&regs->vsyn_para,
		    DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
		    DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
		    DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));

	dcu_write32(&regs->synpol,
		    DCU_SYN_POL_INV_PXCK_FALL |
		    DCU_SYN_POL_NEG_REMAIN |
		    DCU_SYN_POL_INV_VS_LOW |
		    DCU_SYN_POL_INV_HS_LOW);

	dcu_write32(&regs->bgnd,
		    DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));

	dcu_write32(&regs->mode,
		    DCU_MODE_BLEND_ITER(2) |
		    DCU_MODE_RASTER_EN);

	dcu_write32(&regs->threshold,
		    DCU_THRESHOLD_LS_BF_VS(0x3) |
		    DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
		    DCU_THRESHOLD_OUT_BUF_LOW(0));

	mode = dcu_read32(&regs->mode);
	dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);

	layer_ctrldesc_init(*fbinfo, 0, pixel_format);

	div = dcu_set_pixel_clock(fbinfo->var.pixclock);
	dcu_write32(&regs->div_ratio, (div - 1));

	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);

	return 0;
}

ulong board_get_usable_ram_top(ulong total_size)
{
	return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
}

int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
		     unsigned int *win_y)
{
	const char *options;
	unsigned int depth = 0, freq = 0;

	struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;

	if (!video_get_video_mode(win_x, win_y, &depth, &freq,
				  &options))
		return -EINVAL;

	/* Find the monitor port, which is a required option */
	if (!options)
		return -EINVAL;

	if (strncmp(options, "monitor=", 8) != 0)
		return -EINVAL;

	switch (RESOLUTION(*win_x, *win_y)) {
	case RESOLUTION(480, 272):
		fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
		break;
	case RESOLUTION(640, 480):
		if (!strncmp(options, "monitor=hdmi", 12))
			fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
		else
			fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
		break;
	case RESOLUTION(800, 480):
		fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
		break;
	case RESOLUTION(1024, 600):
		fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
		break;
	default:
		printf("unsupported resolution %ux%u\n",
		       *win_x, *win_y);
	}

	fbinfo->var.xres = fsl_dcu_mode_db->xres;
	fbinfo->var.yres = fsl_dcu_mode_db->yres;
	fbinfo->var.bits_per_pixel = 32;
	fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
	fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
	fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
	fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
	fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
	fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
	fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
	fbinfo->var.sync = fsl_dcu_mode_db->sync;
	fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
	fbinfo->fix.line_length = fbinfo->var.xres *
				  fbinfo->var.bits_per_pixel / 8;

	return platform_dcu_init(fbinfo, *win_x, *win_y,
				 options + 8, fsl_dcu_mode_db);
}

#ifndef CONFIG_DM_VIDEO
static struct fb_info info;

#if defined(CONFIG_OF_BOARD_SETUP)
int fsl_dcu_fixedfb_setup(void *blob)
{
	u64 start, size;
	int ret;

	start = gd->bd->bi_dram[0].start;
	size = gd->bd->bi_dram[0].size - info.screen_size;

	/*
	 * Align size on section size (1 MiB).
	 */
	size &= 0xfff00000;
	ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
	if (ret) {
		eprintf("Cannot setup fb: Error reserving memory\n");
		return ret;
	}

	return 0;
}
#endif

void *video_hw_init(void)
{
	static GraphicDevice ctfb;

	if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
		return NULL;

	ctfb.frameAdrs = (unsigned int)info.screen_base;
	ctfb.plnSizeX = ctfb.winSizeX;
	ctfb.plnSizeY = ctfb.winSizeY;

	ctfb.gdfBytesPP = 4;
	ctfb.gdfIndex = GDF_32BIT_X888RGB;

	ctfb.memSize = info.screen_size;

	return &ctfb;
}

#else /* ifndef CONFIG_DM_VIDEO */

static int fsl_dcu_video_probe(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	struct fb_info fbinfo = { 0 };
	unsigned int win_x;
	unsigned int win_y;
	u32 fb_start, fb_end;
	int ret = 0;

	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
	fb_end = plat->base + plat->size;
	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);

	fbinfo.screen_base = (char *)fb_start;
	fbinfo.screen_size = plat->size;

	ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
	if (ret < 0)
		return ret;

	uc_priv->bpix = VIDEO_BPP32;
	uc_priv->xsize = win_x;
	uc_priv->ysize = win_y;

	/* Enable dcache for the frame buffer */
	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
					DCACHE_WRITEBACK);
	video_set_flush_dcache(dev, true);
	return ret;
}

static int fsl_dcu_video_bind(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
	unsigned int win_x;
	unsigned int win_y;
	unsigned int depth = 0, freq = 0;
	const char *options;
	int ret = 0;

	ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
	if (ret < 0)
		return ret;

	plat->size = win_x * win_y * 32;

	return 0;
}

static const struct udevice_id fsl_dcu_video_ids[] = {
	{ .compatible = "fsl,vf610-dcu" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(fsl_dcu_video) = {
	.name	= "fsl_dcu_video",
	.id	= UCLASS_VIDEO,
	.of_match = fsl_dcu_video_ids,
	.bind	= fsl_dcu_video_bind,
	.probe	= fsl_dcu_video_probe,
	.flags	= DM_FLAG_PRE_RELOC,
};
#endif /* ifndef CONFIG_DM_VIDEO */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
327def50 WH	2	/*
327def50 WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
a6eedb67	4	* Copyright 2019 Toradex AG
327def50 WH	5	*
327def50 WH	6	* FSL DCU Framebuffer driver
327def50 WH	7	*/
327def50 WH	8
67c4e9f8	9	#include <init.h>
90526e9f	10	#include <asm/cache.h>
401d1c4f	11	#include <asm/global_data.h>
327def50 WH	12	#include <asm/io.h>
327def50 WH	13	#include <common.h>
be3f1a56	14	#include <dm.h>
77810e63	15	#include <fdt_support.h>
327def50 WH	16	#include <fsl_dcu_fb.h>
	17	#include <linux/fb.h>
	18	#include <malloc.h>
be3f1a56	19	#include <video.h>
327def50 WH	20	#include <video_fb.h>
	21	#include "videomodes.h"
	22
	23	/* Convert the X,Y resolution pair into a single number */
	24	#define RESOLUTION(x, y) (((u32)(x) << 16) \| (y))
	25
	26	#ifdef CONFIG_SYS_FSL_DCU_LE
	27	#define dcu_read32 in_le32
	28	#define dcu_write32 out_le32
	29	#elif defined(CONFIG_SYS_FSL_DCU_BE)
	30	#define dcu_read32 in_be32
	31	#define dcu_write32 out_be32
	32	#endif
	33
	34	#define DCU_MODE_BLEND_ITER(x) ((x) << 20)
	35	#define DCU_MODE_RASTER_EN (1 << 14)
	36	#define DCU_MODE_NORMAL 1
	37	#define DCU_MODE_COLORBAR 3
	38	#define DCU_BGND_R(x) ((x) << 16)
	39	#define DCU_BGND_G(x) ((x) << 8)
	40	#define DCU_BGND_B(x) (x)
	41	#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
	42	#define DCU_DISP_SIZE_DELTA_X(x) (x)
	43	#define DCU_HSYN_PARA_BP(x) ((x) << 22)
	44	#define DCU_HSYN_PARA_PW(x) ((x) << 11)
	45	#define DCU_HSYN_PARA_FP(x) (x)
	46	#define DCU_VSYN_PARA_BP(x) ((x) << 22)
	47	#define DCU_VSYN_PARA_PW(x) ((x) << 11)
	48	#define DCU_VSYN_PARA_FP(x) (x)
32f26f56	49	#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
327def50 WH	50	#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
	51	#define DCU_SYN_POL_INV_VS_LOW (1 << 1)
	52	#define DCU_SYN_POL_INV_HS_LOW (1)
	53	#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
	54	#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
	55	#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
	56	#define DCU_UPDATE_MODE_MODE (1 << 31)
	57	#define DCU_UPDATE_MODE_READREG (1 << 30)
	58
	59	#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
	60	#define DCU_CTRLDESCLN_1_WIDTH(x) (x)
	61	#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
	62	#define DCU_CTRLDESCLN_2_POSX(x) (x)
	63	#define DCU_CTRLDESCLN_4_EN (1 << 31)
	64	#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
	65	#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
	66	#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
	67	#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
	68	#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
	69	#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
	70	#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
	71	#define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
	72	#define DCU_CTRLDESCLN_4_AB(x) (x)
	73	#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
	74	#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
	75	#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
	76	#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
	77	#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
	78	#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
	79	#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
	80	#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
	81	#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
	82	#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
	83
	84	#define BPP_16_RGB565 4
	85	#define BPP_24_RGB888 5
	86	#define BPP_32_ARGB8888 6
	87
77810e63 SA	88	DECLARE_GLOBAL_DATA_PTR;
77810e63 SA	89
327def50 WH	90	/*
	91	* This setting is used for the TWR_LCD_RGB card
	92	*/
	93	static struct fb_videomode fsl_dcu_mode_480_272 = {
	94	.name = "480x272-60",
	95	.refresh = 60,
	96	.xres = 480,
	97	.yres = 272,
	98	.pixclock = 91996,
	99	.left_margin = 2,
	100	.right_margin = 2,
	101	.upper_margin = 1,
	102	.lower_margin = 1,
	103	.hsync_len = 41,
	104	.vsync_len = 2,
	105	.sync = FB_SYNC_COMP_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	106	.vmode = FB_VMODE_NONINTERLACED
	107	};
	108
	109	/*
	110	* This setting is used for Siliconimage SiI9022A HDMI
	111	*/
7a2d533e	112	static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
327def50 WH	113	.name = "640x480-60",
	114	.refresh = 60,
	115	.xres = 640,
	116	.yres = 480,
	117	.pixclock = 39722,
	118	.left_margin = 48,
	119	.right_margin = 16,
	120	.upper_margin = 33,
	121	.lower_margin = 10,
	122	.hsync_len = 96,
	123	.vsync_len = 2,
	124	.sync = 0,
	125	.vmode = FB_VMODE_NONINTERLACED,
	126	};
	127
7a2d533e SA	128	static struct fb_videomode fsl_dcu_mode_640_480 = {
	129	.name = "640x480-60",
	130	.refresh = 60,
	131	.xres = 640,
	132	.yres = 480,
	133	.pixclock = 25175,
	134	.left_margin = 40,
	135	.right_margin = 24,
	136	.upper_margin = 32,
	137	.lower_margin = 11,
	138	.hsync_len = 96,
	139	.vsync_len = 2,
	140	.sync = 0,
	141	.vmode = FB_VMODE_NONINTERLACED,
	142	};
	143
	144	static struct fb_videomode fsl_dcu_mode_800_480 = {
	145	.name = "800x480-60",
	146	.refresh = 60,
	147	.xres = 800,
	148	.yres = 480,
	149	.pixclock = 33260,
	150	.left_margin = 216,
	151	.right_margin = 40,
	152	.upper_margin = 35,
	153	.lower_margin = 10,
	154	.hsync_len = 128,
	155	.vsync_len = 2,
	156	.sync = 0,
	157	.vmode = FB_VMODE_NONINTERLACED,
	158	};
	159
	160	static struct fb_videomode fsl_dcu_mode_1024_600 = {
	161	.name = "1024x600-60",
	162	.refresh = 60,
	163	.xres = 1024,
	164	.yres = 600,
	165	.pixclock = 48000,
	166	.left_margin = 104,
	167	.right_margin = 43,
	168	.upper_margin = 24,
	169	.lower_margin = 20,
	170	.hsync_len = 5,
	171	.vsync_len = 5,
	172	.sync = 0,
	173	.vmode = FB_VMODE_NONINTERLACED,
	174	};
	175
327def50 WH	176	/*
	177	* DCU register map
	178	*/
	179	struct dcu_reg {
	180	u32 desc_cursor[4];
	181	u32 mode;
	182	u32 bgnd;
	183	u32 disp_size;
	184	u32 hsyn_para;
	185	u32 vsyn_para;
	186	u32 synpol;
	187	u32 threshold;
	188	u32 int_status;
	189	u32 int_mask;
	190	u32 colbar[8];
	191	u32 div_ratio;
	192	u32 sign_calc[2];
	193	u32 crc_val;
	194	u8 res_064[0x6c-0x64];
	195	u32 parr_err_status1;
	196	u8 res_070[0x7c-0x70];
	197	u32 parr_err_status3;
	198	u32 mparr_err_status1;
	199	u8 res_084[0x90-0x84];
	200	u32 mparr_err_status3;
	201	u32 threshold_inp_buf[2];
	202	u8 res_09c[0xa0-0x9c];
	203	u32 luma_comp;
	204	u32 chroma_red;
	205	u32 chroma_green;
	206	u32 chroma_blue;
	207	u32 crc_pos;
	208	u32 lyr_intpol_en;
	209	u32 lyr_luma_comp;
	210	u32 lyr_chrm_red;
	211	u32 lyr_chrm_grn;
	212	u32 lyr_chrm_blue;
	213	u8 res_0c4[0xcc-0xc8];
	214	u32 update_mode;
	215	u32 underrun;
	216	u8 res_0d4[0x100-0xd4];
	217	u32 gpr;
	218	u32 slr_l[2];
	219	u32 slr_disp_size;
	220	u32 slr_hvsync_para;
	221	u32 slr_pol;
	222	u32 slr_l_transp[2];
	223	u8 res_120[0x200-0x120];
	224	u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
	225	};
	226
327def50 WH	227	static void reset_total_layers(void)
	228	{
	229	struct dcu_reg regs = (struct dcu_reg )CONFIG_SYS_DCU_ADDR;
	230	int i;
	231
	232	for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
	233	dcu_write32(&regs->ctrldescl[i][0], 0);
	234	dcu_write32(&regs->ctrldescl[i][1], 0);
	235	dcu_write32(&regs->ctrldescl[i][2], 0);
	236	dcu_write32(&regs->ctrldescl[i][3], 0);
	237	dcu_write32(&regs->ctrldescl[i][4], 0);
	238	dcu_write32(&regs->ctrldescl[i][5], 0);
	239	dcu_write32(&regs->ctrldescl[i][6], 0);
	240	dcu_write32(&regs->ctrldescl[i][7], 0);
	241	dcu_write32(&regs->ctrldescl[i][8], 0);
	242	dcu_write32(&regs->ctrldescl[i][9], 0);
	243	dcu_write32(&regs->ctrldescl[i][10], 0);
	244	}
327def50 WH	245	}
327def50 WH	246
a6eedb67 IO	247	static int layer_ctrldesc_init(struct fb_info fbinfo,
a6eedb67 IO	248	int index, u32 pixel_format)
327def50 WH	249	{
	250	struct dcu_reg regs = (struct dcu_reg )CONFIG_SYS_DCU_ADDR;
	251	unsigned int bpp = BPP_24_RGB888;
	252
	253	dcu_write32(&regs->ctrldescl[index][0],
a6eedb67 IO	254	DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) \|
a6eedb67 IO	255	DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
327def50 WH	256
	257	dcu_write32(&regs->ctrldescl[index][1],
	258	DCU_CTRLDESCLN_2_POSY(0) \|
	259	DCU_CTRLDESCLN_2_POSX(0));
	260
a6eedb67 IO	261	dcu_write32(&regs->ctrldescl[index][2],
a6eedb67 IO	262	(unsigned int)fbinfo.screen_base);
327def50 WH	263
	264	switch (pixel_format) {
	265	case 16:
	266	bpp = BPP_16_RGB565;
	267	break;
	268	case 24:
	269	bpp = BPP_24_RGB888;
	270	break;
	271	case 32:
	272	bpp = BPP_32_ARGB8888;
	273	break;
	274	default:
	275	printf("unsupported color depth: %u\n", pixel_format);
	276	}
	277
	278	dcu_write32(&regs->ctrldescl[index][3],
	279	DCU_CTRLDESCLN_4_EN \|
	280	DCU_CTRLDESCLN_4_TRANS(0xff) \|
	281	DCU_CTRLDESCLN_4_BPP(bpp) \|
	282	DCU_CTRLDESCLN_4_AB(0));
	283
	284	dcu_write32(&regs->ctrldescl[index][4],
	285	DCU_CTRLDESCLN_5_CKMAX_R(0xff) \|
	286	DCU_CTRLDESCLN_5_CKMAX_G(0xff) \|
	287	DCU_CTRLDESCLN_5_CKMAX_B(0xff));
	288	dcu_write32(&regs->ctrldescl[index][5],
	289	DCU_CTRLDESCLN_6_CKMIN_R(0) \|
	290	DCU_CTRLDESCLN_6_CKMIN_G(0) \|
	291	DCU_CTRLDESCLN_6_CKMIN_B(0));
	292
	293	dcu_write32(&regs->ctrldescl[index][6],
	294	DCU_CTRLDESCLN_7_TILE_VER(0) \|
	295	DCU_CTRLDESCLN_7_TILE_HOR(0));
	296
	297	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
	298	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
	299
327def50 WH	300	return 0;
	301	}
	302
a6eedb67 IO	303	int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
a6eedb67 IO	304	unsigned int yres, unsigned int pixel_format)
327def50 WH	305	{
	306	struct dcu_reg regs = (struct dcu_reg )CONFIG_SYS_DCU_ADDR;
	307	unsigned int div, mode;
be3f1a56 IO	308	/*
	309	* When DM_VIDEO is enabled reservation of framebuffer is done
	310	* in advance during bind() call.
	311	*/
	312	#if !CONFIG_IS_ENABLED(DM_VIDEO)
a6eedb67 IO	313	fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
a6eedb67 IO	314	(fbinfo->var.bits_per_pixel / 8);
77810e63	315
a6eedb67 IO	316	if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
a6eedb67 IO	317	fbinfo->screen_size = 0;
77810e63 SA	318	return -ENOMEM;
77810e63 SA	319	}
77810e63 SA	320	/* Reserve framebuffer at the end of memory */
77810e63 SA	321	gd->fb_base = gd->bd->bi_dram[0].start +
a6eedb67 IO	322	gd->bd->bi_dram[0].size - fbinfo->screen_size;
a6eedb67 IO	323	fbinfo->screen_base = (char *)gd->fb_base;
77810e63	324
a6eedb67	325	memset(fbinfo->screen_base, 0, fbinfo->screen_size);
be3f1a56	326	#endif
327def50 WH	327
327def50 WH	328	reset_total_layers();
327def50 WH	329
327def50 WH	330	dcu_write32(&regs->disp_size,
a6eedb67 IO	331	DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) \|
a6eedb67 IO	332	DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
327def50 WH	333
327def50 WH	334	dcu_write32(&regs->hsyn_para,
a6eedb67 IO	335	DCU_HSYN_PARA_BP(fbinfo->var.left_margin) \|
	336	DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) \|
	337	DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
327def50 WH	338
327def50 WH	339	dcu_write32(&regs->vsyn_para,
a6eedb67 IO	340	DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) \|
	341	DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) \|
	342	DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
327def50 WH	343
	344	dcu_write32(&regs->synpol,
	345	DCU_SYN_POL_INV_PXCK_FALL \|
	346	DCU_SYN_POL_NEG_REMAIN \|
	347	DCU_SYN_POL_INV_VS_LOW \|
	348	DCU_SYN_POL_INV_HS_LOW);
	349
	350	dcu_write32(&regs->bgnd,
	351	DCU_BGND_R(0) \| DCU_BGND_G(0) \| DCU_BGND_B(0));
	352
	353	dcu_write32(&regs->mode,
7ce92a55	354	DCU_MODE_BLEND_ITER(2) \|
327def50 WH	355	DCU_MODE_RASTER_EN);
	356
	357	dcu_write32(&regs->threshold,
	358	DCU_THRESHOLD_LS_BF_VS(0x3) \|
	359	DCU_THRESHOLD_OUT_BUF_HIGH(0x78) \|
	360	DCU_THRESHOLD_OUT_BUF_LOW(0));
	361
	362	mode = dcu_read32(&regs->mode);
	363	dcu_write32(&regs->mode, mode \| DCU_MODE_NORMAL);
	364
a6eedb67	365	layer_ctrldesc_init(*fbinfo, 0, pixel_format);
327def50	366
a6eedb67	367	div = dcu_set_pixel_clock(fbinfo->var.pixclock);
32f26f56 SA	368	dcu_write32(&regs->div_ratio, (div - 1));
	369
	370	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
	371
327def50 WH	372	return 0;
	373	}
	374
77810e63 SA	375	ulong board_get_usable_ram_top(ulong total_size)
	376	{
	377	return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
	378	}
	379
a6eedb67 IO	380	int fsl_probe_common(struct fb_info fbinfo, unsigned int win_x,
a6eedb67 IO	381	unsigned int *win_y)
327def50	382	{
327def50 WH	383	const char *options;
327def50 WH	384	unsigned int depth = 0, freq = 0;
a6eedb67	385
327def50 WH	386	struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
327def50 WH	387
a6eedb67	388	if (!video_get_video_mode(win_x, win_y, &depth, &freq,
327def50	389	&options))
a6eedb67	390	return -EINVAL;
327def50 WH	391
	392	/* Find the monitor port, which is a required option */
	393	if (!options)
a6eedb67 IO	394	return -EINVAL;
a6eedb67 IO	395
327def50	396	if (strncmp(options, "monitor=", 8) != 0)
a6eedb67	397	return -EINVAL;
327def50	398
a6eedb67	399	switch (RESOLUTION(win_x, win_y)) {
327def50 WH	400	case RESOLUTION(480, 272):
	401	fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
	402	break;
	403	case RESOLUTION(640, 480):
7a2d533e SA	404	if (!strncmp(options, "monitor=hdmi", 12))
	405	fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
	406	else
	407	fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
	408	break;
	409	case RESOLUTION(800, 480):
	410	fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
	411	break;
	412	case RESOLUTION(1024, 600):
	413	fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
327def50 WH	414	break;
	415	default:
	416	printf("unsupported resolution %ux%u\n",
a6eedb67	417	win_x, win_y);
327def50 WH	418	}
327def50 WH	419
a6eedb67 IO	420	fbinfo->var.xres = fsl_dcu_mode_db->xres;
	421	fbinfo->var.yres = fsl_dcu_mode_db->yres;
	422	fbinfo->var.bits_per_pixel = 32;
	423	fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
	424	fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
	425	fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
	426	fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
	427	fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
	428	fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
	429	fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
	430	fbinfo->var.sync = fsl_dcu_mode_db->sync;
	431	fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
	432	fbinfo->fix.line_length = fbinfo->var.xres *
	433	fbinfo->var.bits_per_pixel / 8;
	434
	435	return platform_dcu_init(fbinfo, win_x, win_y,
	436	options + 8, fsl_dcu_mode_db);
	437	}
	438
be3f1a56 IO	439	#ifndef CONFIG_DM_VIDEO
	440	static struct fb_info info;
	441
	442	#if defined(CONFIG_OF_BOARD_SETUP)
	443	int fsl_dcu_fixedfb_setup(void *blob)
	444	{
	445	u64 start, size;
	446	int ret;
	447
	448	start = gd->bd->bi_dram[0].start;
	449	size = gd->bd->bi_dram[0].size - info.screen_size;
	450
	451	/*
	452	* Align size on section size (1 MiB).
	453	*/
	454	size &= 0xfff00000;
	455	ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
	456	if (ret) {
	457	eprintf("Cannot setup fb: Error reserving memory\n");
	458	return ret;
	459	}
	460
	461	return 0;
	462	}
	463	#endif
	464
a6eedb67 IO	465	void *video_hw_init(void)
	466	{
	467	static GraphicDevice ctfb;
	468
	469	if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
327def50 WH	470	return NULL;
	471
	472	ctfb.frameAdrs = (unsigned int)info.screen_base;
	473	ctfb.plnSizeX = ctfb.winSizeX;
	474	ctfb.plnSizeY = ctfb.winSizeY;
	475
	476	ctfb.gdfBytesPP = 4;
	477	ctfb.gdfIndex = GDF_32BIT_X888RGB;
	478
	479	ctfb.memSize = info.screen_size;
	480
	481	return &ctfb;
	482	}
77810e63	483
be3f1a56 IO	484	#else /* ifndef CONFIG_DM_VIDEO */
	485
	486	static int fsl_dcu_video_probe(struct udevice *dev)
77810e63	487	{
8a8d24bd	488	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
be3f1a56 IO	489	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	490	struct fb_info fbinfo = { 0 };
	491	unsigned int win_x;
	492	unsigned int win_y;
	493	u32 fb_start, fb_end;
	494	int ret = 0;
	495
	496	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
	497	fb_end = plat->base + plat->size;
	498	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
	499
	500	fbinfo.screen_base = (char *)fb_start;
	501	fbinfo.screen_size = plat->size;
	502
	503	ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
	504	if (ret < 0)
	505	return ret;
77810e63	506
be3f1a56 IO	507	uc_priv->bpix = VIDEO_BPP32;
	508	uc_priv->xsize = win_x;
	509	uc_priv->ysize = win_y;
77810e63	510
be3f1a56 IO	511	/* Enable dcache for the frame buffer */
	512	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
	513	DCACHE_WRITEBACK);
	514	video_set_flush_dcache(dev, true);
	515	return ret;
	516	}
	517
	518	static int fsl_dcu_video_bind(struct udevice *dev)
	519	{
8a8d24bd	520	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
be3f1a56 IO	521	unsigned int win_x;
	522	unsigned int win_y;
	523	unsigned int depth = 0, freq = 0;
	524	const char *options;
	525	int ret = 0;
	526
	527	ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
	528	if (ret < 0)
77810e63	529	return ret;
be3f1a56 IO	530
be3f1a56 IO	531	plat->size = win_x * win_y * 32;
77810e63 SA	532
	533	return 0;
	534	}
be3f1a56 IO	535
	536	static const struct udevice_id fsl_dcu_video_ids[] = {
	537	{ .compatible = "fsl,vf610-dcu" },
	538	{ /* sentinel */ }
	539	};
	540
	541	U_BOOT_DRIVER(fsl_dcu_video) = {
	542	.name = "fsl_dcu_video",
	543	.id = UCLASS_VIDEO,
	544	.of_match = fsl_dcu_video_ids,
	545	.bind = fsl_dcu_video_bind,
	546	.probe = fsl_dcu_video_probe,
	547	.flags = DM_FLAG_PRE_RELOC,
	548	};
	549	#endif /* ifndef CONFIG_DM_VIDEO */