[u-boot.git] / drivers / video / atmel_lcdfb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Driver for AT91/AT32 LCD Controller
 *
 * Copyright (C) 2007 Atmel Corporation
 */

#include <common.h>
#include <atmel_lcd.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <part.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <bmp_layout.h>
#include <atmel_lcdc.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_DM_VIDEO
enum {
	/* Maximum LCD size we support */
	LCD_MAX_WIDTH		= 1366,
	LCD_MAX_HEIGHT		= 768,
	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
};
#endif

struct atmel_fb_priv {
	struct display_timing timing;
};

/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
#define ATMEL_LCDC_DMA_BURST_LEN	8
#ifndef ATMEL_LCDC_GUARD_TIME
#define ATMEL_LCDC_GUARD_TIME		1
#endif

#if defined(CONFIG_AT91SAM9263)
#define ATMEL_LCDC_FIFO_SIZE		2048
#else
#define ATMEL_LCDC_FIFO_SIZE		512
#endif

#define lcdc_readl(mmio, reg)		__raw_readl((mmio)+(reg))
#define lcdc_writel(mmio, reg, val)	__raw_writel((val), (mmio)+(reg))

#ifndef CONFIG_DM_VIDEO
ushort *configuration_get_cmap(void)
{
	return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
}

#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
void fb_put_word(uchar **fb, uchar **from)
{
	*(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
	*(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
	*from += 2;
}
#endif

#ifdef CONFIG_LCD_LOGO
#include <bmp_logo.h>
void lcd_logo_set_cmap(void)
{
	int i;
	uint lut_entry;
	ushort colreg;
	uint *cmap = (uint *)configuration_get_cmap();

	for (i = 0; i < BMP_LOGO_COLORS; ++i) {
		colreg = bmp_logo_palette[i];
#ifdef CONFIG_ATMEL_LCD_BGR555
		lut_entry = ((colreg & 0x000F) << 11) |
				((colreg & 0x00F0) <<  2) |
				((colreg & 0x0F00) >>  7);
#else
		lut_entry = ((colreg & 0x000F) << 1) |
				((colreg & 0x00F0) << 3) |
				((colreg & 0x0F00) << 4);
#endif
		*(cmap + BMP_LOGO_OFFSET) = lut_entry;
		cmap++;
	}
}
#endif

void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
#if defined(CONFIG_ATMEL_LCD_BGR555)
	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
		    (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
#else
	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
		    (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
#endif
}

void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
{
	int i;

	for (i = 0; i < colors; ++i) {
		struct bmp_color_table_entry cte = bmp->color_table[i];
		lcd_setcolreg(i, cte.red, cte.green, cte.blue);
	}
}
#endif

static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
			  bool tft, bool cont_pol_low, ulong lcdbase)
{
	unsigned long value;
	void *reg = (void *)addr;

	/* Turn off the LCD controller and the DMA controller */
	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
		    ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);

	/* Wait for the LCDC core to become idle */
	while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
		udelay(10);

	lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);

	/* Reset LCDC DMA */
	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);

	/* ...set frame size and burst length = 8 words (?) */
	value = (timing->hactive.typ * timing->vactive.typ *
		 (1 << bpix)) / 32;
	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
	lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);

	/* Set pixel clock */
	value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
	if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
		value++;
	value = (value / 2) - 1;

	if (!value) {
		lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
	} else
		lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
			    value << ATMEL_LCDC_CLKVAL_OFFSET);

	/* Initialize control register 2 */
	value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
	if (tft)
		value |= ATMEL_LCDC_DISTYPE_TFT;

	if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
		value |= ATMEL_LCDC_INVLINE_INVERTED;
	if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
		value |= ATMEL_LCDC_INVFRAME_INVERTED;
	value |= bpix << 5;
	lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);

	/* Vertical timing */
	value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
	value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
	value |= timing->vfront_porch.typ;
	/* Magic! (Datasheet says "Bit 31 must be written to 1") */
	value |= 1U << 31;
	lcdc_writel(reg, ATMEL_LCDC_TIM1, value);

	/* Horizontal timing */
	value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
	value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
	value |= (timing->hback_porch.typ - 1);
	lcdc_writel(reg, ATMEL_LCDC_TIM2, value);

	/* Display size */
	value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
	value |= timing->vactive.typ - 1;
	lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);

	/* FIFO Threshold: Use formula from data sheet */
	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
	lcdc_writel(reg, ATMEL_LCDC_FIFO, value);

	/* Toggle LCD_MODE every frame */
	lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);

	/* Disable all interrupts */
	lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);

	/* Set contrast */
	value = ATMEL_LCDC_PS_DIV8 |
		ATMEL_LCDC_ENA_PWMENABLE;
	if (!cont_pol_low)
		value |= ATMEL_LCDC_POL_POSITIVE;
	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);

	/* Set framebuffer DMA base address and pixel offset */
	lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);

	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
		    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
}

#ifndef CONFIG_DM_VIDEO
void lcd_ctrl_init(void *lcdbase)
{
	struct display_timing timing;

	timing.flags = 0;
	if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
		timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
	if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
		timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
	timing.pixelclock.typ = panel_info.vl_clk;

	timing.hactive.typ = panel_info.vl_col;
	timing.hfront_porch.typ = panel_info.vl_right_margin;
	timing.hback_porch.typ = panel_info.vl_left_margin;
	timing.hsync_len.typ = panel_info.vl_hsync_len;

	timing.vactive.typ = panel_info.vl_row;
	timing.vfront_porch.typ = panel_info.vl_clk;
	timing.vback_porch.typ = panel_info.vl_clk;
	timing.vsync_len.typ = panel_info.vl_clk;

	atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
		      panel_info.vl_tft, panel_info.vl_cont_pol_low,
		      (ulong)lcdbase);
}

ulong calc_fbsize(void)
{
	return ((panel_info.vl_col * panel_info.vl_row *
		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
}
#endif

#ifdef CONFIG_DM_VIDEO
static int atmel_fb_lcd_probe(struct udevice *dev)
{
	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	struct atmel_fb_priv *priv = dev_get_priv(dev);
	struct display_timing *timing = &priv->timing;

	/*
	 * For now some values are hard-coded. We could use the device tree
	 * bindings in simple-framebuffer.txt to specify the format/bpp and
	 * some Atmel-specific binding for tft and cont_pol_low.
	 */
	atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
		      uc_plat->base);
	uc_priv->xsize = timing->hactive.typ;
	uc_priv->ysize = timing->vactive.typ;
	uc_priv->bpix = VIDEO_BPP16;
	video_set_flush_dcache(dev, true);
	debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
	      uc_plat->size, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

static int atmel_fb_of_to_plat(struct udevice *dev)
{
	struct atmel_lcd_plat *plat = dev_get_plat(dev);
	struct atmel_fb_priv *priv = dev_get_priv(dev);
	struct display_timing *timing = &priv->timing;
	const void *blob = gd->fdt_blob;

	if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
					 plat->timing_index, timing)) {
		debug("%s: Failed to decode display timing\n", __func__);
		return -EINVAL;
	}

	return 0;
}

static int atmel_fb_lcd_bind(struct udevice *dev)
{
	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);

	uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
			(1 << VIDEO_BPP16) / 8;
	debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);

	return 0;
}

static const struct udevice_id atmel_fb_lcd_ids[] = {
	{ .compatible = "atmel,at91sam9g45-lcdc" },
	{ }
};

U_BOOT_DRIVER(atmel_fb) = {
	.name	= "atmel_fb",
	.id	= UCLASS_VIDEO,
	.of_match = atmel_fb_lcd_ids,
	.bind	= atmel_fb_lcd_bind,
	.of_to_plat	= atmel_fb_of_to_plat,
	.probe	= atmel_fb_lcd_probe,
	.plat_auto	= sizeof(struct atmel_lcd_plat),
	.priv_auto	= sizeof(struct atmel_fb_priv),
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
39cf4804 SP	2	/*
	3	* Driver for AT91/AT32 LCD Controller
	4	*
	5	* Copyright (C) 2007 Atmel Corporation
39cf4804 SP	6	*/
	7
	8	#include <common.h>
9dc89a05 SG	9	#include <atmel_lcd.h>
9dc89a05 SG	10	#include <dm.h>
d63ec26a	11	#include <fdtdec.h>
f7ae49fc	12	#include <log.h>
e6f6f9e6	13	#include <part.h>
9dc89a05	14	#include <video.h>
401d1c4f	15	#include <asm/global_data.h>
39cf4804	16	#include <asm/io.h>
39cf4804 SP	17	#include <asm/arch/gpio.h>
	18	#include <asm/arch/clk.h>
	19	#include <lcd.h>
0b29a896	20	#include <bmp_layout.h>
39cf4804	21	#include <atmel_lcdc.h>
c05ed00a	22	#include <linux/delay.h>
39cf4804	23
9dc89a05 SG	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	#ifdef CONFIG_DM_VIDEO
	27	enum {
	28	/* Maximum LCD size we support */
	29	LCD_MAX_WIDTH = 1366,
	30	LCD_MAX_HEIGHT = 768,
	31	LCD_MAX_LOG2_BPP = VIDEO_BPP16,
	32	};
	33	#endif
	34
	35	struct atmel_fb_priv {
	36	struct display_timing timing;
	37	};
	38
39cf4804 SP	39	/* configurable parameters */
	40	#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
	41	#define ATMEL_LCDC_DMA_BURST_LEN 8
6bbced67 MJ	42	#ifndef ATMEL_LCDC_GUARD_TIME
	43	#define ATMEL_LCDC_GUARD_TIME 1
	44	#endif
39cf4804	45
c6941e12	46	#if defined(CONFIG_AT91SAM9263)
39cf4804 SP	47	#define ATMEL_LCDC_FIFO_SIZE 2048
	48	#else
	49	#define ATMEL_LCDC_FIFO_SIZE 512
	50	#endif
	51
	52	#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
	53	#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
	54
9dc89a05	55	#ifndef CONFIG_DM_VIDEO
38b55087 NK	56	ushort *configuration_get_cmap(void)
	57	{
	58	return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
	59	}
	60
b3d12e9b NK	61	#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
	62	void fb_put_word(uchar fb, uchar from)
	63	{
	64	(fb)++ = (((from)[0] & 0x1f) << 2) \| ((from)[1] & 0x03);
	65	(fb)++ = ((from)[0] & 0xe0) \| (((from)[1] & 0x7c) >> 2);
	66	*from += 2;
	67	}
	68	#endif
	69
a02e9481 NK	70	#ifdef CONFIG_LCD_LOGO
	71	#include <bmp_logo.h>
	72	void lcd_logo_set_cmap(void)
	73	{
	74	int i;
	75	uint lut_entry;
	76	ushort colreg;
	77	uint cmap = (uint )configuration_get_cmap();
	78
	79	for (i = 0; i < BMP_LOGO_COLORS; ++i) {
	80	colreg = bmp_logo_palette[i];
	81	#ifdef CONFIG_ATMEL_LCD_BGR555
	82	lut_entry = ((colreg & 0x000F) << 11) \|
	83	((colreg & 0x00F0) << 2) \|
	84	((colreg & 0x0F00) >> 7);
	85	#else
	86	lut_entry = ((colreg & 0x000F) << 1) \|
	87	((colreg & 0x00F0) << 3) \|
	88	((colreg & 0x0F00) << 4);
	89	#endif
	90	*(cmap + BMP_LOGO_OFFSET) = lut_entry;
	91	cmap++;
	92	}
	93	}
	94	#endif
	95
39cf4804 SP	96	void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
	97	{
	98	#if defined(CONFIG_ATMEL_LCD_BGR555)
	99	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
	100	(red >> 3) \| ((green & 0xf8) << 2) \| ((blue & 0xf8) << 7));
	101	#else
	102	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
	103	(blue >> 3) \| ((green & 0xfc) << 3) \| ((red & 0xf8) << 8));
	104	#endif
	105	}
	106
1c3dbe56	107	void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
0b29a896 NK	108	{
	109	int i;
	110
	111	for (i = 0; i < colors; ++i) {
1c3dbe56	112	struct bmp_color_table_entry cte = bmp->color_table[i];
0b29a896 NK	113	lcd_setcolreg(i, cte.red, cte.green, cte.blue);
	114	}
	115	}
9dc89a05	116	#endif
0b29a896	117
d63ec26a SG	118	static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
d63ec26a SG	119	bool tft, bool cont_pol_low, ulong lcdbase)
39cf4804 SP	120	{
39cf4804 SP	121	unsigned long value;
d63ec26a	122	void reg = (void )addr;
39cf4804 SP	123
39cf4804 SP	124	/* Turn off the LCD controller and the DMA controller */
d63ec26a	125	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
6bbced67	126	ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
39cf4804 SP	127
39cf4804 SP	128	/* Wait for the LCDC core to become idle */
d63ec26a	129	while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
39cf4804 SP	130	udelay(10);
39cf4804 SP	131
d63ec26a	132	lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
39cf4804 SP	133
39cf4804 SP	134	/* Reset LCDC DMA */
d63ec26a	135	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
39cf4804 SP	136
39cf4804 SP	137	/* ...set frame size and burst length = 8 words (?) */
d63ec26a SG	138	value = (timing->hactive.typ * timing->vactive.typ *
d63ec26a SG	139	(1 << bpix)) / 32;
39cf4804	140	value \|= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
d63ec26a	141	lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
39cf4804 SP	142
39cf4804 SP	143	/* Set pixel clock */
d63ec26a SG	144	value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
d63ec26a SG	145	if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
39cf4804 SP	146	value++;
	147	value = (value / 2) - 1;
	148
	149	if (!value) {
d63ec26a	150	lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
39cf4804	151	} else
d63ec26a	152	lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
39cf4804 SP	153	value << ATMEL_LCDC_CLKVAL_OFFSET);
	154
	155	/* Initialize control register 2 */
	156	value = ATMEL_LCDC_MEMOR_LITTLE \| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
d63ec26a	157	if (tft)
39cf4804 SP	158	value \|= ATMEL_LCDC_DISTYPE_TFT;
39cf4804 SP	159
d63ec26a SG	160	if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
	161	value \|= ATMEL_LCDC_INVLINE_INVERTED;
	162	if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
	163	value \|= ATMEL_LCDC_INVFRAME_INVERTED;
	164	value \|= bpix << 5;
	165	lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
39cf4804 SP	166
39cf4804 SP	167	/* Vertical timing */
d63ec26a SG	168	value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
	169	value \|= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
	170	value \|= timing->vfront_porch.typ;
	171	/* Magic! (Datasheet says "Bit 31 must be written to 1") */
	172	value \|= 1U << 31;
	173	lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
39cf4804 SP	174
39cf4804 SP	175	/* Horizontal timing */
d63ec26a SG	176	value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
	177	value \|= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
	178	value \|= (timing->hback_porch.typ - 1);
	179	lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
39cf4804 SP	180
39cf4804 SP	181	/* Display size */
d63ec26a SG	182	value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
	183	value \|= timing->vactive.typ - 1;
	184	lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
39cf4804 SP	185
	186	/* FIFO Threshold: Use formula from data sheet */
	187	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
d63ec26a	188	lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
39cf4804 SP	189
39cf4804 SP	190	/* Toggle LCD_MODE every frame */
d63ec26a	191	lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
39cf4804 SP	192
39cf4804 SP	193	/* Disable all interrupts */
d63ec26a	194	lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
39cf4804 SP	195
	196	/* Set contrast */
	197	value = ATMEL_LCDC_PS_DIV8 \|
39cf4804	198	ATMEL_LCDC_ENA_PWMENABLE;
d63ec26a	199	if (!cont_pol_low)
cdfcedbf	200	value \|= ATMEL_LCDC_POL_POSITIVE;
d63ec26a SG	201	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
d63ec26a SG	202	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
39cf4804 SP	203
39cf4804 SP	204	/* Set framebuffer DMA base address and pixel offset */
d63ec26a	205	lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
39cf4804	206
d63ec26a SG	207	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
d63ec26a SG	208	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
6bbced67	209	(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) \| ATMEL_LCDC_PWR);
39cf4804 SP	210	}
39cf4804 SP	211
9dc89a05	212	#ifndef CONFIG_DM_VIDEO
d63ec26a SG	213	void lcd_ctrl_init(void *lcdbase)
	214	{
	215	struct display_timing timing;
	216
	217	timing.flags = 0;
	218	if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
	219	timing.flags \|= DISPLAY_FLAGS_HSYNC_HIGH;
	220	if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
	221	timing.flags \|= DISPLAY_FLAGS_VSYNC_LOW;
	222	timing.pixelclock.typ = panel_info.vl_clk;
	223
	224	timing.hactive.typ = panel_info.vl_col;
	225	timing.hfront_porch.typ = panel_info.vl_right_margin;
	226	timing.hback_porch.typ = panel_info.vl_left_margin;
	227	timing.hsync_len.typ = panel_info.vl_hsync_len;
	228
	229	timing.vactive.typ = panel_info.vl_row;
	230	timing.vfront_porch.typ = panel_info.vl_clk;
	231	timing.vback_porch.typ = panel_info.vl_clk;
	232	timing.vsync_len.typ = panel_info.vl_clk;
	233
	234	atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
	235	panel_info.vl_tft, panel_info.vl_cont_pol_low,
	236	(ulong)lcdbase);
	237	}
	238
39cf4804 SP	239	ulong calc_fbsize(void)
	240	{
	241	return ((panel_info.vl_col * panel_info.vl_row *
	242	NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
	243	}
9dc89a05 SG	244	#endif
	245
	246	#ifdef CONFIG_DM_VIDEO
	247	static int atmel_fb_lcd_probe(struct udevice *dev)
	248	{
8a8d24bd	249	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
9dc89a05 SG	250	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	251	struct atmel_fb_priv *priv = dev_get_priv(dev);
	252	struct display_timing *timing = &priv->timing;
	253
	254	/*
	255	* For now some values are hard-coded. We could use the device tree
	256	* bindings in simple-framebuffer.txt to specify the format/bpp and
	257	* some Atmel-specific binding for tft and cont_pol_low.
	258	*/
	259	atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
	260	uc_plat->base);
	261	uc_priv->xsize = timing->hactive.typ;
	262	uc_priv->ysize = timing->vactive.typ;
	263	uc_priv->bpix = VIDEO_BPP16;
	264	video_set_flush_dcache(dev, true);
	265	debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
	266	uc_plat->size, uc_priv->xsize, uc_priv->ysize);
	267
	268	return 0;
	269	}
	270
d1998a9f	271	static int atmel_fb_of_to_plat(struct udevice *dev)
9dc89a05	272	{
8a8d24bd	273	struct atmel_lcd_plat *plat = dev_get_plat(dev);
9dc89a05 SG	274	struct atmel_fb_priv *priv = dev_get_priv(dev);
	275	struct display_timing *timing = &priv->timing;
	276	const void *blob = gd->fdt_blob;
	277
e160f7d4	278	if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
9dc89a05 SG	279	plat->timing_index, timing)) {
	280	debug("%s: Failed to decode display timing\n", __func__);
	281	return -EINVAL;
	282	}
	283
	284	return 0;
	285	}
	286
	287	static int atmel_fb_lcd_bind(struct udevice *dev)
	288	{
8a8d24bd	289	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
9dc89a05 SG	290
	291	uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
	292	(1 << VIDEO_BPP16) / 8;
	293	debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
	294
	295	return 0;
	296	}
	297
	298	static const struct udevice_id atmel_fb_lcd_ids[] = {
	299	{ .compatible = "atmel,at91sam9g45-lcdc" },
	300	{ }
	301	};
	302
	303	U_BOOT_DRIVER(atmel_fb) = {
	304	.name = "atmel_fb",
	305	.id = UCLASS_VIDEO,
	306	.of_match = atmel_fb_lcd_ids,
	307	.bind = atmel_fb_lcd_bind,
d1998a9f	308	.of_to_plat = atmel_fb_of_to_plat,
9dc89a05	309	.probe = atmel_fb_lcd_probe,
8a8d24bd	310	.plat_auto = sizeof(struct atmel_lcd_plat),
41575d8e	311	.priv_auto = sizeof(struct atmel_fb_priv),
9dc89a05 SG	312	};
9dc89a05 SG	313	#endif