[u-boot.git] / drivers / spi / zynq_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 Xilinx, Inc.
 * (C) Copyright 2015 Jagan Teki <[email protected]>
 *
 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>

DECLARE_GLOBAL_DATA_PTR;

/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
#define ZYNQ_QSPI_CR_IFMODE_MASK	BIT(31)	/* Flash intrface mode*/
#define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
#define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
#define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
#define ZYNQ_QSPI_CR_FW_MASK		GENMASK(7, 6)	/* FIFO width */
#define ZYNQ_QSPI_CR_SS_MASK		GENMASK(13, 10)	/* Slave Select */
#define ZYNQ_QSPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
#define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
#define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
#define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
#define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
#define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
#define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK	BIT(31) /* Linear QSPI Mode */

/* zynq qspi Transmit Data Register */
#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */
#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80	/* Transmit 1-byte inst */
#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84	/* Transmit 2-byte inst */
#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88	/* Transmit 3-byte inst */

#define ZYNQ_QSPI_TXFIFO_THRESHOLD	1	/* Tx FIFO threshold level*/
#define ZYNQ_QSPI_RXFIFO_THRESHOLD	32	/* Rx FIFO threshold level */

#define ZYNQ_QSPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
#define ZYNQ_QSPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
#define ZYNQ_QSPI_CR_SS_SHIFT		10	/* Slave select shift */

#define ZYNQ_QSPI_FIFO_DEPTH		63
#define ZYNQ_QSPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */

/* zynq qspi register set */
struct zynq_qspi_regs {
	u32 cr;		/* 0x00 */
	u32 isr;	/* 0x04 */
	u32 ier;	/* 0x08 */
	u32 idr;	/* 0x0C */
	u32 imr;	/* 0x10 */
	u32 enr;	/* 0x14 */
	u32 dr;		/* 0x18 */
	u32 txd0r;	/* 0x1C */
	u32 drxr;	/* 0x20 */
	u32 sicr;	/* 0x24 */
	u32 txftr;	/* 0x28 */
	u32 rxftr;	/* 0x2C */
	u32 gpior;	/* 0x30 */
	u32 reserved0[19];
	u32 txd1r;	/* 0x80 */
	u32 txd2r;	/* 0x84 */
	u32 txd3r;	/* 0x88 */
	u32 reserved1[5];
	u32 lqspicfg;	/* 0xA0 */
	u32 lqspists;	/* 0xA4 */
};

/* zynq qspi platform data */
struct zynq_qspi_plat {
	struct zynq_qspi_regs *regs;
	u32 frequency;          /* input frequency */
	u32 speed_hz;
};

/* zynq qspi priv */
struct zynq_qspi_priv {
	struct zynq_qspi_regs *regs;
	u8 cs;
	u8 mode;
	u8 fifo_depth;
	u32 freq;		/* required frequency */
	const void *tx_buf;
	void *rx_buf;
	unsigned len;
	int bytes_to_transfer;
	int bytes_to_receive;
	unsigned int is_inst;
	unsigned cs_change:1;
};

static int zynq_qspi_of_to_plat(struct udevice *bus)
{
	struct zynq_qspi_plat *plat = dev_get_plat(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
							      node, "reg");

	return 0;
}

/**
 * zynq_qspi_init_hw - Initialize the hardware
 * @priv:	Pointer to the zynq_qspi_priv structure
 *
 * The default settings of the QSPI controller's configurable parameters on
 * reset are
 *	- Master mode
 *	- Baud rate divisor is set to 2
 *	- Threshold value for TX FIFO not full interrupt is set to 1
 *	- Flash memory interface mode enabled
 *	- Size of the word to be transferred as 8 bit
 * This function performs the following actions
 *	- Disable and clear all the interrupts
 *	- Enable manual slave select
 *	- Enable auto start
 *	- Deselect all the chip select lines
 *	- Set the size of the word to be transferred as 32 bit
 *	- Set the little endian mode of TX FIFO and
 *	- Enable the QSPI controller
 */
static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
{
	struct zynq_qspi_regs *regs = priv->regs;
	u32 confr;

	/* Disable QSPI */
	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	/* Disable Interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);

	/* Clear the TX and RX threshold reg */
	writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
	writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);

	/* Clear the RX FIFO */
	while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
		readl(&regs->drxr);

	/* Clear Interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);

	/* Manual slave select and Auto start */
	confr = readl(&regs->cr);
	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
	confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
		ZYNQ_QSPI_CR_MSTREN_MASK;
	writel(confr, &regs->cr);

	/* Disable the LQSPI feature */
	confr = readl(&regs->lqspicfg);
	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
	writel(confr, &regs->lqspicfg);

	/* Enable SPI */
	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
}

static int zynq_qspi_probe(struct udevice *bus)
{
	struct zynq_qspi_plat *plat = dev_get_plat(bus);
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct clk clk;
	unsigned long clock;
	int ret;

	priv->regs = plat->regs;
	priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;

	ret = clk_get_by_name(bus, "ref_clk", &clk);
	if (ret < 0) {
		dev_err(bus, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(bus, "failed to get rate\n");
		return clock;
	}

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}

	/* init the zynq spi hw */
	zynq_qspi_init_hw(priv);

	plat->frequency = clock;
	plat->speed_hz = plat->frequency / 2;

	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);

	return 0;
}

/**
 * zynq_qspi_read_data - Copy data to RX buffer
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @data:	The 32 bit variable where data is stored
 * @size:	Number of bytes to be copied from data to RX buffer
 */
static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
{
	u8 byte3;

	debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
	      data, (unsigned)(priv->rx_buf), size);

	if (priv->rx_buf) {
		switch (size) {
		case 1:
			*((u8 *)priv->rx_buf) = data;
			priv->rx_buf += 1;
			break;
		case 2:
			*((u16 *)priv->rx_buf) = data;
			priv->rx_buf += 2;
			break;
		case 3:
			*((u16 *)priv->rx_buf) = data;
			priv->rx_buf += 2;
			byte3 = (u8)(data >> 16);
			*((u8 *)priv->rx_buf) = byte3;
			priv->rx_buf += 1;
			break;
		case 4:
			/* Can not assume word aligned buffer */
			memcpy(priv->rx_buf, &data, size);
			priv->rx_buf += 4;
			break;
		default:
			/* This will never execute */
			break;
		}
	}
	priv->bytes_to_receive -= size;
	if (priv->bytes_to_receive < 0)
		priv->bytes_to_receive = 0;
}

/**
 * zynq_qspi_write_data - Copy data from TX buffer
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @data:	Pointer to the 32 bit variable where data is to be copied
 * @size:	Number of bytes to be copied from TX buffer to data
 */
static void zynq_qspi_write_data(struct  zynq_qspi_priv *priv,
		u32 *data, u8 size)
{
	if (priv->tx_buf) {
		switch (size) {
		case 1:
			*data = *((u8 *)priv->tx_buf);
			priv->tx_buf += 1;
			*data |= 0xFFFFFF00;
			break;
		case 2:
			*data = *((u16 *)priv->tx_buf);
			priv->tx_buf += 2;
			*data |= 0xFFFF0000;
			break;
		case 3:
			*data = *((u16 *)priv->tx_buf);
			priv->tx_buf += 2;
			*data |= (*((u8 *)priv->tx_buf) << 16);
			priv->tx_buf += 1;
			*data |= 0xFF000000;
			break;
		case 4:
			/* Can not assume word aligned buffer */
			memcpy(data, priv->tx_buf, size);
			priv->tx_buf += 4;
			break;
		default:
			/* This will never execute */
			break;
		}
	} else {
		*data = 0;
	}

	debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
	      *data, (u32)priv->tx_buf, size);

	priv->bytes_to_transfer -= size;
	if (priv->bytes_to_transfer < 0)
		priv->bytes_to_transfer = 0;
}

/**
 * zynq_qspi_chipselect - Select or deselect the chip select line
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @is_on:	Select(1) or deselect (0) the chip select line
 */
static void zynq_qspi_chipselect(struct  zynq_qspi_priv *priv, int is_on)
{
	u32 confr;
	struct zynq_qspi_regs *regs = priv->regs;

	confr = readl(&regs->cr);

	if (is_on) {
		/* Select the slave */
		confr &= ~ZYNQ_QSPI_CR_SS_MASK;
		confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
					ZYNQ_QSPI_CR_SS_MASK;
	} else
		/* Deselect the slave */
		confr |= ZYNQ_QSPI_CR_SS_MASK;

	writel(confr, &regs->cr);
}

/**
 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 * @priv:	Pointer to the zynq_qspi_priv structure
 * @size:	Number of bytes to be copied to fifo
 */
static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
{
	u32 data = 0;
	u32 fifocount = 0;
	unsigned len, offset;
	struct zynq_qspi_regs *regs = priv->regs;
	static const unsigned offsets[4] = {
		ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
		ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };

	while ((fifocount < size) &&
			(priv->bytes_to_transfer > 0)) {
		if (priv->bytes_to_transfer >= 4) {
			if (priv->tx_buf) {
				memcpy(&data, priv->tx_buf, 4);
				priv->tx_buf += 4;
			} else {
				data = 0;
			}
			writel(data, &regs->txd0r);
			priv->bytes_to_transfer -= 4;
			fifocount++;
		} else {
			/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
			if (!(readl(&regs->isr)
					& ZYNQ_QSPI_IXR_TXOW_MASK) &&
					!priv->rx_buf)
				return;
			len = priv->bytes_to_transfer;
			zynq_qspi_write_data(priv, &data, len);
			offset = (priv->rx_buf) ? offsets[0] : offsets[len];
			writel(data, &regs->cr + (offset / 4));
		}
	}
}

/**
 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
 * @priv:	Pointer to the zynq_qspi structure
 *
 * This function handles TX empty and Mode Fault interrupts only.
 * On TX empty interrupt this function reads the received data from RX FIFO and
 * fills the TX FIFO if there is any data remaining to be transferred.
 * On Mode Fault interrupt this function indicates that transfer is completed,
 * the SPI subsystem will identify the error as the remaining bytes to be
 * transferred is non-zero.
 *
 * returns:	0 for poll timeout
 *		1 transfer operation complete
 */
static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
{
	struct zynq_qspi_regs *regs = priv->regs;
	u32 rxindex = 0;
	u32 rxcount;
	u32 status, timeout;

	/* Poll until any of the interrupt status bits are set */
	timeout = get_timer(0);
	do {
		status = readl(&regs->isr);
	} while ((status == 0) &&
		(get_timer(timeout) < ZYNQ_QSPI_WAIT));

	if (status == 0) {
		printf("zynq_qspi_irq_poll: Timeout!\n");
		return -ETIMEDOUT;
	}

	writel(status, &regs->isr);

	/* Disable all interrupts */
	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
	    (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
		/*
		 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
		 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
		 * is empty
		 */
		rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
		rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
		while ((rxindex < rxcount) &&
				(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
			/* Read out the data from the RX FIFO */
			u32 data;
			data = readl(&regs->drxr);

			if (priv->bytes_to_receive >= 4) {
				if (priv->rx_buf) {
					memcpy(priv->rx_buf, &data, 4);
					priv->rx_buf += 4;
				}
				priv->bytes_to_receive -= 4;
			} else {
				zynq_qspi_read_data(priv, data,
						    priv->bytes_to_receive);
			}
			rxindex++;
		}

		if (priv->bytes_to_transfer) {
			/* There is more data to send */
			zynq_qspi_fill_tx_fifo(priv,
					       ZYNQ_QSPI_RXFIFO_THRESHOLD);

			writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
		} else {
			/*
			 * If transfer and receive is completed then only send
			 * complete signal
			 */
			if (!priv->bytes_to_receive) {
				/* return operation complete */
				writel(ZYNQ_QSPI_IXR_ALL_MASK,
				       &regs->idr);
				return 1;
			}
		}
	}

	return 0;
}

/**
 * zynq_qspi_start_transfer - Initiates the QSPI transfer
 * @priv:	Pointer to the zynq_qspi_priv structure
 *
 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 * transfer to be completed.
 *
 * returns:	Number of bytes transferred in the last transfer
 */
static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
{
	u32 data = 0;
	struct zynq_qspi_regs *regs = priv->regs;

	debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
	      (u32)priv, (u32)priv, priv->len);

	priv->bytes_to_transfer = priv->len;
	priv->bytes_to_receive = priv->len;

	if (priv->len < 4)
		zynq_qspi_fill_tx_fifo(priv, priv->len);
	else
		zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);

	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);

	/* wait for completion */
	do {
		data = zynq_qspi_irq_poll(priv);
	} while (data == 0);

	return (priv->len) - (priv->bytes_to_transfer);
}

static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
{
	unsigned cs_change = 1;
	int status = 0;

	while (1) {
		/* Select the chip if required */
		if (cs_change)
			zynq_qspi_chipselect(priv, 1);

		cs_change = priv->cs_change;

		if (!priv->tx_buf && !priv->rx_buf && priv->len) {
			status = -1;
			break;
		}

		/* Request the transfer */
		if (priv->len) {
			status = zynq_qspi_start_transfer(priv);
			priv->is_inst = 0;
		}

		if (status != priv->len) {
			if (status > 0)
				status = -EMSGSIZE;
			debug("zynq_qspi_transfer:%d len:%d\n",
			      status, priv->len);
			break;
		}
		status = 0;

		if (cs_change)
			/* Deselect the chip */
			zynq_qspi_chipselect(priv, 0);

		break;
	}

	return status;
}

static int zynq_qspi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;

	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_qspi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;

	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	priv->cs = slave_plat->cs;
	priv->tx_buf = dout;
	priv->rx_buf = din;
	priv->len = bitlen / 8;

	debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
	      dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);

	/*
	 * Festering sore.
	 * Assume that the beginning of a transfer with bits to
	 * transmit must contain a device command.
	 */
	if (dout && flags & SPI_XFER_BEGIN)
		priv->is_inst = 1;
	else
		priv->is_inst = 0;

	if (flags & SPI_XFER_END)
		priv->cs_change = 1;
	else
		priv->cs_change = 0;

	zynq_qspi_transfer(priv);

	return 0;
}

static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
	struct zynq_qspi_plat *plat = dev_get_plat(bus);
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;
	uint32_t confr;
	u8 baud_rate_val = 0;

	if (speed > plat->frequency)
		speed = plat->frequency;

	/* Set the clock frequency */
	confr = readl(&regs->cr);
	if (speed == 0) {
		/* Set baudrate x8, if the freq is 0 */
		baud_rate_val = 0x2;
	} else if (plat->speed_hz != speed) {
		while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
		       ((plat->frequency /
		       (2 << baud_rate_val)) > speed))
			baud_rate_val++;

		plat->speed_hz = speed / (2 << baud_rate_val);
	}
	confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
	confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);

	writel(confr, &regs->cr);
	priv->freq = speed;

	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);

	return 0;
}

static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	struct zynq_qspi_regs *regs = priv->regs;
	uint32_t confr;

	/* Set the SPI Clock phase and polarities */
	confr = readl(&regs->cr);
	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);

	if (mode & SPI_CPHA)
		confr |= ZYNQ_QSPI_CR_CPHA_MASK;
	if (mode & SPI_CPOL)
		confr |= ZYNQ_QSPI_CR_CPOL_MASK;

	writel(confr, &regs->cr);
	priv->mode = mode;

	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops zynq_qspi_ops = {
	.claim_bus      = zynq_qspi_claim_bus,
	.release_bus    = zynq_qspi_release_bus,
	.xfer           = zynq_qspi_xfer,
	.set_speed      = zynq_qspi_set_speed,
	.set_mode       = zynq_qspi_set_mode,
};

static const struct udevice_id zynq_qspi_ids[] = {
	{ .compatible = "xlnx,zynq-qspi-1.0" },
	{ }
};

U_BOOT_DRIVER(zynq_qspi) = {
	.name   = "zynq_qspi",
	.id     = UCLASS_SPI,
	.of_match = zynq_qspi_ids,
	.ops    = &zynq_qspi_ops,
	.of_to_plat = zynq_qspi_of_to_plat,
	.plat_auto	= sizeof(struct zynq_qspi_plat),
	.priv_auto	= sizeof(struct zynq_qspi_priv),
	.probe  = zynq_qspi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
46d0a991 JT	2	/*
	3	* (C) Copyright 2013 Xilinx, Inc.
	4	* (C) Copyright 2015 Jagan Teki <[email protected]>
	5	*
	6	* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
46d0a991 JT	7	*/
46d0a991 JT	8
ea836be1	9	#include <clk.h>
46d0a991 JT	10	#include <common.h>
46d0a991 JT	11	#include <dm.h>
ea836be1	12	#include <dm/device_compat.h>
f7ae49fc	13	#include <log.h>
46d0a991 JT	14	#include <malloc.h>
46d0a991 JT	15	#include <spi.h>
401d1c4f	16	#include <asm/global_data.h>
46d0a991	17	#include <asm/io.h>
cd93d625	18	#include <linux/bitops.h>
46d0a991 JT	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
736b4df1 JT	23	#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
	24	#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
	25	#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
	26	#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
9cf2ffb3 JT	27	#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
	28	#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
	29	#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
736b4df1 JT	30	#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
	31	#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
	32	#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
	33	#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
	34	#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
9cf2ffb3	35	#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
736b4df1	36	#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
04a44d36	37	#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
46d0a991 JT	38
	39	/* zynq qspi Transmit Data Register */
	40	#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
	41	#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
	42	#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
	43	#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
	44
	45	#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
	46	#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
	47
	48	#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
	49	#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
	50	#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
	51
	52	#define ZYNQ_QSPI_FIFO_DEPTH 63
f44bd3bc	53	#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
46d0a991 JT	54
	55	/* zynq qspi register set */
	56	struct zynq_qspi_regs {
	57	u32 cr; /* 0x00 */
	58	u32 isr; /* 0x04 */
	59	u32 ier; /* 0x08 */
	60	u32 idr; /* 0x0C */
	61	u32 imr; /* 0x10 */
	62	u32 enr; /* 0x14 */
	63	u32 dr; /* 0x18 */
	64	u32 txd0r; /* 0x1C */
	65	u32 drxr; /* 0x20 */
	66	u32 sicr; /* 0x24 */
	67	u32 txftr; /* 0x28 */
	68	u32 rxftr; /* 0x2C */
	69	u32 gpior; /* 0x30 */
	70	u32 reserved0[19];
	71	u32 txd1r; /* 0x80 */
	72	u32 txd2r; /* 0x84 */
	73	u32 txd3r; /* 0x88 */
04a44d36 NR	74	u32 reserved1[5];
	75	u32 lqspicfg; /* 0xA0 */
	76	u32 lqspists; /* 0xA4 */
46d0a991 JT	77	};
	78
	79	/* zynq qspi platform data */
8a8d24bd	80	struct zynq_qspi_plat {
46d0a991 JT	81	struct zynq_qspi_regs *regs;
	82	u32 frequency; /* input frequency */
	83	u32 speed_hz;
	84	};
	85
	86	/* zynq qspi priv */
	87	struct zynq_qspi_priv {
	88	struct zynq_qspi_regs *regs;
	89	u8 cs;
	90	u8 mode;
	91	u8 fifo_depth;
	92	u32 freq; /* required frequency */
	93	const void *tx_buf;
	94	void *rx_buf;
	95	unsigned len;
	96	int bytes_to_transfer;
	97	int bytes_to_receive;
	98	unsigned int is_inst;
	99	unsigned cs_change:1;
	100	};
	101
d1998a9f	102	static int zynq_qspi_of_to_plat(struct udevice *bus)
46d0a991	103	{
0fd3d911	104	struct zynq_qspi_plat *plat = dev_get_plat(bus);
46d0a991	105	const void *blob = gd->fdt_blob;
e160f7d4	106	int node = dev_of_offset(bus);
46d0a991 JT	107
	108	plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
	109	node, "reg");
	110
46d0a991 JT	111	return 0;
	112	}
	113
17fbb598 ARS	114	/**
	115	* zynq_qspi_init_hw - Initialize the hardware
	116	* @priv: Pointer to the zynq_qspi_priv structure
	117	*
	118	* The default settings of the QSPI controller's configurable parameters on
	119	* reset are
	120	* - Master mode
	121	* - Baud rate divisor is set to 2
	122	* - Threshold value for TX FIFO not full interrupt is set to 1
	123	* - Flash memory interface mode enabled
	124	* - Size of the word to be transferred as 8 bit
	125	* This function performs the following actions
	126	* - Disable and clear all the interrupts
	127	* - Enable manual slave select
	128	* - Enable auto start
	129	* - Deselect all the chip select lines
	130	* - Set the size of the word to be transferred as 32 bit
	131	* - Set the little endian mode of TX FIFO and
	132	* - Enable the QSPI controller
	133	*/
46d0a991 JT	134	static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
	135	{
	136	struct zynq_qspi_regs *regs = priv->regs;
	137	u32 confr;
	138
	139	/* Disable QSPI */
	140	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	141
	142	/* Disable Interrupts */
	143	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	144
	145	/* Clear the TX and RX threshold reg */
	146	writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
	147	writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
	148
	149	/* Clear the RX FIFO */
	150	while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
	151	readl(&regs->drxr);
	152
	153	/* Clear Interrupts */
	154	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
	155
	156	/* Manual slave select and Auto start */
	157	confr = readl(&regs->cr);
	158	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
	159	confr \|= ZYNQ_QSPI_CR_IFMODE_MASK \| ZYNQ_QSPI_CR_MCS_MASK \|
	160	ZYNQ_QSPI_CR_PCS_MASK \| ZYNQ_QSPI_CR_FW_MASK \|
	161	ZYNQ_QSPI_CR_MSTREN_MASK;
	162	writel(confr, &regs->cr);
	163
04a44d36 NR	164	/* Disable the LQSPI feature */
	165	confr = readl(&regs->lqspicfg);
	166	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
	167	writel(confr, &regs->lqspicfg);
	168
46d0a991 JT	169	/* Enable SPI */
	170	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	171	}
	172
	173	static int zynq_qspi_probe(struct udevice *bus)
	174	{
8a8d24bd	175	struct zynq_qspi_plat *plat = dev_get_plat(bus);
46d0a991	176	struct zynq_qspi_priv *priv = dev_get_priv(bus);
ea836be1 KR	177	struct clk clk;
	178	unsigned long clock;
	179	int ret;
46d0a991 JT	180
	181	priv->regs = plat->regs;
	182	priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
	183
ea836be1 KR	184	ret = clk_get_by_name(bus, "ref_clk", &clk);
	185	if (ret < 0) {
	186	dev_err(bus, "failed to get clock\n");
	187	return ret;
	188	}
	189
	190	clock = clk_get_rate(&clk);
	191	if (IS_ERR_VALUE(clock)) {
	192	dev_err(bus, "failed to get rate\n");
	193	return clock;
	194	}
	195
	196	ret = clk_enable(&clk);
	197	if (ret && ret != -ENOSYS) {
	198	dev_err(bus, "failed to enable clock\n");
	199	return ret;
	200	}
	201
46d0a991 JT	202	/* init the zynq spi hw */
	203	zynq_qspi_init_hw(priv);
	204
ea836be1 KR	205	plat->frequency = clock;
	206	plat->speed_hz = plat->frequency / 2;
	207
	208	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
	209
46d0a991 JT	210	return 0;
	211	}
	212
17fbb598	213	/**
46d0a991	214	* zynq_qspi_read_data - Copy data to RX buffer
17fbb598	215	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	216	* @data: The 32 bit variable where data is stored
	217	* @size: Number of bytes to be copied from data to RX buffer
	218	*/
	219	static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
	220	{
	221	u8 byte3;
	222
	223	debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
	224	data, (unsigned)(priv->rx_buf), size);
	225
	226	if (priv->rx_buf) {
	227	switch (size) {
	228	case 1:
	229	((u8 )priv->rx_buf) = data;
	230	priv->rx_buf += 1;
	231	break;
	232	case 2:
	233	((u16 )priv->rx_buf) = data;
	234	priv->rx_buf += 2;
	235	break;
	236	case 3:
	237	((u16 )priv->rx_buf) = data;
	238	priv->rx_buf += 2;
	239	byte3 = (u8)(data >> 16);
	240	((u8 )priv->rx_buf) = byte3;
	241	priv->rx_buf += 1;
	242	break;
	243	case 4:
	244	/* Can not assume word aligned buffer */
	245	memcpy(priv->rx_buf, &data, size);
	246	priv->rx_buf += 4;
	247	break;
	248	default:
	249	/* This will never execute */
	250	break;
	251	}
	252	}
	253	priv->bytes_to_receive -= size;
	254	if (priv->bytes_to_receive < 0)
	255	priv->bytes_to_receive = 0;
	256	}
	257
17fbb598	258	/**
46d0a991	259	* zynq_qspi_write_data - Copy data from TX buffer
17fbb598	260	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	261	* @data: Pointer to the 32 bit variable where data is to be copied
	262	* @size: Number of bytes to be copied from TX buffer to data
	263	*/
	264	static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
	265	u32 *data, u8 size)
	266	{
	267	if (priv->tx_buf) {
	268	switch (size) {
	269	case 1:
	270	data = ((u8 *)priv->tx_buf);
	271	priv->tx_buf += 1;
	272	*data \|= 0xFFFFFF00;
	273	break;
	274	case 2:
	275	data = ((u16 *)priv->tx_buf);
	276	priv->tx_buf += 2;
	277	*data \|= 0xFFFF0000;
	278	break;
	279	case 3:
	280	data = ((u16 *)priv->tx_buf);
	281	priv->tx_buf += 2;
	282	data \|= (((u8 *)priv->tx_buf) << 16);
	283	priv->tx_buf += 1;
	284	*data \|= 0xFF000000;
	285	break;
	286	case 4:
	287	/* Can not assume word aligned buffer */
	288	memcpy(data, priv->tx_buf, size);
	289	priv->tx_buf += 4;
	290	break;
	291	default:
	292	/* This will never execute */
	293	break;
	294	}
	295	} else {
	296	*data = 0;
	297	}
	298
	299	debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
	300	*data, (u32)priv->tx_buf, size);
	301
	302	priv->bytes_to_transfer -= size;
	303	if (priv->bytes_to_transfer < 0)
	304	priv->bytes_to_transfer = 0;
	305	}
	306
17fbb598 ARS	307	/**
	308	* zynq_qspi_chipselect - Select or deselect the chip select line
	309	* @priv: Pointer to the zynq_qspi_priv structure
	310	* @is_on: Select(1) or deselect (0) the chip select line
	311	*/
46d0a991 JT	312	static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
	313	{
	314	u32 confr;
	315	struct zynq_qspi_regs *regs = priv->regs;
	316
	317	confr = readl(&regs->cr);
	318
	319	if (is_on) {
	320	/* Select the slave */
	321	confr &= ~ZYNQ_QSPI_CR_SS_MASK;
	322	confr \|= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
	323	ZYNQ_QSPI_CR_SS_MASK;
	324	} else
	325	/* Deselect the slave */
	326	confr \|= ZYNQ_QSPI_CR_SS_MASK;
	327
	328	writel(confr, &regs->cr);
	329	}
	330
17fbb598	331	/**
46d0a991	332	* zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
17fbb598 ARS	333	* @priv: Pointer to the zynq_qspi_priv structure
17fbb598 ARS	334	* @size: Number of bytes to be copied to fifo
46d0a991 JT	335	*/
	336	static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
	337	{
	338	u32 data = 0;
	339	u32 fifocount = 0;
	340	unsigned len, offset;
	341	struct zynq_qspi_regs *regs = priv->regs;
	342	static const unsigned offsets[4] = {
	343	ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
	344	ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
	345
	346	while ((fifocount < size) &&
	347	(priv->bytes_to_transfer > 0)) {
	348	if (priv->bytes_to_transfer >= 4) {
	349	if (priv->tx_buf) {
	350	memcpy(&data, priv->tx_buf, 4);
	351	priv->tx_buf += 4;
	352	} else {
	353	data = 0;
	354	}
	355	writel(data, &regs->txd0r);
	356	priv->bytes_to_transfer -= 4;
	357	fifocount++;
	358	} else {
	359	/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
	360	if (!(readl(&regs->isr)
	361	& ZYNQ_QSPI_IXR_TXOW_MASK) &&
	362	!priv->rx_buf)
	363	return;
	364	len = priv->bytes_to_transfer;
	365	zynq_qspi_write_data(priv, &data, len);
	366	offset = (priv->rx_buf) ? offsets[0] : offsets[len];
	367	writel(data, &regs->cr + (offset / 4));
	368	}
	369	}
	370	}
	371
17fbb598	372	/**
46d0a991	373	* zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
17fbb598	374	* @priv: Pointer to the zynq_qspi structure
46d0a991 JT	375	*
	376	* This function handles TX empty and Mode Fault interrupts only.
	377	* On TX empty interrupt this function reads the received data from RX FIFO and
	378	* fills the TX FIFO if there is any data remaining to be transferred.
	379	* On Mode Fault interrupt this function indicates that transfer is completed,
	380	* the SPI subsystem will identify the error as the remaining bytes to be
	381	* transferred is non-zero.
	382	*
	383	* returns: 0 for poll timeout
	384	* 1 transfer operation complete
	385	*/
	386	static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
	387	{
	388	struct zynq_qspi_regs *regs = priv->regs;
	389	u32 rxindex = 0;
	390	u32 rxcount;
	391	u32 status, timeout;
	392
	393	/* Poll until any of the interrupt status bits are set */
	394	timeout = get_timer(0);
	395	do {
	396	status = readl(&regs->isr);
	397	} while ((status == 0) &&
f44bd3bc	398	(get_timer(timeout) < ZYNQ_QSPI_WAIT));
46d0a991 JT	399
	400	if (status == 0) {
	401	printf("zynq_qspi_irq_poll: Timeout!\n");
	402	return -ETIMEDOUT;
	403	}
	404
	405	writel(status, &regs->isr);
	406
	407	/* Disable all interrupts */
	408	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
	409	if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) \|\|
	410	(status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
	411	/*
	412	* This bit is set when Tx FIFO has < THRESHOLD entries. We have
	413	* the THRESHOLD value set to 1, so this bit indicates Tx FIFO
	414	* is empty
	415	*/
	416	rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
	417	rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
	418	while ((rxindex < rxcount) &&
	419	(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
	420	/* Read out the data from the RX FIFO */
	421	u32 data;
	422	data = readl(&regs->drxr);
	423
	424	if (priv->bytes_to_receive >= 4) {
	425	if (priv->rx_buf) {
	426	memcpy(priv->rx_buf, &data, 4);
	427	priv->rx_buf += 4;
	428	}
	429	priv->bytes_to_receive -= 4;
	430	} else {
	431	zynq_qspi_read_data(priv, data,
	432	priv->bytes_to_receive);
	433	}
	434	rxindex++;
	435	}
	436
	437	if (priv->bytes_to_transfer) {
	438	/* There is more data to send */
	439	zynq_qspi_fill_tx_fifo(priv,
	440	ZYNQ_QSPI_RXFIFO_THRESHOLD);
	441
	442	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
	443	} else {
	444	/*
	445	* If transfer and receive is completed then only send
	446	* complete signal
	447	*/
	448	if (!priv->bytes_to_receive) {
	449	/* return operation complete */
	450	writel(ZYNQ_QSPI_IXR_ALL_MASK,
	451	&regs->idr);
	452	return 1;
	453	}
	454	}
	455	}
	456
	457	return 0;
	458	}
	459
17fbb598	460	/**
46d0a991	461	* zynq_qspi_start_transfer - Initiates the QSPI transfer
17fbb598	462	* @priv: Pointer to the zynq_qspi_priv structure
46d0a991 JT	463	*
	464	* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
	465	* transfer to be completed.
	466	*
	467	* returns: Number of bytes transferred in the last transfer
	468	*/
	469	static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
	470	{
	471	u32 data = 0;
	472	struct zynq_qspi_regs *regs = priv->regs;
	473
	474	debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
	475	(u32)priv, (u32)priv, priv->len);
	476
	477	priv->bytes_to_transfer = priv->len;
	478	priv->bytes_to_receive = priv->len;
	479
	480	if (priv->len < 4)
	481	zynq_qspi_fill_tx_fifo(priv, priv->len);
	482	else
	483	zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
	484
	485	writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
46d0a991 JT	486
	487	/* wait for completion */
	488	do {
	489	data = zynq_qspi_irq_poll(priv);
	490	} while (data == 0);
	491
	492	return (priv->len) - (priv->bytes_to_transfer);
	493	}
	494
	495	static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
	496	{
	497	unsigned cs_change = 1;
	498	int status = 0;
	499
	500	while (1) {
	501	/* Select the chip if required */
	502	if (cs_change)
	503	zynq_qspi_chipselect(priv, 1);
	504
	505	cs_change = priv->cs_change;
	506
	507	if (!priv->tx_buf && !priv->rx_buf && priv->len) {
	508	status = -1;
	509	break;
	510	}
	511
	512	/* Request the transfer */
	513	if (priv->len) {
	514	status = zynq_qspi_start_transfer(priv);
	515	priv->is_inst = 0;
	516	}
	517
	518	if (status != priv->len) {
	519	if (status > 0)
	520	status = -EMSGSIZE;
	521	debug("zynq_qspi_transfer:%d len:%d\n",
	522	status, priv->len);
	523	break;
	524	}
	525	status = 0;
	526
	527	if (cs_change)
	528	/* Deselect the chip */
	529	zynq_qspi_chipselect(priv, 0);
	530
	531	break;
	532	}
	533
240cd756	534	return status;
46d0a991 JT	535	}
	536
	537	static int zynq_qspi_claim_bus(struct udevice *dev)
	538	{
	539	struct udevice *bus = dev->parent;
	540	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	541	struct zynq_qspi_regs *regs = priv->regs;
	542
	543	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	544
	545	return 0;
	546	}
	547
	548	static int zynq_qspi_release_bus(struct udevice *dev)
	549	{
	550	struct udevice *bus = dev->parent;
	551	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	552	struct zynq_qspi_regs *regs = priv->regs;
	553
	554	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
	555
	556	return 0;
	557	}
	558
	559	static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
	560	const void dout, void din, unsigned long flags)
	561	{
	562	struct udevice *bus = dev->parent;
	563	struct zynq_qspi_priv *priv = dev_get_priv(bus);
8a8d24bd	564	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
46d0a991 JT	565
	566	priv->cs = slave_plat->cs;
	567	priv->tx_buf = dout;
	568	priv->rx_buf = din;
	569	priv->len = bitlen / 8;
	570
e5e0d68f	571	debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
8b85dfc6	572	dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
46d0a991 JT	573
	574	/*
	575	* Festering sore.
	576	* Assume that the beginning of a transfer with bits to
	577	* transmit must contain a device command.
	578	*/
	579	if (dout && flags & SPI_XFER_BEGIN)
	580	priv->is_inst = 1;
	581	else
	582	priv->is_inst = 0;
	583
	584	if (flags & SPI_XFER_END)
	585	priv->cs_change = 1;
	586	else
	587	priv->cs_change = 0;
	588
	589	zynq_qspi_transfer(priv);
	590
	591	return 0;
	592	}
	593
	594	static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
	595	{
0fd3d911	596	struct zynq_qspi_plat *plat = dev_get_plat(bus);
46d0a991 JT	597	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	598	struct zynq_qspi_regs *regs = priv->regs;
	599	uint32_t confr;
	600	u8 baud_rate_val = 0;
	601
	602	if (speed > plat->frequency)
	603	speed = plat->frequency;
	604
	605	/* Set the clock frequency */
	606	confr = readl(&regs->cr);
	607	if (speed == 0) {
	608	/* Set baudrate x8, if the freq is 0 */
	609	baud_rate_val = 0x2;
	610	} else if (plat->speed_hz != speed) {
	611	while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
	612	((plat->frequency /
	613	(2 << baud_rate_val)) > speed))
	614	baud_rate_val++;
	615
	616	plat->speed_hz = speed / (2 << baud_rate_val);
	617	}
	618	confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
	619	confr \|= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
	620
	621	writel(confr, &regs->cr);
	622	priv->freq = speed;
	623
e5e0d68f	624	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
46d0a991 JT	625
	626	return 0;
	627	}
	628
	629	static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
	630	{
	631	struct zynq_qspi_priv *priv = dev_get_priv(bus);
	632	struct zynq_qspi_regs *regs = priv->regs;
	633	uint32_t confr;
	634
	635	/* Set the SPI Clock phase and polarities */
	636	confr = readl(&regs->cr);
	637	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK \| ZYNQ_QSPI_CR_CPOL_MASK);
	638
2775e918	639	if (mode & SPI_CPHA)
46d0a991	640	confr \|= ZYNQ_QSPI_CR_CPHA_MASK;
2775e918	641	if (mode & SPI_CPOL)
46d0a991 JT	642	confr \|= ZYNQ_QSPI_CR_CPOL_MASK;
	643
	644	writel(confr, &regs->cr);
	645	priv->mode = mode;
	646
e5e0d68f	647	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
46d0a991 JT	648
	649	return 0;
	650	}
	651
	652	static const struct dm_spi_ops zynq_qspi_ops = {
	653	.claim_bus = zynq_qspi_claim_bus,
	654	.release_bus = zynq_qspi_release_bus,
	655	.xfer = zynq_qspi_xfer,
	656	.set_speed = zynq_qspi_set_speed,
	657	.set_mode = zynq_qspi_set_mode,
	658	};
	659
	660	static const struct udevice_id zynq_qspi_ids[] = {
	661	{ .compatible = "xlnx,zynq-qspi-1.0" },
	662	{ }
	663	};
	664
	665	U_BOOT_DRIVER(zynq_qspi) = {
	666	.name = "zynq_qspi",
	667	.id = UCLASS_SPI,
	668	.of_match = zynq_qspi_ids,
	669	.ops = &zynq_qspi_ops,
d1998a9f	670	.of_to_plat = zynq_qspi_of_to_plat,
8a8d24bd	671	.plat_auto = sizeof(struct zynq_qspi_plat),
41575d8e	672	.priv_auto = sizeof(struct zynq_qspi_priv),
46d0a991 JT	673	.probe = zynq_qspi_probe,
46d0a991 JT	674	};