[u-boot.git] / drivers / i2c / nx_i2c.c

#include <common.h>
#include <errno.h>
#include <dm.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/nexell.h>
#include <asm/arch/reset.h>
#include <asm/arch/clk.h>
#include <asm/arch/nx_gpio.h>
#include <asm/global_data.h>
#include <linux/delay.h>

#define I2C_WRITE       0
#define I2C_READ        1

#define I2CSTAT_MTM     0xC0    /* Master Transmit Mode */
#define I2CSTAT_MRM     0x80    /* Master Receive Mode */
#define I2CSTAT_BSY     0x20    /* Read: Bus Busy */
#define I2CSTAT_SS      0x20    /* Write: START (1) / STOP (0) */
#define I2CSTAT_RXTXEN  0x10    /* Rx/Tx enable */
#define I2CSTAT_ABT	0x08	/* Arbitration bit */
#define I2CSTAT_NACK    0x01    /* Nack bit */
#define I2CCON_IRCLR    0x100   /* Interrupt Clear bit  */
#define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
#define I2CCON_TCP256	0x40    /* Tx-clock prescaler: 16 (0) / 256 (1) */
#define I2CCON_IRENB	0x20	/* Interrupt Enable bit  */
#define I2CCON_IRPND    0x10    /* Interrupt pending bit */
#define I2CCON_TCDMSK	0x0F    /* I2C-bus transmit clock divider bit mask */

#ifdef CONFIG_ARCH_S5P6818
#define SDADLY_CLKSTEP	5	/* SDA delay: Reg. val. is multiple of 5 clks */
#define SDADLY_MAX	3	/* SDA delay: Max. reg. value is 3 */
#define I2CLC_FILTER	0x04	/* SDA filter on */
#else
#define STOPCON_CLR	0x01	/* Clock Line Release */
#define STOPCON_DLR	0x02	/* Data Line Release */
#define STOPCON_NAG	0x04	/* not-ackn. generation and data shift cont. */
#endif

#define I2C_TIMEOUT_MS	10      /* 10 ms */

#define I2C_M_NOSTOP	0x100

#define MAX_I2C_NUM 3

#define DEFAULT_SPEED   100000  /* default I2C speed [Hz] */

DECLARE_GLOBAL_DATA_PTR;

struct nx_i2c_regs {
	uint     iiccon;
	uint     iicstat;
	uint     iicadd;
	uint     iicds;
#ifdef CONFIG_ARCH_S5P6818
	/* S5P6818: Offset 0x10 is Line Control Register (SDA-delay, Filter) */
	uint     iiclc;
#else
	/* S5P4418: Offset 0x10 is Stop Control Register */
	uint     iicstopcon;
#endif
};

struct nx_i2c_bus {
	uint bus_num;
	struct nx_i2c_regs *regs;
	uint speed;
	uint target_speed;
#ifdef CONFIG_ARCH_S5P6818
	uint sda_delay;
#else
	/* setup time for Stop condition [us] */
	uint tsu_stop;
#endif
};

/* s5pxx18 i2c must be reset before enabled */
static void i2c_reset(int ch)
{
	int rst_id = RESET_ID_I2C0 + ch;

	nx_rstcon_setrst(rst_id, 0);
	nx_rstcon_setrst(rst_id, 1);
}

static uint i2c_get_clkrate(struct nx_i2c_bus *bus)
{
	struct clk *clk;
	int index = bus->bus_num;
	char name[50] = {0, };

	sprintf(name, "%s.%d", DEV_NAME_I2C, index);
	clk = clk_get((const char *)name);
	if (!clk)
		return -1;

	return clk_get_rate(clk);
}

static uint i2c_set_clk(struct nx_i2c_bus *bus, uint enb)
{
	struct clk *clk;
	char name[50];

	sprintf(name, "%s.%d", DEV_NAME_I2C, bus->bus_num);
	clk = clk_get((const char *)name);
	if (!clk) {
		debug("%s(): clk_get(%s) error!\n",
		      __func__, (const char *)name);
		return -EINVAL;
	}

	clk_disable(clk);
	if (enb)
		clk_enable(clk);

	return 0;
}

#ifdef CONFIG_ARCH_S5P6818
/* Set SDA line delay, not available at S5P4418 */
static int nx_i2c_set_sda_delay(struct nx_i2c_bus *bus)
{
	struct nx_i2c_regs *i2c = bus->regs;
	uint pclk = 0;
	uint t_pclk = 0;
	uint delay = 0;

	/* get input clock of the I2C-controller */
	pclk = i2c_get_clkrate(bus);

	if (bus->sda_delay) {
		/* t_pclk = period time of one pclk [ns] */
		t_pclk = DIV_ROUND_UP(1000, pclk / 1000000);
		/* delay = number of pclks required for sda_delay [ns] */
		delay = DIV_ROUND_UP(bus->sda_delay, t_pclk);
		/* delay = register value (step of 5 clocks) */
		delay = DIV_ROUND_UP(delay, SDADLY_CLKSTEP);
		/* max. possible register value = 3 */
		if (delay > SDADLY_MAX) {
			delay = SDADLY_MAX;
			debug("%s(): sda-delay des.: %dns, sat. to max.: %dns (granularity: %dns)\n",
			      __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
			      t_pclk * SDADLY_CLKSTEP);
		} else {
			debug("%s(): sda-delay des.: %dns, act.: %dns (granularity: %dns)\n",
			      __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
			      t_pclk * SDADLY_CLKSTEP);
		}

		delay |= I2CLC_FILTER;
	} else {
		delay = 0;
		debug("%s(): sda-delay = 0\n", __func__);
	}

	delay &= 0x7;
	writel(delay, &i2c->iiclc);

	return 0;
}
#endif

static int nx_i2c_set_bus_speed(struct udevice *dev, uint speed)
{
	struct nx_i2c_bus *bus = dev_get_priv(dev);
	struct nx_i2c_regs *i2c = bus->regs;
	unsigned long pclk, pres = 16, div;

	if (i2c_set_clk(bus, 1))
		return -EINVAL;

	/* get input clock of the I2C-controller */
	pclk = i2c_get_clkrate(bus);

	/* calculate prescaler and divisor values */
	if ((pclk / pres / (16 + 1)) > speed)
		/* prescaler value 16 is too less --> set to 256 */
		pres = 256;

	div = 0;
	/* actual divider = div + 1 */
	while ((pclk / pres / (div + 1)) > speed)
		div++;

	if (div > 0xF) {
		debug("%s(): pres==%ld, div==0x%lx is saturated to 0xF !)\n",
		      __func__, pres, div);
		div = 0xF;
	} else {
		debug("%s(): pres==%ld, div==0x%lx)\n", __func__, pres, div);
	}

	/* set Tx-clock divisor and prescaler values */
	writel((div & I2CCON_TCDMSK) | ((pres == 256) ? I2CCON_TCP256 : 0),
	       &i2c->iiccon);

	/* init to SLAVE REVEIVE and set slaveaddr */
	writel(0, &i2c->iicstat);
	writel(0x00, &i2c->iicadd);

	/* program Master Transmit (and implicit STOP) */
	writel(I2CSTAT_MTM | I2CSTAT_RXTXEN, &i2c->iicstat);

	/* calculate actual I2C speed [Hz] */
	bus->speed = pclk / ((div + 1) * pres);
	debug("%s(): speed des.: %dHz, act.: %dHz\n",
	      __func__, speed, bus->speed);

#ifdef CONFIG_ARCH_S5P6818
	nx_i2c_set_sda_delay(bus);
#else
	/* setup time for Stop condition [us], min. 4us @ 100kHz I2C-clock */
	bus->tsu_stop = DIV_ROUND_UP(400, bus->speed / 1000);
#endif

	if (i2c_set_clk(bus, 0))
		return -EINVAL;
	return 0;
}

static void i2c_process_node(struct udevice *dev)
{
	struct nx_i2c_bus *bus = dev_get_priv(dev);

	bus->target_speed = dev_read_s32_default(dev, "clock-frequency",
						 DEFAULT_SPEED);
#ifdef CONFIG_ARCH_S5P6818
	bus->sda_delay = dev_read_s32_default(dev, "i2c-sda-delay-ns", 0);
#endif
}

static int nx_i2c_probe(struct udevice *dev)
{
	struct nx_i2c_bus *bus = dev_get_priv(dev);
	fdt_addr_t addr;

	/* get regs = i2c base address */
	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;
	bus->regs = (struct nx_i2c_regs *)addr;

	bus->bus_num = dev_seq(dev);

	/* i2c node parsing */
	i2c_process_node(dev);
	if (!bus->target_speed)
		return -ENODEV;

	/* reset */
	i2c_reset(bus->bus_num);

	return 0;
}

/* i2c bus busy check */
static int i2c_is_busy(struct nx_i2c_regs *i2c)
{
	ulong start_time;

	start_time = get_timer(0);
	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
		if (get_timer(start_time) > I2C_TIMEOUT_MS) {
			debug("Timeout\n");
			return -EBUSY;
		}
	}
	return 0;
}

/* irq enable/disable functions */
static void i2c_enable_irq(struct nx_i2c_regs *i2c)
{
	unsigned int reg;

	reg = readl(&i2c->iiccon);
	reg |= I2CCON_IRENB;
	writel(reg, &i2c->iiccon);
}

/* irq clear function */
static void i2c_clear_irq(struct nx_i2c_regs *i2c)
{
	unsigned int reg;

	reg = readl(&i2c->iiccon);
	/* reset interrupt pending flag */
	reg &= ~(I2CCON_IRPND);
	/*
	 * Interrupt must also be cleared!
	 * Otherwise linux boot may hang after:
	 *     [    0.436000] NetLabel:  unlabeled traffic allowed by default
	 * Next would be:
	 *     [    0.442000] clocksource: Switched to clocksource source timer
	 */
	reg |= I2CCON_IRCLR;
	writel(reg, &i2c->iiccon);
}

/* ack enable functions */
static void i2c_enable_ack(struct nx_i2c_regs *i2c)
{
	unsigned int reg;

	reg = readl(&i2c->iiccon);
	reg |= I2CCON_ACKGEN;
	writel(reg, &i2c->iiccon);
}

static void i2c_send_stop(struct nx_i2c_bus *bus)
{
	struct nx_i2c_regs *i2c = bus->regs;

	if (IS_ENABLED(CONFIG_ARCH_S5P6818)) {
		unsigned int reg;

		reg = readl(&i2c->iicstat);
		reg |= I2CSTAT_MRM | I2CSTAT_RXTXEN;
		reg &= (~I2CSTAT_SS);

		writel(reg, &i2c->iicstat);
		i2c_clear_irq(i2c);
	} else {  /* S5P4418 */
		writel(STOPCON_NAG, &i2c->iicstopcon);

		i2c_clear_irq(i2c);

		/*
		 * Clock Line Release --> SDC changes from Low to High and
		 * SDA from High to Low
		 */
		writel(STOPCON_CLR, &i2c->iicstopcon);

		/* Hold SDA Low (Setup Time for Stop condition) */
		udelay(bus->tsu_stop);

		i2c_clear_irq(i2c);

		/* Master Receive Mode Stop --> SDA becomes High */
		writel(I2CSTAT_MRM, &i2c->iicstat);
	}
}

static int wait_for_xfer(struct nx_i2c_regs *i2c)
{
	unsigned long start_time = get_timer(0);

	do {
		if (readl(&i2c->iiccon) & I2CCON_IRPND)
			/* return -EREMOTEIO if not Acknowledged, otherwise 0 */
			return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
				-EREMOTEIO : 0;
	} while (get_timer(start_time) < I2C_TIMEOUT_MS);

	return -ETIMEDOUT;
}

static int i2c_transfer(struct nx_i2c_regs *i2c,
			uchar cmd_type,
			uchar chip_addr,
			uchar addr[],
			uchar addr_len,
			uchar data[],
			unsigned short data_len,
			uint seq)
{
	uint status;
	int i = 0, result;

	/* Note: data_len = 0 is supported for "probe_chip" */

	i2c_enable_irq(i2c);
	i2c_enable_ack(i2c);

	/* Get the slave chip address going */
	/* Enable Rx/Tx */
	writel(I2CSTAT_RXTXEN, &i2c->iicstat);

	writel(chip_addr, &i2c->iicds);
	status = I2CSTAT_RXTXEN | I2CSTAT_SS;
	if (cmd_type == I2C_WRITE || (addr && addr_len))
		status |= I2CSTAT_MTM;
	else
		status |= I2CSTAT_MRM;

	writel(status, &i2c->iicstat);
	if (seq)
		i2c_clear_irq(i2c);

	/* Wait for chip address to transmit. */
	result = wait_for_xfer(i2c);
	if (result) {
		debug("%s: transmitting chip address failed\n", __func__);
		goto bailout;
	}

	/* If register address needs to be transmitted - do it now. */
	if (addr && addr_len) {  /* register addr */
		while ((i < addr_len) && !result) {
			writel(addr[i++], &i2c->iicds);
			i2c_clear_irq(i2c);
			result = wait_for_xfer(i2c);
		}

		i = 0;
		if (result) {
			debug("%s: transmitting register address failed\n",
			      __func__);
			goto bailout;
		}
	}

	switch (cmd_type) {
	case I2C_WRITE:
		while ((i < data_len) && !result) {
			writel(data[i++], &i2c->iicds);
			i2c_clear_irq(i2c);
			result = wait_for_xfer(i2c);
		}
		break;
	case I2C_READ:
		if (addr && addr_len) {
			/*
			 * Register address has been sent, now send slave chip
			 * address again to start the actual read transaction.
			 */
			writel(chip_addr, &i2c->iicds);

			/* Generate a re-START. */
			writel(I2CSTAT_MRM | I2CSTAT_RXTXEN |
			       I2CSTAT_SS, &i2c->iicstat);
			i2c_clear_irq(i2c);
			result = wait_for_xfer(i2c);
			if (result) {
				debug("%s: I2C_READ: sending chip addr. failed\n",
				      __func__);
				goto bailout;
			}
		}

		while ((i < data_len) && !result) {
			/* disable ACK for final READ */
			if (i == data_len - 1)
				clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);

			i2c_clear_irq(i2c);
			result = wait_for_xfer(i2c);
			data[i++] = readb(&i2c->iicds);
		}

		if (result == -EREMOTEIO)
			 /* Not Acknowledged --> normal terminated read. */
			result = 0;
		else if (result == -ETIMEDOUT)
			debug("%s: I2C_READ: time out\n", __func__);
		else
			debug("%s: I2C_READ: read not terminated with NACK\n",
			      __func__);
		break;

	default:
		debug("%s: bad call\n", __func__);
		result = -EINVAL;
		break;
	}

bailout:
	return result;
}

static int nx_i2c_read(struct udevice *dev, uchar chip_addr, uint addr,
		       uint alen, uchar *buffer, uint len, uint seq)
{
	struct nx_i2c_bus *i2c;
	uchar xaddr[4];
	int ret;

	i2c = dev_get_priv(dev);
	if (!i2c)
		return -EFAULT;

	if (alen > 4) {
		debug("I2C read: addr len %d not supported\n", alen);
		return -EADDRNOTAVAIL;
	}

	if (alen > 0)
		xaddr[0] = (addr >> 24) & 0xFF;

	if (alen > 0) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}

	ret = i2c_transfer(i2c->regs, I2C_READ, chip_addr << 1,
			   &xaddr[4 - alen], alen, buffer, len, seq);

	if (ret) {
		debug("I2C read failed %d\n", ret);
		return -EIO;
	}

	return 0;
}

static int nx_i2c_write(struct udevice *dev, uchar chip_addr, uint addr,
			uint alen, uchar *buffer, uint len, uint seq)
{
	struct nx_i2c_bus *i2c;
	uchar xaddr[4];
	int ret;

	i2c = dev_get_priv(dev);
	if (!i2c)
		return -EFAULT;

	if (alen > 4) {
		debug("I2C write: addr len %d not supported\n", alen);
		return -EINVAL;
	}

	if (alen > 0) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}

	ret = i2c_transfer(i2c->regs, I2C_WRITE, chip_addr << 1,
			   &xaddr[4 - alen], alen, buffer, len, seq);
	if (ret) {
		debug("I2C write failed %d\n", ret);
		return -EIO;
	}

	return 0;
}

static int nx_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
{
	struct nx_i2c_bus *bus = dev_get_priv(dev);
	struct nx_i2c_regs *i2c = bus->regs;
	int ret;
	int i;

	/* The power loss by the clock, only during on/off. */
	ret = i2c_set_clk(bus, 1);

	if (!ret)
		/* Bus State(Busy) check  */
		ret = i2c_is_busy(i2c);
	if (!ret) {
		for (i = 0; i < nmsgs; msg++, i++) {
			if (msg->flags & I2C_M_RD) {
				ret = nx_i2c_read(dev, msg->addr, 0, 0,
						  msg->buf, msg->len, i);
			} else {
				ret = nx_i2c_write(dev, msg->addr, 0, 0,
						   msg->buf, msg->len, i);
			}

			if (ret) {
				debug("i2c_xfer: error sending\n");
				ret = -EREMOTEIO;
			}
		}

		i2c_send_stop(bus);
		if (i2c_set_clk(bus, 0))
			ret = -EINVAL;
	}

	return ret;
};

static int nx_i2c_probe_chip(struct udevice *dev, u32 chip_addr,
			     u32 chip_flags)
{
	int ret;
	struct nx_i2c_bus *bus = dev_get_priv(dev);

	ret = i2c_set_clk(bus, 1);

	if (!ret) {
		/*
		 * Send Chip Address only
		 * --> I2C transfer with data length and address length = 0.
		 * If there is a Slave, i2c_transfer() returns 0 (acknowledge
		 * transfer).
		 * I2C_WRITE must be used in order Master Transmit Mode is
		 * selected. Otherwise (in Master Receive Mode, I2C_READ)
		 * sending the stop condition below is not working (SDA does
		 * not transit to High).
		 */
		ret = i2c_transfer(bus->regs, I2C_WRITE, (uchar)chip_addr << 1,
				   NULL, 0, NULL, 0, 0);

		i2c_send_stop(bus);
		if (i2c_set_clk(bus, 0))
			ret = -EINVAL;
	}

	return ret;
}

static const struct dm_i2c_ops nx_i2c_ops = {
	.xfer		= nx_i2c_xfer,
	.probe_chip	= nx_i2c_probe_chip,
	.set_bus_speed	= nx_i2c_set_bus_speed,
};

static const struct udevice_id nx_i2c_ids[] = {
	{ .compatible = "nexell,s5pxx18-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_nexell) = {
	.name		= "i2c_nexell",
	.id		= UCLASS_I2C,
	.of_match	= nx_i2c_ids,
	.probe		= nx_i2c_probe,
	.priv_auto	= sizeof(struct nx_i2c_bus),
	.ops		= &nx_i2c_ops,
};
Commit	Line	Data
c25e9e04 SB	1	#include <common.h>
	2	#include <errno.h>
	3	#include <dm.h>
	4	#include <i2c.h>
	5	#include <log.h>
	6	#include <asm/arch/nexell.h>
	7	#include <asm/arch/reset.h>
	8	#include <asm/arch/clk.h>
	9	#include <asm/arch/nx_gpio.h>
401d1c4f	10	#include <asm/global_data.h>
c25e9e04 SB	11	#include <linux/delay.h>
	12
	13	#define I2C_WRITE 0
	14	#define I2C_READ 1
	15
	16	#define I2CSTAT_MTM 0xC0 /* Master Transmit Mode */
	17	#define I2CSTAT_MRM 0x80 /* Master Receive Mode */
	18	#define I2CSTAT_BSY 0x20 /* Read: Bus Busy */
	19	#define I2CSTAT_SS 0x20 /* Write: START (1) / STOP (0) */
	20	#define I2CSTAT_RXTXEN 0x10 /* Rx/Tx enable */
	21	#define I2CSTAT_ABT 0x08 /* Arbitration bit */
	22	#define I2CSTAT_NACK 0x01 /* Nack bit */
	23	#define I2CCON_IRCLR 0x100 /* Interrupt Clear bit */
	24	#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
	25	#define I2CCON_TCP256 0x40 /* Tx-clock prescaler: 16 (0) / 256 (1) */
	26	#define I2CCON_IRENB 0x20 /* Interrupt Enable bit */
	27	#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
	28	#define I2CCON_TCDMSK 0x0F /* I2C-bus transmit clock divider bit mask */
	29
	30	#ifdef CONFIG_ARCH_S5P6818
	31	#define SDADLY_CLKSTEP 5 /* SDA delay: Reg. val. is multiple of 5 clks */
	32	#define SDADLY_MAX 3 /* SDA delay: Max. reg. value is 3 */
	33	#define I2CLC_FILTER 0x04 /* SDA filter on */
	34	#else
	35	#define STOPCON_CLR 0x01 /* Clock Line Release */
	36	#define STOPCON_DLR 0x02 /* Data Line Release */
	37	#define STOPCON_NAG 0x04 /* not-ackn. generation and data shift cont. */
	38	#endif
	39
	40	#define I2C_TIMEOUT_MS 10 /* 10 ms */
	41
	42	#define I2C_M_NOSTOP 0x100
	43
	44	#define MAX_I2C_NUM 3
	45
	46	#define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */
	47
	48	DECLARE_GLOBAL_DATA_PTR;
	49
	50	struct nx_i2c_regs {
	51	uint iiccon;
	52	uint iicstat;
	53	uint iicadd;
	54	uint iicds;
	55	#ifdef CONFIG_ARCH_S5P6818
	56	/* S5P6818: Offset 0x10 is Line Control Register (SDA-delay, Filter) */
	57	uint iiclc;
	58	#else
	59	/* S5P4418: Offset 0x10 is Stop Control Register */
	60	uint iicstopcon;
	61	#endif
	62	};
	63
	64	struct nx_i2c_bus {
	65	uint bus_num;
	66	struct nx_i2c_regs *regs;
	67	uint speed;
	68	uint target_speed;
	69	#ifdef CONFIG_ARCH_S5P6818
	70	uint sda_delay;
	71	#else
	72	/* setup time for Stop condition [us] */
	73	uint tsu_stop;
	74	#endif
75	};
76
77	/* s5pxx18 i2c must be reset before enabled */
78	static void i2c_reset(int ch)
79	{
80	int rst_id = RESET_ID_I2C0 + ch;
81
82	nx_rstcon_setrst(rst_id, 0);
83	nx_rstcon_setrst(rst_id, 1);
84	}
85
86	static uint i2c_get_clkrate(struct nx_i2c_bus *bus)
87	{
88	struct clk *clk;
89	int index = bus->bus_num;
90	char name[50] = {0, };
91
92	sprintf(name, "%s.%d", DEV_NAME_I2C, index);
93	clk = clk_get((const char *)name);
94	if (!clk)
95	return -1;
96
97	return clk_get_rate(clk);
98	}
99
100	static uint i2c_set_clk(struct nx_i2c_bus *bus, uint enb)
101	{
102	struct clk *clk;
103	char name[50];
104
105	sprintf(name, "%s.%d", DEV_NAME_I2C, bus->bus_num);
106	clk = clk_get((const char *)name);
107	if (!clk) {
108	debug("%s(): clk_get(%s) error!\n",
109	__func__, (const char *)name);
110	return -EINVAL;
111	}
112
113	clk_disable(clk);
114	if (enb)
115	clk_enable(clk);
116
117	return 0;
118	}
119
120	#ifdef CONFIG_ARCH_S5P6818
121	/* Set SDA line delay, not available at S5P4418 */
122	static int nx_i2c_set_sda_delay(struct nx_i2c_bus *bus)
123	{
124	struct nx_i2c_regs *i2c = bus->regs;
125	uint pclk = 0;
126	uint t_pclk = 0;
127	uint delay = 0;
128
129	/* get input clock of the I2C-controller */
130	pclk = i2c_get_clkrate(bus);
131
132	if (bus->sda_delay) {
133	/* t_pclk = period time of one pclk [ns] */
134	t_pclk = DIV_ROUND_UP(1000, pclk / 1000000);
135	/* delay = number of pclks required for sda_delay [ns] */
136	delay = DIV_ROUND_UP(bus->sda_delay, t_pclk);
137	/* delay = register value (step of 5 clocks) */
138	delay = DIV_ROUND_UP(delay, SDADLY_CLKSTEP);
139	/* max. possible register value = 3 */
140	if (delay > SDADLY_MAX) {
141	delay = SDADLY_MAX;
142	debug("%s(): sda-delay des.: %dns, sat. to max.: %dns (granularity: %dns)\n",
143	__func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
144	t_pclk * SDADLY_CLKSTEP);
145	} else {
146	debug("%s(): sda-delay des.: %dns, act.: %dns (granularity: %dns)\n",
147	__func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
148	t_pclk * SDADLY_CLKSTEP);
149	}
150
151	delay \|= I2CLC_FILTER;
152	} else {
153	delay = 0;
154	debug("%s(): sda-delay = 0\n", __func__);
155	}
156
157	delay &= 0x7;
158	writel(delay, &i2c->iiclc);
159
160	return 0;
161	}
162	#endif
163
164	static int nx_i2c_set_bus_speed(struct udevice *dev, uint speed)
165	{
166	struct nx_i2c_bus *bus = dev_get_priv(dev);
167	struct nx_i2c_regs *i2c = bus->regs;
168	unsigned long pclk, pres = 16, div;
169
170	if (i2c_set_clk(bus, 1))
171	return -EINVAL;
172
173	/* get input clock of the I2C-controller */
174	pclk = i2c_get_clkrate(bus);
175
176	/* calculate prescaler and divisor values */
177	if ((pclk / pres / (16 + 1)) > speed)
178	/* prescaler value 16 is too less --> set to 256 */
179	pres = 256;
180
181	div = 0;
182	/* actual divider = div + 1 */
183	while ((pclk / pres / (div + 1)) > speed)
184	div++;
185
186	if (div > 0xF) {
187	debug("%s(): pres==%ld, div==0x%lx is saturated to 0xF !)\n",
188	__func__, pres, div);
189	div = 0xF;
190	} else {
191	debug("%s(): pres==%ld, div==0x%lx)\n", __func__, pres, div);
192	}
193
194	/* set Tx-clock divisor and prescaler values */
195	writel((div & I2CCON_TCDMSK) \| ((pres == 256) ? I2CCON_TCP256 : 0),
196	&i2c->iiccon);
197
198	/* init to SLAVE REVEIVE and set slaveaddr */
199	writel(0, &i2c->iicstat);
200	writel(0x00, &i2c->iicadd);
201
202	/* program Master Transmit (and implicit STOP) */
203	writel(I2CSTAT_MTM \| I2CSTAT_RXTXEN, &i2c->iicstat);
204
205	/* calculate actual I2C speed [Hz] */
206	bus->speed = pclk / ((div + 1) * pres);
207	debug("%s(): speed des.: %dHz, act.: %dHz\n",
208	__func__, speed, bus->speed);
209
210	#ifdef CONFIG_ARCH_S5P6818
211	nx_i2c_set_sda_delay(bus);
212	#else
213	/* setup time for Stop condition [us], min. 4us @ 100kHz I2C-clock */
214	bus->tsu_stop = DIV_ROUND_UP(400, bus->speed / 1000);
215	#endif
216
217	if (i2c_set_clk(bus, 0))
218	return -EINVAL;
219	return 0;
220	}
221
222	static void i2c_process_node(struct udevice *dev)
223	{
224	struct nx_i2c_bus *bus = dev_get_priv(dev);
225
226	bus->target_speed = dev_read_s32_default(dev, "clock-frequency",
227	DEFAULT_SPEED);
228	#ifdef CONFIG_ARCH_S5P6818
229	bus->sda_delay = dev_read_s32_default(dev, "i2c-sda-delay-ns", 0);
230	#endif
231	}
232
233	static int nx_i2c_probe(struct udevice *dev)
234	{
235	struct nx_i2c_bus *bus = dev_get_priv(dev);
236	fdt_addr_t addr;
237
238	/* get regs = i2c base address */
239	addr = devfdt_get_addr(dev);
240	if (addr == FDT_ADDR_T_NONE)
241	return -EINVAL;
242	bus->regs = (struct nx_i2c_regs *)addr;
243
8b85dfc6	244	bus->bus_num = dev_seq(dev);
c25e9e04 SB	245
	246	/* i2c node parsing */
	247	i2c_process_node(dev);
	248	if (!bus->target_speed)
	249	return -ENODEV;
	250
	251	/* reset */
	252	i2c_reset(bus->bus_num);
	253
	254	return 0;
	255	}
	256
	257	/* i2c bus busy check */
	258	static int i2c_is_busy(struct nx_i2c_regs *i2c)
	259	{
	260	ulong start_time;
	261
	262	start_time = get_timer(0);
	263	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
	264	if (get_timer(start_time) > I2C_TIMEOUT_MS) {
	265	debug("Timeout\n");
	266	return -EBUSY;
	267	}
	268	}
	269	return 0;
	270	}
	271
	272	/* irq enable/disable functions */
	273	static void i2c_enable_irq(struct nx_i2c_regs *i2c)
	274	{
	275	unsigned int reg;
	276
	277	reg = readl(&i2c->iiccon);
	278	reg \|= I2CCON_IRENB;
	279	writel(reg, &i2c->iiccon);
	280	}
	281
	282	/* irq clear function */
	283	static void i2c_clear_irq(struct nx_i2c_regs *i2c)
	284	{
	285	unsigned int reg;
	286
	287	reg = readl(&i2c->iiccon);
	288	/* reset interrupt pending flag */
	289	reg &= ~(I2CCON_IRPND);
	290	/*
	291	* Interrupt must also be cleared!
	292	* Otherwise linux boot may hang after:
	293	* [ 0.436000] NetLabel: unlabeled traffic allowed by default
	294	* Next would be:
	295	* [ 0.442000] clocksource: Switched to clocksource source timer
	296	*/
	297	reg \|= I2CCON_IRCLR;
	298	writel(reg, &i2c->iiccon);
	299	}
	300
	301	/* ack enable functions */
	302	static void i2c_enable_ack(struct nx_i2c_regs *i2c)
	303	{
	304	unsigned int reg;
	305
	306	reg = readl(&i2c->iiccon);
	307	reg \|= I2CCON_ACKGEN;
	308	writel(reg, &i2c->iiccon);
309	}
310
311	static void i2c_send_stop(struct nx_i2c_bus *bus)
312	{
313	struct nx_i2c_regs *i2c = bus->regs;
314
315	if (IS_ENABLED(CONFIG_ARCH_S5P6818)) {
316	unsigned int reg;
317
318	reg = readl(&i2c->iicstat);
319	reg \|= I2CSTAT_MRM \| I2CSTAT_RXTXEN;
320	reg &= (~I2CSTAT_SS);
321
322	writel(reg, &i2c->iicstat);
323	i2c_clear_irq(i2c);
324	} else { /* S5P4418 */
325	writel(STOPCON_NAG, &i2c->iicstopcon);
326
327	i2c_clear_irq(i2c);
328
329	/*
330	* Clock Line Release --> SDC changes from Low to High and
331	* SDA from High to Low
332	*/
333	writel(STOPCON_CLR, &i2c->iicstopcon);
334
335	/* Hold SDA Low (Setup Time for Stop condition) */
336	udelay(bus->tsu_stop);
337
338	i2c_clear_irq(i2c);
339
340	/* Master Receive Mode Stop --> SDA becomes High */
341	writel(I2CSTAT_MRM, &i2c->iicstat);
342	}
343	}
344
345	static int wait_for_xfer(struct nx_i2c_regs *i2c)
346	{
347	unsigned long start_time = get_timer(0);
348
349	do {
350	if (readl(&i2c->iiccon) & I2CCON_IRPND)
351	/* return -EREMOTEIO if not Acknowledged, otherwise 0 */
352	return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
353	-EREMOTEIO : 0;
354	} while (get_timer(start_time) < I2C_TIMEOUT_MS);
355
356	return -ETIMEDOUT;
357	}
358
359	static int i2c_transfer(struct nx_i2c_regs *i2c,
360	uchar cmd_type,
361	uchar chip_addr,
362	uchar addr[],
363	uchar addr_len,
364	uchar data[],
365	unsigned short data_len,
366	uint seq)
367	{
368	uint status;
369	int i = 0, result;
370
371	/* Note: data_len = 0 is supported for "probe_chip" */
372
373	i2c_enable_irq(i2c);
374	i2c_enable_ack(i2c);
375
376	/* Get the slave chip address going */
377	/* Enable Rx/Tx */
378	writel(I2CSTAT_RXTXEN, &i2c->iicstat);
379
380	writel(chip_addr, &i2c->iicds);
381	status = I2CSTAT_RXTXEN \| I2CSTAT_SS;
382	if (cmd_type == I2C_WRITE \|\| (addr && addr_len))
383	status \|= I2CSTAT_MTM;
384	else
385	status \|= I2CSTAT_MRM;
386
387	writel(status, &i2c->iicstat);
388	if (seq)
389	i2c_clear_irq(i2c);
390
391	/* Wait for chip address to transmit. */
392	result = wait_for_xfer(i2c);
393	if (result) {
394	debug("%s: transmitting chip address failed\n", __func__);
395	goto bailout;
396	}
397
398	/* If register address needs to be transmitted - do it now. */
399	if (addr && addr_len) { /* register addr */
400	while ((i < addr_len) && !result) {
401	writel(addr[i++], &i2c->iicds);
402	i2c_clear_irq(i2c);
403	result = wait_for_xfer(i2c);
404	}
405
406	i = 0;
407	if (result) {
408	debug("%s: transmitting register address failed\n",
409	__func__);
410	goto bailout;
411	}
412	}
413
414	switch (cmd_type) {
415	case I2C_WRITE:
416	while ((i < data_len) && !result) {
417	writel(data[i++], &i2c->iicds);
418	i2c_clear_irq(i2c);
419	result = wait_for_xfer(i2c);
420	}
421	break;
422	case I2C_READ:
423	if (addr && addr_len) {
424	/*
425	* Register address has been sent, now send slave chip
426	* address again to start the actual read transaction.
427	*/
428	writel(chip_addr, &i2c->iicds);
429
430	/* Generate a re-START. */
431	writel(I2CSTAT_MRM \| I2CSTAT_RXTXEN \|
432	I2CSTAT_SS, &i2c->iicstat);
433	i2c_clear_irq(i2c);
434	result = wait_for_xfer(i2c);
435	if (result) {
436	debug("%s: I2C_READ: sending chip addr. failed\n",
437	__func__);
438	goto bailout;
439	}
440	}
441
442	while ((i < data_len) && !result) {
443	/* disable ACK for final READ */
444	if (i == data_len - 1)
445	clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
446
447	i2c_clear_irq(i2c);
448	result = wait_for_xfer(i2c);
449	data[i++] = readb(&i2c->iicds);
450	}
451
452	if (result == -EREMOTEIO)
453	/* Not Acknowledged --> normal terminated read. */
454	result = 0;
455	else if (result == -ETIMEDOUT)
456	debug("%s: I2C_READ: time out\n", __func__);
457	else
458	debug("%s: I2C_READ: read not terminated with NACK\n",
459	__func__);
460	break;
461
462	default:
463	debug("%s: bad call\n", __func__);
464	result = -EINVAL;
465	break;
466	}
467
468	bailout:
469	return result;
470	}
471
472	static int nx_i2c_read(struct udevice *dev, uchar chip_addr, uint addr,
473	uint alen, uchar *buffer, uint len, uint seq)
474	{
475	struct nx_i2c_bus *i2c;
476	uchar xaddr[4];
477	int ret;
478
479	i2c = dev_get_priv(dev);
480	if (!i2c)
481	return -EFAULT;
482
483	if (alen > 4) {
484	debug("I2C read: addr len %d not supported\n", alen);
485	return -EADDRNOTAVAIL;
486	}
487
488	if (alen > 0)
489	xaddr[0] = (addr >> 24) & 0xFF;
490
491	if (alen > 0) {
492	xaddr[0] = (addr >> 24) & 0xFF;
493	xaddr[1] = (addr >> 16) & 0xFF;
494	xaddr[2] = (addr >> 8) & 0xFF;
495	xaddr[3] = addr & 0xFF;
496	}
497
498	ret = i2c_transfer(i2c->regs, I2C_READ, chip_addr << 1,
499	&xaddr[4 - alen], alen, buffer, len, seq);
500
501	if (ret) {
502	debug("I2C read failed %d\n", ret);
503	return -EIO;
504	}
505
506	return 0;
507	}
508
509	static int nx_i2c_write(struct udevice *dev, uchar chip_addr, uint addr,
510	uint alen, uchar *buffer, uint len, uint seq)
511	{
512	struct nx_i2c_bus *i2c;
513	uchar xaddr[4];
514	int ret;
515
516	i2c = dev_get_priv(dev);
517	if (!i2c)
518	return -EFAULT;
519
520	if (alen > 4) {
521	debug("I2C write: addr len %d not supported\n", alen);
522	return -EINVAL;
523	}
524
525	if (alen > 0) {
526	xaddr[0] = (addr >> 24) & 0xFF;
527	xaddr[1] = (addr >> 16) & 0xFF;
528	xaddr[2] = (addr >> 8) & 0xFF;
529	xaddr[3] = addr & 0xFF;
530	}
531
532	ret = i2c_transfer(i2c->regs, I2C_WRITE, chip_addr << 1,
533	&xaddr[4 - alen], alen, buffer, len, seq);
534	if (ret) {
535	debug("I2C write failed %d\n", ret);
536	return -EIO;
537	}
538
539	return 0;
540	}
541
542	static int nx_i2c_xfer(struct udevice dev, struct i2c_msg msg, int nmsgs)
543	{
544	struct nx_i2c_bus *bus = dev_get_priv(dev);
545	struct nx_i2c_regs *i2c = bus->regs;
546	int ret;
547	int i;
548
549	/* The power loss by the clock, only during on/off. */
550	ret = i2c_set_clk(bus, 1);
551
552	if (!ret)
553	/* Bus State(Busy) check */
554	ret = i2c_is_busy(i2c);
555	if (!ret) {
556	for (i = 0; i < nmsgs; msg++, i++) {
557	if (msg->flags & I2C_M_RD) {
558	ret = nx_i2c_read(dev, msg->addr, 0, 0,
559	msg->buf, msg->len, i);
560	} else {
561	ret = nx_i2c_write(dev, msg->addr, 0, 0,
562	msg->buf, msg->len, i);
563	}
564
565	if (ret) {
566	debug("i2c_xfer: error sending\n");
567	ret = -EREMOTEIO;
568	}
569	}
570
571	i2c_send_stop(bus);
572	if (i2c_set_clk(bus, 0))
573	ret = -EINVAL;
574	}
575
576	return ret;
577	};
578
579	static int nx_i2c_probe_chip(struct udevice *dev, u32 chip_addr,
580	u32 chip_flags)
581	{
582	int ret;
583	struct nx_i2c_bus *bus = dev_get_priv(dev);
584
585	ret = i2c_set_clk(bus, 1);
586
587	if (!ret) {
588	/*
589	* Send Chip Address only
590	* --> I2C transfer with data length and address length = 0.
591	* If there is a Slave, i2c_transfer() returns 0 (acknowledge
592	* transfer).
593	* I2C_WRITE must be used in order Master Transmit Mode is
594	* selected. Otherwise (in Master Receive Mode, I2C_READ)
595	* sending the stop condition below is not working (SDA does
596	* not transit to High).
597	*/
598	ret = i2c_transfer(bus->regs, I2C_WRITE, (uchar)chip_addr << 1,
599	NULL, 0, NULL, 0, 0);
600
601	i2c_send_stop(bus);
602	if (i2c_set_clk(bus, 0))
603	ret = -EINVAL;
604	}
605
606	return ret;
607	}
608
609	static const struct dm_i2c_ops nx_i2c_ops = {
610	.xfer = nx_i2c_xfer,
611	.probe_chip = nx_i2c_probe_chip,
612	.set_bus_speed = nx_i2c_set_bus_speed,
613	};
614
615	static const struct udevice_id nx_i2c_ids[] = {
616	{ .compatible = "nexell,s5pxx18-i2c" },
617	{ }
618	};
619
620	U_BOOT_DRIVER(i2c_nexell) = {
621	.name = "i2c_nexell",
622	.id = UCLASS_I2C,
623	.of_match = nx_i2c_ids,
624	.probe = nx_i2c_probe,
41575d8e	625	.priv_auto = sizeof(struct nx_i2c_bus),
c25e9e04 SB	626	.ops = &nx_i2c_ops,
c25e9e04 SB	627	};