[u-boot.git] / board / theadorable / theadorable.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015-2019 Stefan Roese <[email protected]>
 */

#include <common.h>
#include <command.h>
#include <console.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#if !defined(CONFIG_SPL_BUILD)
#include <bootcount.h>
#endif
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <linux/delay.h>
#include <linux/mbus.h>
#ifdef CONFIG_NET
#include <netdev.h>
#endif
#include <u-boot/crc.h>
#include "theadorable.h"

#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"

DECLARE_GLOBAL_DATA_PTR;

#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)

#define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
#define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
#define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))

#define THEADORABLE_GPP_OUT_VAL_LOW	0x2c0c983f
#define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
#define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000

#define GPIO_USB0_PWR_ON		18
#define GPIO_USB1_PWR_ON		19

#define PEX_SWITCH_NOT_FOUNT_LIMIT	3

#define STM_I2C_BUS	1
#define STM_I2C_ADDR	0x27
#define REBOOT_DELAY	1000		/* reboot-delay in ms */
#define ABORT_TIMEOUT	3000		/* 3 seconds reboot abort timeout */

/* DDR3 static configuration */
static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
	{0x00001404, 0x30000800},	/* Dunit Control Low Register */
	{0x00001408, 0x44149887},	/* DDR SDRAM Timing (Low) Register */
	{0x0000140C, 0x38d93fc7},	/* DDR SDRAM Timing (High) Register */
	{0x00001410, 0x1b100001},	/* DDR SDRAM Address Control Register */
	{0x00001424, 0x0000f3ff},	/* Dunit Control High Register */
	{0x00001428, 0x000f8830},	/* ODT Timing (Low) Register */
	{0x0000142C, 0x014c50f4},	/* DDR3 Timing Register */
	{0x0000147C, 0x0000c671},	/* ODT Timing (High) Register */

	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
	{0x000014A0, 0x00000001},	/* DRAM FIFO Control Register */
	{0x000014A8, 0x00000101},	/* AXI Control Register */

	/*
	 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
	 * training sequence
	 */
	{0x000200e8, 0x3fff0e01},
	{0x00020184, 0x3fffffe0},	/* Close fast path Window to - 2G */

	{0x0001504, 0x7fffffe1},	/* CS0 Size */
	{0x000150C, 0x00000000},	/* CS1 Size */
	{0x0001514, 0x00000000},	/* CS2 Size */
	{0x000151C, 0x00000000},	/* CS3 Size */

	{0x00020220, 0x00000007},	/* Reserved */

	{0x00001538, 0x00000009},	/* Read Data Sample Delays Register */
	{0x0000153C, 0x00000009},	/* Read Data Ready Delay Register */

	{0x000015D0, 0x00000650},	/* MR0 */
	{0x000015D4, 0x00000044},	/* MR1 */
	{0x000015D8, 0x00000010},	/* MR2 */
	{0x000015DC, 0x00000000},	/* MR3 */
	{0x000015E0, 0x00000001},
	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
	{0x000015EC, 0xf800a225},	/* DDR PHY */

	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
	{0x000014C0, 0x192424c9},	/* DRAM addr and Ctrl Driving Strenght*/
	{0x000014C4, 0x0aaa24c9},	/* DRAM Data and DQS Driving Strenght */

	{0x0, 0x0}
};

static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
	{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable,  NULL},
};

extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];

/*
 * Lane0 - PCIE0.0 X1 (to WIFI Module)
 * Lane5 - SATA0
 * Lane6 - SATA1
 * Lane7 - SGMII0 (to Ethernet Phy)
 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
 * all other lanes are disabled
 */
MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
	{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
	  { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
	    PEX_BUS_DISABLED },
	  0x0060, serdes_change_m_phy
	},
};

/*
 * Define a board-specific detection pulse-width array for the SerDes PCIe
 * interfaces. If not defined in the board code, the default of currently 2
 * is used. Values from 0...3 are possible (2 bits).
 */
u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };

MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
{
	/* Only one mode supported for this board */
	return &board_ddr_modes[0];
}

MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
	return &theadorable_serdes_cfg[0];
}

u8 board_sat_r_get(u8 dev_num, u8 reg)
{
	/* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
	return 0xe;	/* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
}

int board_early_init_f(void)
{
	/* Configure MPP */
	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
	writel(0x03300000, MVEBU_MPP_BASE + 0x04);
	writel(0x00000033, MVEBU_MPP_BASE + 0x08);
	writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
	writel(0x11110000, MVEBU_MPP_BASE + 0x10);
	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
	writel(0x00000000, MVEBU_MPP_BASE + 0x18);
	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
	writel(0x00000000, MVEBU_MPP_BASE + 0x20);

	/* Configure GPIO */
	writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
	writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
	writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
	writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
	writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
	writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);

	return 0;
}

int board_init(void)
{
	int ret;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	/*
	 * Map SPI devices via MBUS so that they can be accessed via
	 * the SPI direct access mode
	 */
	mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);

	/*
	 * Set RX Channel Control 0 Register:
	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
	 * to 3 (1/1) results in a more stable USB connection.
	 */
	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);

	/* Toggle USB power */
	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
	if (ret < 0)
		return ret;
	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
	if (ret < 0)
		return ret;
	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
	mdelay(1);
	gpio_set_value(GPIO_USB0_PWR_ON, 1);
	gpio_set_value(GPIO_USB1_PWR_ON, 1);

	return 0;
}

int checkboard(void)
{
	board_fpga_add();

	return 0;
}

#ifdef CONFIG_NET
int board_eth_init(struct bd_info *bis)
{
	cpu_eth_init(bis); /* Built in controller(s) come first */
	return pci_eth_init(bis);
}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
	pci_dev_t bdf;
	ulong bootcount;

	/*
	 * Check if the PEX switch is detected (somtimes its not available
	 * on the PCIe bus). In this case, try to recover by issuing a
	 * soft-reset or even a power-cycle, depending on the bootcounter
	 * value.
	 */
	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
	if (bdf == -1) {
		unsigned long start_time = get_timer(0);
		u8 i2c_buf[8];
		int ret;

		/* PEX switch not found! */
		bootcount = bootcount_load();
		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
		       bootcount);

		/*
		 * The user can exit this boot-loop in the error case by
		 * hitting Ctrl-C. So wait some time for this key here.
		 */
		printf("Continue booting with Ctrl-C, otherwise rebooting\n");
		do {
			/* Handle control-c and timeouts */
			if (ctrlc()) {
				printf("PEX error boot-loop aborted!\n");
				return 0;
			}
		} while (get_timer(start_time) < ABORT_TIMEOUT);


		/*
		 * At this stage the bootcounter has not been incremented
		 * yet. We need to do this manually here to get an actually
		 * working bootcounter in this error case.
		 */
		bootcount_inc();

		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
			printf("Issuing power-switch via uC!\n");

			printf("Issuing power-switch via uC!\n");
			i2c_set_bus_num(STM_I2C_BUS);
			i2c_buf[0] = STM_I2C_ADDR << 1;
			i2c_buf[1] = 0xc5;	/* cmd */
			i2c_buf[2] = 0x01;	/* enable */
			/* Delay before reboot */
			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
			/* Delay before shutdown */
			i2c_buf[5] = 0x00;
			i2c_buf[6] = 0x00;
			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);

			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
			if (ret) {
				printf("I2C write error (ret=%d)\n", ret);
				printf("Issuing soft-reset...\n");
				/* default handling: SOFT reset */
				do_reset(NULL, 0, 0, NULL);
			}

			/* Wait for power-cycle to occur... */
			printf("Waiting for power-cycle via uC...\n");
			while (1)
				;
		} else {
			printf("Issuing soft-reset...\n");
			/* default handling: SOFT reset */
			do_reset(NULL, 0, 0, NULL);
		}
	}

	return 0;
}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	pci_dev_t bdf;
	u16 ven_id, dev_id;

	if (argc != 3)
		return cmd_usage(cmdtp);

	ven_id = simple_strtoul(argv[1], NULL, 16);
	dev_id = simple_strtoul(argv[2], NULL, 16);

	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
	       ven_id, dev_id);

	/*
	 * Check if the PCIe device is detected (somtimes its not available
	 * on the PCIe bus)
	 */
	bdf = pci_find_device(ven_id, dev_id, 0);
	if (bdf == -1) {
		/* PCIe device not found! */
		printf("Failed to find PCIe device\n");
	} else {
		/* PCIe device found! */
		printf("PCIe device found, resetting board...\n");

		/* default handling: SOFT reset */
		do_reset(NULL, 0, 0, NULL);
	}

	return 0;
}

U_BOOT_CMD(
	pcie,   3,   0,     do_pcie_test,
	"Test for presence of a PCIe device",
	"<VendorID> <DeviceID>"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b20c38a9	2	/*
54055ff7	3	* Copyright (C) 2015-2019 Stefan Roese <[email protected]>
b20c38a9 SR	4	*/
	5
	6	#include <common.h>
09140113	7	#include <command.h>
54055ff7	8	#include <console.h>
169a8550	9	#include <i2c.h>
5255932f	10	#include <init.h>
90526e9f	11	#include <net.h>
169a8550	12	#include <pci.h>
54055ff7 SR	13	#if !defined(CONFIG_SPL_BUILD)
	14	#include <bootcount.h>
	15	#endif
401d1c4f	16	#include <asm/global_data.h>
ced0d849	17	#include <asm/gpio.h>
b20c38a9 SR	18	#include <asm/io.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/arch/soc.h>
c05ed00a	21	#include <linux/delay.h>
aea02abe	22	#include <linux/mbus.h>
b20c38a9 SR	23	#ifdef CONFIG_NET
	24	#include <netdev.h>
	25	#endif
c3a4d1c3	26	#include <u-boot/crc.h>
aea02abe	27	#include "theadorable.h"
b20c38a9 SR	28
	29	#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
	30	#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
ced0d849 SR	34	#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
	35	#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
	36	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
	37
b20c38a9 SR	38	#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
	39	#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
	40	#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
	41
	42	#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
	43	#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
	44	#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
	45
ced0d849 SR	46	#define GPIO_USB0_PWR_ON 18
	47	#define GPIO_USB1_PWR_ON 19
	48
169a8550 SR	49	#define PEX_SWITCH_NOT_FOUNT_LIMIT 3
	50
	51	#define STM_I2C_BUS 1
	52	#define STM_I2C_ADDR 0x27
	53	#define REBOOT_DELAY 1000 /* reboot-delay in ms */
54055ff7	54	#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
169a8550	55
b20c38a9 SR	56	/* DDR3 static configuration */
	57	static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
	58	{0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
	59	{0x00001404, 0x30000800}, /* Dunit Control Low Register */
	60	{0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
	61	{0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
	62	{0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
	63	{0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
	64	{0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
	65	{0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
	66	{0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
	67
	68	{0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
	69	{0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
	70	{0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
	71	{0x000014A8, 0x00000101}, /* AXI Control Register */
	72
	73	/*
	74	* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
	75	* training sequence
	76	*/
	77	{0x000200e8, 0x3fff0e01},
	78	{0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
	79
	80	{0x0001504, 0x7fffffe1}, /* CS0 Size */
	81	{0x000150C, 0x00000000}, /* CS1 Size */
	82	{0x0001514, 0x00000000}, /* CS2 Size */
	83	{0x000151C, 0x00000000}, /* CS3 Size */
	84
	85	{0x00020220, 0x00000007}, /* Reserved */
	86
	87	{0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
	88	{0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
	89
	90	{0x000015D0, 0x00000650}, /* MR0 */
	91	{0x000015D4, 0x00000044}, /* MR1 */
	92	{0x000015D8, 0x00000010}, /* MR2 */
	93	{0x000015DC, 0x00000000}, /* MR3 */
	94	{0x000015E0, 0x00000001},
	95	{0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
	96	{0x000015EC, 0xf800a225}, /* DDR PHY */
	97
	98	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
	99	{0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
	100	{0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
	101
	102	{0x0, 0x0}
	103	};
	104
	105	static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
	106	{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
	107	};
	108
	109	extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
	110
	111	/*
	112	* Lane0 - PCIE0.0 X1 (to WIFI Module)
	113	* Lane5 - SATA0
	114	* Lane6 - SATA1
	115	* Lane7 - SGMII0 (to Ethernet Phy)
	116	* Lane8-11 - PCIE2.0 X4 (to PEX Switch)
	117	* all other lanes are disabled
	118	*/
	119	MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
120	{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
121	{ PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
122	PEX_BUS_DISABLED },
123	0x0060, serdes_change_m_phy
124	},
125	};
126
1304f4bb SR	127	/*
	128	* Define a board-specific detection pulse-width array for the SerDes PCIe
	129	* interfaces. If not defined in the board code, the default of currently 2
	130	* is used. Values from 0...3 are possible (2 bits).
	131	*/
	132	u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
	133
b20c38a9 SR	134	MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
	135	{
	136	/* Only one mode supported for this board */
	137	return &board_ddr_modes[0];
	138	}
	139
0a590243	140	MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
b20c38a9 SR	141	{
	142	return &theadorable_serdes_cfg[0];
	143	}
	144
9ed00b07 SR	145	u8 board_sat_r_get(u8 dev_num, u8 reg)
9ed00b07 SR	146	{
0a590243 SR	147	/* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
0a590243 SR	148	return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
9ed00b07 SR	149	}
9ed00b07 SR	150
b20c38a9 SR	151	int board_early_init_f(void)
	152	{
	153	/* Configure MPP */
	154	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
	155	writel(0x03300000, MVEBU_MPP_BASE + 0x04);
	156	writel(0x00000033, MVEBU_MPP_BASE + 0x08);
	157	writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
	158	writel(0x11110000, MVEBU_MPP_BASE + 0x10);
	159	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
	160	writel(0x00000000, MVEBU_MPP_BASE + 0x18);
	161	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
	162	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
	163
	164	/* Configure GPIO */
	165	writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
	166	writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
	167	writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
	168	writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
	169	writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
	170	writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
	171
	172	return 0;
	173	}
	174
	175	int board_init(void)
	176	{
ced0d849 SR	177	int ret;
ced0d849 SR	178
b20c38a9 SR	179	/* adress of boot parameters */
	180	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
	181
aea02abe SR	182	/*
	183	* Map SPI devices via MBUS so that they can be accessed via
	184	* the SPI direct access mode
	185	*/
	186	mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
	187	CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
	188	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
	189	CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
	190
ced0d849 SR	191	/*
	192	* Set RX Channel Control 0 Register:
	193	* Tests have shown, that setting the LPF_COEF from 0 (1/8)
	194	* to 3 (1/1) results in a more stable USB connection.
	195	*/
	196	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
	197	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
	198	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
	199
	200	/* Toggle USB power */
	201	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
	202	if (ret < 0)
	203	return ret;
	204	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
	205	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
	206	if (ret < 0)
	207	return ret;
	208	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
	209	mdelay(1);
	210	gpio_set_value(GPIO_USB0_PWR_ON, 1);
	211	gpio_set_value(GPIO_USB1_PWR_ON, 1);
	212
b20c38a9 SR	213	return 0;
	214	}
	215
	216	int checkboard(void)
	217	{
aea02abe SR	218	board_fpga_add();
aea02abe SR	219
b20c38a9 SR	220	return 0;
	221	}
	222
	223	#ifdef CONFIG_NET
b75d8dc5	224	int board_eth_init(struct bd_info *bis)
b20c38a9 SR	225	{
	226	cpu_eth_init(bis); /* Built in controller(s) come first */
	227	return pci_eth_init(bis);
	228	}
	229	#endif
	230
54055ff7	231	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
169a8550 SR	232	int board_late_init(void)
	233	{
	234	pci_dev_t bdf;
	235	ulong bootcount;
	236
	237	/*
	238	* Check if the PEX switch is detected (somtimes its not available
	239	* on the PCIe bus). In this case, try to recover by issuing a
	240	* soft-reset or even a power-cycle, depending on the bootcounter
	241	* value.
	242	*/
	243	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
	244	if (bdf == -1) {
54055ff7	245	unsigned long start_time = get_timer(0);
169a8550 SR	246	u8 i2c_buf[8];
	247	int ret;
	248
	249	/* PEX switch not found! */
	250	bootcount = bootcount_load();
	251	printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
	252	bootcount);
54055ff7 SR	253
	254	/*
	255	* The user can exit this boot-loop in the error case by
	256	* hitting Ctrl-C. So wait some time for this key here.
	257	*/
	258	printf("Continue booting with Ctrl-C, otherwise rebooting\n");
	259	do {
	260	/* Handle control-c and timeouts */
	261	if (ctrlc()) {
	262	printf("PEX error boot-loop aborted!\n");
	263	return 0;
	264	}
	265	} while (get_timer(start_time) < ABORT_TIMEOUT);
	266
	267
	268	/*
	269	* At this stage the bootcounter has not been incremented
	270	* yet. We need to do this manually here to get an actually
	271	* working bootcounter in this error case.
	272	*/
	273	bootcount_inc();
	274
169a8550 SR	275	if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
	276	printf("Issuing power-switch via uC!\n");
	277
	278	printf("Issuing power-switch via uC!\n");
	279	i2c_set_bus_num(STM_I2C_BUS);
	280	i2c_buf[0] = STM_I2C_ADDR << 1;
	281	i2c_buf[1] = 0xc5; /* cmd */
	282	i2c_buf[2] = 0x01; /* enable */
	283	/* Delay before reboot */
	284	i2c_buf[3] = REBOOT_DELAY & 0x00ff;
	285	i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
	286	/* Delay before shutdown */
	287	i2c_buf[5] = 0x00;
	288	i2c_buf[6] = 0x00;
	289	i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
	290
	291	ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
	292	if (ret) {
	293	printf("I2C write error (ret=%d)\n", ret);
	294	printf("Issuing soft-reset...\n");
	295	/* default handling: SOFT reset */
	296	do_reset(NULL, 0, 0, NULL);
	297	}
	298
	299	/* Wait for power-cycle to occur... */
	300	printf("Waiting for power-cycle via uC...\n");
	301	while (1)
	302	;
	303	} else {
	304	printf("Issuing soft-reset...\n");
	305	/* default handling: SOFT reset */
	306	do_reset(NULL, 0, 0, NULL);
	307	}
	308	}
	309
	310	return 0;
	311	}
	312	#endif
1ec2a80b SR	313
1ec2a80b SR	314	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
09140113	315	int do_pcie_test(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
1ec2a80b SR	316	{
	317	pci_dev_t bdf;
	318	u16 ven_id, dev_id;
	319
	320	if (argc != 3)
	321	return cmd_usage(cmdtp);
	322
	323	ven_id = simple_strtoul(argv[1], NULL, 16);
	324	dev_id = simple_strtoul(argv[2], NULL, 16);
	325
	326	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
	327	ven_id, dev_id);
	328
	329	/*
	330	* Check if the PCIe device is detected (somtimes its not available
	331	* on the PCIe bus)
	332	*/
	333	bdf = pci_find_device(ven_id, dev_id, 0);
	334	if (bdf == -1) {
	335	/* PCIe device not found! */
	336	printf("Failed to find PCIe device\n");
	337	} else {
	338	/* PCIe device found! */
	339	printf("PCIe device found, resetting board...\n");
	340
	341	/* default handling: SOFT reset */
	342	do_reset(NULL, 0, 0, NULL);
	343	}
	344
	345	return 0;
	346	}
	347
	348	U_BOOT_CMD(
	349	pcie, 3, 0, do_pcie_test,
	350	"Test for presence of a PCIe device",
	351	"<VendorID> <DeviceID>"
	352	);
	353	#endif