[u-boot.git] / board / menlo / m53menlo / m53menlo.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Menlosystems M53Menlo board
 *
 * Copyright (C) 2012-2017 Marek Vasut <[email protected]>
 * Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <init.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
#include <asm/spl.h>
#include <env.h>
#include <fdt_support.h>
#include <fsl_esdhc_imx.h>
#include <gzip.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <splash.h>
#include <usb/ehci-ci.h>
#include <video_console.h>

DECLARE_GLOBAL_DATA_PTR;

static u32 mx53_dram_size[2];

ulong board_get_usable_ram_top(ulong total_size)
{
	/*
	 * WARNING: We must override get_effective_memsize() function here
	 * to report only the size of the first DRAM bank. This is to make
	 * U-Boot relocator place U-Boot into valid memory, that is, at the
	 * end of the first DRAM bank. If we did not override this function
	 * like so, U-Boot would be placed at the address of the first DRAM
	 * bank + total DRAM size - sizeof(uboot), which in the setup where
	 * each DRAM bank contains 512MiB of DRAM would result in placing
	 * U-Boot into invalid memory area close to the end of the first
	 * DRAM bank.
	 */
	return PHYS_SDRAM_2 + mx53_dram_size[1];
}

int dram_init(void)
{
	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);

	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = mx53_dram_size[0];

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = mx53_dram_size[1];

	return 0;
}

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
		MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		/* MDIO pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),

		/* FEC 0 pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),

		/* FEC 1 pads */
		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg = {
	MMC_SDHC1_BASE_ADDR,
};

int board_mmc_getcd(struct mmc *mmc)
{
	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	gpio_direction_input(IMX_GPIO_NR(1, 1));

	return !gpio_get_value(IMX_GPIO_NR(1, 1));
}

#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
				 PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
				 PAD_CTL_DSE_HIGH)

int board_mmc_init(struct bd_info *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	};

	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));

	return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
#endif

static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	int ret;

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
	if (ret)
		puts("IPU:   Failed to configure LDB clock\n");

	/* Configure CCM_CSCMR2 */
	clrsetbits_le32(&mxc_ccm->cscmr2,
			(0x7 << 26) | BIT(10) | BIT(8),
			(0x5 << 26) | BIT(10) | BIT(8));

	/* Configure LDB_CTRL */
	writel(0x201, 0x53fa8008);
}

static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 63);
}

static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 233);

	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
}

static const char *lvds_compat_string;

static int detect_lvds(struct display_info_t const *dev)
{
	u8 touchid[23];
	u8 *touchptr = &touchid[0];
	int ret;

	ret = i2c_set_bus_num(0);
	if (ret)
		return 0;

	/* Touchscreen is at address 0x38, ID register is 0xbb. */
	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
	if (ret)
		return 0;

	/* EP0430 prefixes the response with 0xbb, skip it. */
	if (*touchptr == 0xbb)
		touchptr++;

	/* Skip the 'EP' prefix. */
	touchptr += 2;

	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	if (ret)
		lvds_compat_string = dev->mode.name;

	return ret;
}

void board_preboot_os(void)
{
	/* Power off the LCD to prevent awful color flicker */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
}

int ft_board_setup(void *blob, struct bd_info *bd)
{
	if (lvds_compat_string)
		do_fixup_by_path_string(blob, "/panel", "compatible",
					lvds_compat_string);

	return 0;
}

struct display_info_t const displays[] = {
	{
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0430g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0430g0dh6",
			.refresh	= 60,
			.xres		= 480,
			.yres		= 272,
			.pixclock	= 111111, /* picosecond (9 MHz) */
			.left_margin	= 2,
			.right_margin	= 2,
			.upper_margin	= 2,
			.lower_margin	= 2,
			.hsync_len	= 41,
			.vsync_len	= 10,
			.sync		= 0x40000000,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}, {
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0700g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0700g0dh6",
			.refresh	= 60,
			.xres		= 800,
			.yres		= 480,
			.pixclock	= 30048, /* picosecond (33.28 MHz) */
			.left_margin	= 40,
			.right_margin	= 88,
			.upper_margin	= 10,
			.lower_margin	= 33,
			.hsync_len	= 128,
			.vsync_len	= 2,
			.sync		= FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}
};

size_t display_count = ARRAY_SIZE(displays);

#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location default_splash_locations[] = {
	{
		.name		= "mmc_fs",
		.storage	= SPLASH_STORAGE_MMC,
		.flags		= SPLASH_STORAGE_FS,
		.devpart	= "0:1",
	},
};

int splash_screen_prepare(void)
{
	return splash_source_load(default_splash_locations,
				  ARRAY_SIZE(default_splash_locations));
}
#endif

int board_late_init(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
	struct udevice *dev;
	int xpos, ypos, ret;
	char *s;
	void *dst;
	ulong addr, len;

	splash_get_pos(&xpos, &ypos);

	s = env_get("splashimage");
	if (!s)
		return 0;

	addr = simple_strtoul(s, NULL, 16);
	dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
	if (!dst)
		return -ENOMEM;

	ret = splash_screen_prepare();
	if (ret < 0)
		goto splasherr;

	len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
	ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
		     (uchar *)addr, &len);
	if (ret) {
		printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
		goto splasherr;
	}

	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
	if (ret)
		goto splasherr;

	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
	if (ret)
		goto splasherr;

	return 0;

splasherr:
	free(dst);
#endif
	return 0;
}

#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c_pads[] = {
		/* I2C1 */
		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
		/* I2C2 */
		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}

static void setup_iomux_video(void)
{
	static const iomux_v3_cfg_t lcd_pads[] = {
		MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
		MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
		MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
		MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
		MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
	};

	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}

static void setup_iomux_nand(void)
{
	static const iomux_v3_cfg_t nand_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
	};

	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}

static void m53_set_clock(void)
{
	int ret;
	const u32 ref_clk = MXC_HCLK;
	const u32 dramclk = 400;
	u32 cpuclk;

	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
	gpio_direction_input(IMX_GPIO_NR(4, 0));

	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;

	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	if (ret)
		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);

	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	if (ret) {
		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
		       dramclk);
	}

	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	if (ret)
		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
}

static void m53_set_nand(void)
{
	u32 i;

	/* NAND flash is muxed on ATA pins */
	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);

	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	for (i = 0x4; i < 0x94; i += 0x18) {
		clrbits_le32(WEIM_BASE_ADDR + i,
			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	}

	mxc_set_clock(0, 33, MXC_NFC_CLK);
	enable_nfc_clk(1);
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
	setup_iomux_i2c();
	setup_iomux_nand();
	setup_iomux_video();

	m53_set_clock();

	mxc_set_sata_internal_clock();

	/* NAND clock @ 33MHz */
	m53_set_nand();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: Menlosystems M53Menlo\n");

	return 0;
}

/*
 * NAND SPL
 */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
	setup_iomux_nand();
	m53_set_clock();
	m53_set_nand();
}

u32 spl_boot_device(void)
{
	return BOOT_DEVICE_NAND;
}
#endif
Commit	Line	Data
39cb4f3c MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Menlosystems M53Menlo board
	4	*
	5	* Copyright (C) 2012-2017 Marek Vasut <[email protected]>
	6	* Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
	7	*/
	8
	9	#include <common.h>
f0be8ff4	10	#include <dm.h>
67c4e9f8	11	#include <init.h>
336d4615	12	#include <malloc.h>
401d1c4f	13	#include <asm/global_data.h>
39cb4f3c MV	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/sys_proto.h>
	17	#include <asm/arch/crm_regs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/iomux-mx53.h>
	20	#include <asm/mach-imx/mx5_video.h>
	21	#include <asm/mach-imx/video.h>
	22	#include <asm/gpio.h>
	23	#include <asm/spl.h>
7b51b576	24	#include <env.h>
39cb4f3c	25	#include <fdt_support.h>
e37ac717	26	#include <fsl_esdhc_imx.h>
0c670fc1	27	#include <gzip.h>
39cb4f3c MV	28	#include <i2c.h>
39cb4f3c MV	29	#include <ipu_pixfmt.h>
cd93d625	30	#include <linux/bitops.h>
39cb4f3c MV	31	#include <linux/errno.h>
	32	#include <linux/fb.h>
	33	#include <mmc.h>
	34	#include <netdev.h>
	35	#include <spl.h>
	36	#include <splash.h>
	37	#include <usb/ehci-ci.h>
f0be8ff4	38	#include <video_console.h>
39cb4f3c MV	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	static u32 mx53_dram_size[2];
	43
	44	ulong board_get_usable_ram_top(ulong total_size)
	45	{
	46	/*
	47	* WARNING: We must override get_effective_memsize() function here
	48	* to report only the size of the first DRAM bank. This is to make
	49	* U-Boot relocator place U-Boot into valid memory, that is, at the
	50	* end of the first DRAM bank. If we did not override this function
	51	* like so, U-Boot would be placed at the address of the first DRAM
	52	* bank + total DRAM size - sizeof(uboot), which in the setup where
	53	* each DRAM bank contains 512MiB of DRAM would result in placing
	54	* U-Boot into invalid memory area close to the end of the first
	55	* DRAM bank.
	56	*/
	57	return PHYS_SDRAM_2 + mx53_dram_size[1];
	58	}
	59
	60	int dram_init(void)
	61	{
	62	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	63	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
	64
	65	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
	66
	67	return 0;
	68	}
	69
	70	int dram_init_banksize(void)
	71	{
	72	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	73	gd->bd->bi_dram[0].size = mx53_dram_size[0];
	74
	75	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	76	gd->bd->bi_dram[1].size = mx53_dram_size[1];
	77
	78	return 0;
	79	}
	80
	81	static void setup_iomux_uart(void)
	82	{
	83	static const iomux_v3_cfg_t uart_pads[] = {
	84	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
	85	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
	86	};
	87
	88	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	89	}
	90
39cb4f3c MV	91	static void setup_iomux_fec(void)
	92	{
	93	static const iomux_v3_cfg_t fec_pads[] = {
	94	/* MDIO pads */
	95	NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS \|
	96	PAD_CTL_DSE_HIGH \| PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE),
	97	NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
	98
	99	/* FEC 0 pads */
	100	NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
	101	PAD_CTL_HYS \| PAD_CTL_PKE),
	102	NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
	103	PAD_CTL_HYS \| PAD_CTL_PKE),
	104	NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
	105	PAD_CTL_HYS \| PAD_CTL_PKE),
	106	NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
	107	NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
	108	PAD_CTL_HYS \| PAD_CTL_PKE),
	109	NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
	110	PAD_CTL_HYS \| PAD_CTL_PKE),
	111	NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
	112	NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
	113
	114	/* FEC 1 pads */
	115	NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
	116	PAD_CTL_HYS \| PAD_CTL_PKE),
	117	NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
	118	PAD_CTL_HYS \| PAD_CTL_PKE),
	119	NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
	120	PAD_CTL_HYS \| PAD_CTL_PKE),
	121	NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
	122	PAD_CTL_HYS \| PAD_CTL_PKE),
	123	NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
	124	PAD_CTL_HYS \| PAD_CTL_PKE),
	125	NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
	126	NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
	127	PAD_CTL_HYS \| PAD_CTL_PKE),
	128	NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	129	};
	130
	131	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	132	}
	133
e37ac717	134	#ifdef CONFIG_FSL_ESDHC_IMX
39cb4f3c MV	135	struct fsl_esdhc_cfg esdhc_cfg = {
	136	MMC_SDHC1_BASE_ADDR,
	137	};
	138
	139	int board_mmc_getcd(struct mmc *mmc)
	140	{
	141	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	142	gpio_direction_input(IMX_GPIO_NR(1, 1));
	143
	144	return !gpio_get_value(IMX_GPIO_NR(1, 1));
	145	}
	146
	147	#define SD_CMD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	148	PAD_CTL_PUS_100K_UP)
	149	#define SD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	150	PAD_CTL_DSE_HIGH)
	151
b75d8dc5	152	int board_mmc_init(struct bd_info *bis)
39cb4f3c MV	153	{
	154	static const iomux_v3_cfg_t sd1_pads[] = {
	155	NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
	156	NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
	157	NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
	158	NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
	159	NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
	160	NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	161	};
	162
	163	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	164
	165	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
	166
	167	return fsl_esdhc_initialize(bis, &esdhc_cfg);
	168	}
	169	#endif
	170
39cb4f3c MV	171	static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
	172	{
	173	static struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
	174	int ret;
	175
	176	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	177	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	178
	179	/*
	180	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	181	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	182	*/
	183	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
	184	if (ret)
	185	puts("IPU: Failed to configure LDB clock\n");
	186
	187	/* Configure CCM_CSCMR2 */
	188	clrsetbits_le32(&mxc_ccm->cscmr2,
	189	(0x7 << 26) \| BIT(10) \| BIT(8),
	190	(0x5 << 26) \| BIT(10) \| BIT(8));
	191
	192	/* Configure LDB_CTRL */
	193	writel(0x201, 0x53fa8008);
	194	}
	195
	196	static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
	197	{
9b352ae1 MV	198	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	199
39cb4f3c MV	200	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	201	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	202
	203	/*
	204	* Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	205	* 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	206	*/
	207	enable_lvds_clock(dev, 63);
	208	}
	209
	210	static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
	211	{
9b352ae1 MV	212	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	213
39cb4f3c MV	214	/*
	215	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	216	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	217	*/
	218	enable_lvds_clock(dev, 233);
	219
	220	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	221	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	222	}
	223
	224	static const char *lvds_compat_string;
	225
	226	static int detect_lvds(struct display_info_t const *dev)
	227	{
	228	u8 touchid[23];
	229	u8 *touchptr = &touchid[0];
	230	int ret;
	231
	232	ret = i2c_set_bus_num(0);
	233	if (ret)
	234	return 0;
	235
	236	/* Touchscreen is at address 0x38, ID register is 0xbb. */
	237	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
	238	if (ret)
	239	return 0;
	240
	241	/* EP0430 prefixes the response with 0xbb, skip it. */
	242	if (*touchptr == 0xbb)
	243	touchptr++;
	244
	245	/* Skip the 'EP' prefix. */
	246	touchptr += 2;
	247
	248	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	249	if (ret)
	250	lvds_compat_string = dev->mode.name;
	251
	252	return ret;
	253	}
	254
	255	void board_preboot_os(void)
	256	{
	257	/* Power off the LCD to prevent awful color flicker */
	258	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
	259	}
	260
b75d8dc5	261	int ft_board_setup(void blob, struct bd_info bd)
39cb4f3c MV	262	{
	263	if (lvds_compat_string)
	264	do_fixup_by_path_string(blob, "/panel", "compatible",
	265	lvds_compat_string);
	266
	267	return 0;
	268	}
	269
	270	struct display_info_t const displays[] = {
	271	{
	272	.bus = 0,
	273	.addr = 0,
	274	.detect = detect_lvds,
	275	.enable = enable_lvds_etm0430g0dh6,
	276	.pixfmt = IPU_PIX_FMT_RGB666,
	277	.mode = {
	278	.name = "edt,etm0430g0dh6",
	279	.refresh = 60,
	280	.xres = 480,
	281	.yres = 272,
	282	.pixclock = 111111, /* picosecond (9 MHz) */
	283	.left_margin = 2,
	284	.right_margin = 2,
	285	.upper_margin = 2,
	286	.lower_margin = 2,
	287	.hsync_len = 41,
	288	.vsync_len = 10,
	289	.sync = 0x40000000,
	290	.vmode = FB_VMODE_NONINTERLACED
	291	}
	292	}, {
	293	.bus = 0,
	294	.addr = 0,
	295	.detect = detect_lvds,
	296	.enable = enable_lvds_etm0700g0dh6,
	297	.pixfmt = IPU_PIX_FMT_RGB666,
	298	.mode = {
	299	.name = "edt,etm0700g0dh6",
	300	.refresh = 60,
	301	.xres = 800,
	302	.yres = 480,
	303	.pixclock = 30048, /* picosecond (33.28 MHz) */
	304	.left_margin = 40,
	305	.right_margin = 88,
	306	.upper_margin = 10,
	307	.lower_margin = 33,
	308	.hsync_len = 128,
	309	.vsync_len = 2,
	310	.sync = FB_SYNC_EXT,
	311	.vmode = FB_VMODE_NONINTERLACED
	312	}
	313	}
	314	};
	315
	316	size_t display_count = ARRAY_SIZE(displays);
39cb4f3c MV	317
	318	#ifdef CONFIG_SPLASH_SCREEN
	319	static struct splash_location default_splash_locations[] = {
	320	{
	321	.name = "mmc_fs",
	322	.storage = SPLASH_STORAGE_MMC,
	323	.flags = SPLASH_STORAGE_FS,
	324	.devpart = "0:1",
	325	},
	326	};
	327
	328	int splash_screen_prepare(void)
	329	{
	330	return splash_source_load(default_splash_locations,
	331	ARRAY_SIZE(default_splash_locations));
	332	}
	333	#endif
	334
f0be8ff4 MV	335	int board_late_init(void)
	336	{
	337	#if defined(CONFIG_VIDEO_IPUV3)
	338	struct udevice *dev;
	339	int xpos, ypos, ret;
	340	char *s;
	341	void *dst;
	342	ulong addr, len;
	343
	344	splash_get_pos(&xpos, &ypos);
	345
	346	s = env_get("splashimage");
	347	if (!s)
	348	return 0;
	349
	350	addr = simple_strtoul(s, NULL, 16);
	351	dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
	352	if (!dst)
	353	return -ENOMEM;
	354
	355	ret = splash_screen_prepare();
	356	if (ret < 0)
dae6cb8f	357	goto splasherr;
f0be8ff4 MV	358
	359	len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
	360	ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
	361	(uchar *)addr, &len);
	362	if (ret) {
	363	printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
dae6cb8f	364	goto splasherr;
f0be8ff4 MV	365	}
	366
	367	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
	368	if (ret)
dae6cb8f	369	goto splasherr;
f0be8ff4 MV	370
	371	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
	372	if (ret)
dae6cb8f MV	373	goto splasherr;
	374
	375	return 0;
	376
	377	splasherr:
	378	free(dst);
f0be8ff4 MV	379	#endif
	380	return 0;
	381	}
	382
39cb4f3c MV	383	#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST \| PAD_CTL_DSE_HIGH \| \
	384	PAD_CTL_PUS_100K_UP \| PAD_CTL_ODE)
	385
	386	static void setup_iomux_i2c(void)
	387	{
	388	static const iomux_v3_cfg_t i2c_pads[] = {
	389	/* I2C1 */
	390	NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
	391	NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
	392	/* I2C2 */
	393	NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
	394	NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
	395	};
	396
	397	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
	398	}
	399
	400	static void setup_iomux_video(void)
	401	{
	402	static const iomux_v3_cfg_t lcd_pads[] = {
	403	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
	404	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
	405	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
	406	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
	407	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
	408	};
	409
	410	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
	411	}
	412
	413	static void setup_iomux_nand(void)
	414	{
	415	static const iomux_v3_cfg_t nand_pads[] = {
	416	NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
	417	PAD_CTL_DSE_HIGH),
	418	NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
	419	PAD_CTL_DSE_HIGH),
	420	NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
	421	PAD_CTL_DSE_HIGH),
	422	NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
	423	PAD_CTL_DSE_HIGH),
	424	NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
	425	PAD_CTL_PUS_100K_UP),
	426	NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
	427	PAD_CTL_PUS_100K_UP),
	428	NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
	429	PAD_CTL_DSE_HIGH),
	430	NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
	431	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	432	NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
	433	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	434	NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
	435	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	436	NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
	437	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	438	NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
	439	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	440	NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
	441	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	442	NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
	443	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	444	NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
	445	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	446	};
447
448	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
449	}
450
451	static void m53_set_clock(void)
452	{
453	int ret;
454	const u32 ref_clk = MXC_HCLK;
455	const u32 dramclk = 400;
456	u32 cpuclk;
457
9b352ae1 MV	458	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
9b352ae1 MV	459
39cb4f3c MV	460	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
	461	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE));
	462	gpio_direction_input(IMX_GPIO_NR(4, 0));
	463
	464	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	465	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
	466
	467	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	468	if (ret)
	469	printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
	470
	471	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	472	if (ret) {
	473	printf("CPU: Switch peripheral clock to %dMHz failed\n",
	474	dramclk);
	475	}
	476
	477	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	478	if (ret)
	479	printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
	480	}
	481
	482	static void m53_set_nand(void)
	483	{
	484	u32 i;
	485
	486	/* NAND flash is muxed on ATA pins */
	487	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
	488
	489	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	490	for (i = 0x4; i < 0x94; i += 0x18) {
	491	clrbits_le32(WEIM_BASE_ADDR + i,
	492	WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	493	}
	494
	495	mxc_set_clock(0, 33, MXC_NFC_CLK);
	496	enable_nfc_clk(1);
	497	}
	498
	499	int board_early_init_f(void)
	500	{
	501	setup_iomux_uart();
	502	setup_iomux_fec();
	503	setup_iomux_i2c();
	504	setup_iomux_nand();
	505	setup_iomux_video();
	506
	507	m53_set_clock();
	508
	509	mxc_set_sata_internal_clock();
	510
	511	/* NAND clock @ 33MHz */
	512	m53_set_nand();
	513
	514	return 0;
	515	}
	516
	517	int board_init(void)
	518	{
	519	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	520
	521	return 0;
	522	}
	523
524	int checkboard(void)
525	{
526	puts("Board: Menlosystems M53Menlo\n");
527
528	return 0;
529	}
530
531	/*
532	* NAND SPL
533	*/
534	#ifdef CONFIG_SPL_BUILD
535	void spl_board_init(void)
536	{
537	setup_iomux_nand();
538	m53_set_clock();
539	m53_set_nand();
540	}
541
542	u32 spl_boot_device(void)
543	{
544	return BOOT_DEVICE_NAND;
545	}
546	#endif