[u-boot.git] / arch / x86 / lib / mpspec.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015, Bin Meng <[email protected]>
 *
 * Adapted from coreboot src/arch/x86/boot/mpspec.c
 */

#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/cpu.h>
#include <asm/global_data.h>
#include <asm/irq.h>
#include <asm/ioapic.h>
#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <dm/uclass-internal.h>

DECLARE_GLOBAL_DATA_PTR;

static bool isa_irq_occupied[16];

struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
{
	ulong mc;

	memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
	mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
	mf->mpf_length = 1;
	mf->mpf_spec = MPSPEC_V14;
	mf->mpf_checksum = 0;
	/* We don't use the default configuration table */
	mf->mpf_feature1 = 0;
	/* Indicate that virtual wire mode is always implemented */
	mf->mpf_feature2 = 0;
	mf->mpf_feature3 = 0;
	mf->mpf_feature4 = 0;
	mf->mpf_feature5 = 0;
	mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);

	mc = (ulong)mf + sizeof(struct mp_floating_table);
	return (struct mp_config_table *)mc;
}

void mp_config_table_init(struct mp_config_table *mc)
{
	memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
	mc->mpc_length = sizeof(struct mp_config_table);
	mc->mpc_spec = MPSPEC_V14;
	mc->mpc_checksum = 0;
	mc->mpc_oemptr = 0;
	mc->mpc_oemsize = 0;
	mc->mpc_entry_count = 0;
	mc->mpc_lapic = LAPIC_DEFAULT_BASE;
	mc->mpe_length = 0;
	mc->mpe_checksum = 0;
	mc->reserved = 0;

	/* The oem/product id fields are exactly 8/12 bytes long */
	table_fill_string(mc->mpc_oem, CONFIG_SYS_VENDOR, 8, ' ');
	table_fill_string(mc->mpc_product, CONFIG_SYS_BOARD, 12, ' ');
}

void mp_write_processor(struct mp_config_table *mc)
{
	struct mpc_config_processor *mpc;
	struct udevice *dev;
	u8 boot_apicid, apicver;
	u32 cpusignature, cpufeature;
	struct cpuid_result result;

	boot_apicid = lapicid();
	apicver = lapic_read(LAPIC_LVR) & 0xff;
	result = cpuid(1);
	cpusignature = result.eax;
	cpufeature = result.edx;

	for (uclass_find_first_device(UCLASS_CPU, &dev);
	     dev;
	     uclass_find_next_device(&dev)) {
		struct cpu_plat *plat = dev_get_parent_plat(dev);
		u8 cpuflag = MPC_CPU_EN;

		if (!device_active(dev))
			continue;

		mpc = (struct mpc_config_processor *)mp_next_mpc_entry(mc);
		mpc->mpc_type = MP_PROCESSOR;
		mpc->mpc_apicid = plat->cpu_id;
		mpc->mpc_apicver = apicver;
		if (boot_apicid == plat->cpu_id)
			cpuflag |= MPC_CPU_BP;
		mpc->mpc_cpuflag = cpuflag;
		mpc->mpc_cpusignature = cpusignature;
		mpc->mpc_cpufeature = cpufeature;
		mpc->mpc_reserved[0] = 0;
		mpc->mpc_reserved[1] = 0;
		mp_add_mpc_entry(mc, sizeof(*mpc));
	}
}

void mp_write_bus(struct mp_config_table *mc, int id, const char *bustype)
{
	struct mpc_config_bus *mpc;

	mpc = (struct mpc_config_bus *)mp_next_mpc_entry(mc);
	mpc->mpc_type = MP_BUS;
	mpc->mpc_busid = id;
	memcpy(mpc->mpc_bustype, bustype, 6);
	mp_add_mpc_entry(mc, sizeof(*mpc));
}

void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr)
{
	struct mpc_config_ioapic *mpc;

	mpc = (struct mpc_config_ioapic *)mp_next_mpc_entry(mc);
	mpc->mpc_type = MP_IOAPIC;
	mpc->mpc_apicid = id;
	mpc->mpc_apicver = ver;
	mpc->mpc_flags = MPC_APIC_USABLE;
	mpc->mpc_apicaddr = apicaddr;
	mp_add_mpc_entry(mc, sizeof(*mpc));
}

void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
		     int srcbus, int srcbusirq, int dstapic, int dstirq)
{
	struct mpc_config_intsrc *mpc;

	mpc = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
	mpc->mpc_type = MP_INTSRC;
	mpc->mpc_irqtype = irqtype;
	mpc->mpc_irqflag = irqflag;
	mpc->mpc_srcbus = srcbus;
	mpc->mpc_srcbusirq = srcbusirq;
	mpc->mpc_dstapic = dstapic;
	mpc->mpc_dstirq = dstirq;
	mp_add_mpc_entry(mc, sizeof(*mpc));
}

void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
			 int srcbus, int dev, int pin, int dstapic, int dstirq)
{
	u8 srcbusirq = (dev << 2) | (pin - 1);

	mp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
			srcbus, srcbusirq, dstapic, dstirq);
}

void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
		      int srcbus, int srcbusirq, int destapic, int destlint)
{
	struct mpc_config_lintsrc *mpc;

	mpc = (struct mpc_config_lintsrc *)mp_next_mpc_entry(mc);
	mpc->mpc_type = MP_LINTSRC;
	mpc->mpc_irqtype = irqtype;
	mpc->mpc_irqflag = irqflag;
	mpc->mpc_srcbusid = srcbus;
	mpc->mpc_srcbusirq = srcbusirq;
	mpc->mpc_destapic = destapic;
	mpc->mpc_destlint = destlint;
	mp_add_mpc_entry(mc, sizeof(*mpc));
}

void mp_write_address_space(struct mp_config_table *mc,
			    int busid, int addr_type,
			    u32 addr_base_low, u32 addr_base_high,
			    u32 addr_length_low, u32 addr_length_high)
{
	struct mp_ext_system_address_space *mpe;

	mpe = (struct mp_ext_system_address_space *)mp_next_mpe_entry(mc);
	mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
	mpe->mpe_length = sizeof(*mpe);
	mpe->mpe_busid = busid;
	mpe->mpe_addr_type = addr_type;
	mpe->mpe_addr_base_low = addr_base_low;
	mpe->mpe_addr_base_high = addr_base_high;
	mpe->mpe_addr_length_low = addr_length_low;
	mpe->mpe_addr_length_high = addr_length_high;
	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
}

void mp_write_bus_hierarchy(struct mp_config_table *mc,
			    int busid, int bus_info, int parent_busid)
{
	struct mp_ext_bus_hierarchy *mpe;

	mpe = (struct mp_ext_bus_hierarchy *)mp_next_mpe_entry(mc);
	mpe->mpe_type = MPE_BUS_HIERARCHY;
	mpe->mpe_length = sizeof(*mpe);
	mpe->mpe_busid = busid;
	mpe->mpe_bus_info = bus_info;
	mpe->mpe_parent_busid = parent_busid;
	mpe->reserved[0] = 0;
	mpe->reserved[1] = 0;
	mpe->reserved[2] = 0;
	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
}

void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
				   int addr_modifier, u32 range_list)
{
	struct mp_ext_compat_address_space *mpe;

	mpe = (struct mp_ext_compat_address_space *)mp_next_mpe_entry(mc);
	mpe->mpe_type = MPE_COMPAT_ADDRESS_SPACE;
	mpe->mpe_length = sizeof(*mpe);
	mpe->mpe_busid = busid;
	mpe->mpe_addr_modifier = addr_modifier;
	mpe->mpe_range_list = range_list;
	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
}

u32 mptable_finalize(struct mp_config_table *mc)
{
	ulong end;

	mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
						  mc->mpe_length);
	mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
	end = mp_next_mpe_entry(mc);

	debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);

	return end;
}

static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
				       int apicid, int external_int2)
{
	int i;

	mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
			bus_isa, 0, apicid, 0);
	mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
			bus_isa, 1, apicid, 1);
	mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
			bus_isa, 0, apicid, 2);

	for (i = 3; i < 16; i++) {
		/*
		 * Do not write ISA interrupt entry if it is already occupied
		 * by the platform devices.
		 */
		if (isa_irq_occupied[i])
			continue;

		mp_write_intsrc(mc, MP_INT,
				MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
				bus_isa, i, apicid, i);
	}
}

/*
 * Check duplicated I/O interrupt assignment table entry, to make sure
 * there is only one entry with the given bus, device and interrupt pin.
 */
static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
			    int entry_num, int bus, int device, int pin)
{
	struct mpc_config_intsrc *intsrc = intsrc_base;
	int i;

	for (i = 0; i < entry_num; i++) {
		if (intsrc->mpc_srcbus == bus &&
		    intsrc->mpc_srcbusirq == ((device << 2) | (pin - 1)))
			break;
		intsrc++;
	}

	return (i == entry_num) ? false : true;
}

/* TODO: move this to driver model */
__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
{
	/* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */
	return pirq + 16;
}

static int mptable_add_intsrc(struct mp_config_table *mc,
			      int bus_isa, int apicid)
{
	struct mpc_config_intsrc *intsrc_base;
	int intsrc_entries = 0;
	const void *blob = gd->fdt_blob;
	struct udevice *dev;
	int len, count;
	const u32 *cell;
	int i, ret;

	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
	if (ret && ret != -ENODEV) {
		debug("%s: Cannot find irq router node\n", __func__);
		return ret;
	}

	/* Get I/O interrupt information from device tree */
	cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
			   &len);
	if (!cell)
		return -ENOENT;

	if ((len % sizeof(struct pirq_routing)) == 0)
		count = len / sizeof(struct pirq_routing);
	else
		return -EINVAL;

	intsrc_base = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);

	for (i = 0; i < count; i++) {
		struct pirq_routing pr;
		int bus, dev, func;
		int dstirq;

		pr.bdf = fdt_addr_to_cpu(cell[0]);
		pr.pin = fdt_addr_to_cpu(cell[1]);
		pr.pirq = fdt_addr_to_cpu(cell[2]);
		bus = PCI_BUS(pr.bdf);
		dev = PCI_DEV(pr.bdf);
		func = PCI_FUNC(pr.bdf);

		if (check_dup_entry(intsrc_base, intsrc_entries,
				    bus, dev, pr.pin)) {
			debug("found entry for bus %d device %d INT%c, skipping\n",
			      bus, dev, 'A' + pr.pin - 1);
			cell += sizeof(struct pirq_routing) / sizeof(u32);
			continue;
		}

		dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq);
		/*
		 * For PIRQ which is connected to I/O APIC interrupt pin#0-15,
		 * mark it as occupied so that we can skip it later.
		 */
		if (dstirq < 16)
			isa_irq_occupied[dstirq] = true;
		mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin,
				    apicid, dstirq);
		intsrc_entries++;
		cell += sizeof(struct pirq_routing) / sizeof(u32);
	}

	/* Legacy Interrupts */
	debug("Writing ISA IRQs\n");
	mptable_add_isa_interrupts(mc, bus_isa, apicid, 0);

	return 0;
}

static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
{
	mp_write_lintsrc(mc, MP_EXTINT,
			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
			 bus_isa, 0, MP_APIC_ALL, 0);
	mp_write_lintsrc(mc, MP_NMI,
			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
			 bus_isa, 0, MP_APIC_ALL, 1);
}

ulong write_mp_table(ulong addr)
{
	struct mp_config_table *mc;
	int ioapic_id, ioapic_ver;
	int bus_isa = 0xff;
	int ret;
	ulong end;

	/* 16 byte align the table address */
	addr = ALIGN(addr, 16);

	/* Write floating table */
	mc = mp_write_floating_table((struct mp_floating_table *)addr);

	/* Write configuration table header */
	mp_config_table_init(mc);

	/* Write processor entry */
	mp_write_processor(mc);

	/* Write bus entry */
	mp_write_bus(mc, bus_isa, BUSTYPE_ISA);

	/* Write I/O APIC entry */
	ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
	ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
	mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);

	/* Write I/O interrupt assignment entry */
	ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
	if (ret)
		debug("Failed to write I/O interrupt assignment table\n");

	/* Write local interrupt assignment entry */
	mptable_add_lintsrc(mc, bus_isa);

	/* Finalize the MP table */
	end = mptable_finalize(mc);

	return end;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7f5df8d4 BM	2	/*
	3	* Copyright (C) 2015, Bin Meng <[email protected]>
	4	*
	5	* Adapted from coreboot src/arch/x86/boot/mpspec.c
7f5df8d4 BM	6	*/
	7
	8	#include <common.h>
	9	#include <cpu.h>
	10	#include <dm.h>
07545d86 BM	11	#include <errno.h>
07545d86 BM	12	#include <fdtdec.h>
f7ae49fc	13	#include <log.h>
7f5df8d4	14	#include <asm/cpu.h>
401d1c4f	15	#include <asm/global_data.h>
07545d86	16	#include <asm/irq.h>
7f5df8d4 BM	17	#include <asm/ioapic.h>
	18	#include <asm/lapic.h>
	19	#include <asm/mpspec.h>
	20	#include <asm/tables.h>
	21	#include <dm/uclass-internal.h>
	22
07545d86 BM	23	DECLARE_GLOBAL_DATA_PTR;
07545d86 BM	24
53832bb8 BM	25	static bool isa_irq_occupied[16];
53832bb8 BM	26
7f5df8d4 BM	27	struct mp_config_table mp_write_floating_table(struct mp_floating_table mf)
7f5df8d4 BM	28	{
e71ffd09	29	ulong mc;
7f5df8d4 BM	30
7f5df8d4 BM	31	memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
e71ffd09	32	mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
7f5df8d4 BM	33	mf->mpf_length = 1;
	34	mf->mpf_spec = MPSPEC_V14;
	35	mf->mpf_checksum = 0;
	36	/* We don't use the default configuration table */
	37	mf->mpf_feature1 = 0;
	38	/* Indicate that virtual wire mode is always implemented */
	39	mf->mpf_feature2 = 0;
	40	mf->mpf_feature3 = 0;
	41	mf->mpf_feature4 = 0;
	42	mf->mpf_feature5 = 0;
	43	mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
	44
e71ffd09	45	mc = (ulong)mf + sizeof(struct mp_floating_table);
7f5df8d4 BM	46	return (struct mp_config_table *)mc;
	47	}
	48
	49	void mp_config_table_init(struct mp_config_table *mc)
	50	{
	51	memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
	52	mc->mpc_length = sizeof(struct mp_config_table);
	53	mc->mpc_spec = MPSPEC_V14;
	54	mc->mpc_checksum = 0;
	55	mc->mpc_oemptr = 0;
	56	mc->mpc_oemsize = 0;
	57	mc->mpc_entry_count = 0;
	58	mc->mpc_lapic = LAPIC_DEFAULT_BASE;
	59	mc->mpe_length = 0;
	60	mc->mpe_checksum = 0;
	61	mc->reserved = 0;
	62
	63	/* The oem/product id fields are exactly 8/12 bytes long */
	64	table_fill_string(mc->mpc_oem, CONFIG_SYS_VENDOR, 8, ' ');
	65	table_fill_string(mc->mpc_product, CONFIG_SYS_BOARD, 12, ' ');
	66	}
	67
	68	void mp_write_processor(struct mp_config_table *mc)
	69	{
	70	struct mpc_config_processor *mpc;
	71	struct udevice *dev;
	72	u8 boot_apicid, apicver;
	73	u32 cpusignature, cpufeature;
	74	struct cpuid_result result;
	75
	76	boot_apicid = lapicid();
	77	apicver = lapic_read(LAPIC_LVR) & 0xff;
	78	result = cpuid(1);
	79	cpusignature = result.eax;
	80	cpufeature = result.edx;
	81
	82	for (uclass_find_first_device(UCLASS_CPU, &dev);
	83	dev;
	84	uclass_find_next_device(&dev)) {
8a8d24bd	85	struct cpu_plat *plat = dev_get_parent_plat(dev);
7f5df8d4 BM	86	u8 cpuflag = MPC_CPU_EN;
	87
	88	if (!device_active(dev))
	89	continue;
	90
	91	mpc = (struct mpc_config_processor *)mp_next_mpc_entry(mc);
	92	mpc->mpc_type = MP_PROCESSOR;
	93	mpc->mpc_apicid = plat->cpu_id;
	94	mpc->mpc_apicver = apicver;
	95	if (boot_apicid == plat->cpu_id)
	96	cpuflag \|= MPC_CPU_BP;
	97	mpc->mpc_cpuflag = cpuflag;
	98	mpc->mpc_cpusignature = cpusignature;
	99	mpc->mpc_cpufeature = cpufeature;
	100	mpc->mpc_reserved[0] = 0;
	101	mpc->mpc_reserved[1] = 0;
	102	mp_add_mpc_entry(mc, sizeof(*mpc));
	103	}
	104	}
	105
	106	void mp_write_bus(struct mp_config_table mc, int id, const char bustype)
	107	{
	108	struct mpc_config_bus *mpc;
	109
	110	mpc = (struct mpc_config_bus *)mp_next_mpc_entry(mc);
	111	mpc->mpc_type = MP_BUS;
	112	mpc->mpc_busid = id;
	113	memcpy(mpc->mpc_bustype, bustype, 6);
	114	mp_add_mpc_entry(mc, sizeof(*mpc));
	115	}
	116
	117	void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr)
	118	{
	119	struct mpc_config_ioapic *mpc;
	120
	121	mpc = (struct mpc_config_ioapic *)mp_next_mpc_entry(mc);
	122	mpc->mpc_type = MP_IOAPIC;
	123	mpc->mpc_apicid = id;
	124	mpc->mpc_apicver = ver;
	125	mpc->mpc_flags = MPC_APIC_USABLE;
	126	mpc->mpc_apicaddr = apicaddr;
	127	mp_add_mpc_entry(mc, sizeof(*mpc));
	128	}
	129
	130	void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
	131	int srcbus, int srcbusirq, int dstapic, int dstirq)
	132	{
	133	struct mpc_config_intsrc *mpc;
	134
	135	mpc = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
	136	mpc->mpc_type = MP_INTSRC;
	137	mpc->mpc_irqtype = irqtype;
	138	mpc->mpc_irqflag = irqflag;
	139	mpc->mpc_srcbus = srcbus;
	140	mpc->mpc_srcbusirq = srcbusirq;
	141	mpc->mpc_dstapic = dstapic;
	142	mpc->mpc_dstirq = dstirq;
	143	mp_add_mpc_entry(mc, sizeof(*mpc));
	144	}
	145
	146	void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
	147	int srcbus, int dev, int pin, int dstapic, int dstirq)
	148	{
	149	u8 srcbusirq = (dev << 2) \| (pin - 1);
150
151	mp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL \| MP_IRQ_POLARITY_LOW,
152	srcbus, srcbusirq, dstapic, dstirq);
153	}
154
155	void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
156	int srcbus, int srcbusirq, int destapic, int destlint)
157	{
158	struct mpc_config_lintsrc *mpc;
159
160	mpc = (struct mpc_config_lintsrc *)mp_next_mpc_entry(mc);
161	mpc->mpc_type = MP_LINTSRC;
162	mpc->mpc_irqtype = irqtype;
163	mpc->mpc_irqflag = irqflag;
164	mpc->mpc_srcbusid = srcbus;
165	mpc->mpc_srcbusirq = srcbusirq;
166	mpc->mpc_destapic = destapic;
167	mpc->mpc_destlint = destlint;
168	mp_add_mpc_entry(mc, sizeof(*mpc));
169	}
170
171	void mp_write_address_space(struct mp_config_table *mc,
172	int busid, int addr_type,
173	u32 addr_base_low, u32 addr_base_high,
174	u32 addr_length_low, u32 addr_length_high)
175	{
176	struct mp_ext_system_address_space *mpe;
177
178	mpe = (struct mp_ext_system_address_space *)mp_next_mpe_entry(mc);
179	mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
180	mpe->mpe_length = sizeof(*mpe);
181	mpe->mpe_busid = busid;
182	mpe->mpe_addr_type = addr_type;
183	mpe->mpe_addr_base_low = addr_base_low;
184	mpe->mpe_addr_base_high = addr_base_high;
185	mpe->mpe_addr_length_low = addr_length_low;
186	mpe->mpe_addr_length_high = addr_length_high;
187	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
188	}
189
190	void mp_write_bus_hierarchy(struct mp_config_table *mc,
191	int busid, int bus_info, int parent_busid)
192	{
193	struct mp_ext_bus_hierarchy *mpe;
194
195	mpe = (struct mp_ext_bus_hierarchy *)mp_next_mpe_entry(mc);
196	mpe->mpe_type = MPE_BUS_HIERARCHY;
197	mpe->mpe_length = sizeof(*mpe);
198	mpe->mpe_busid = busid;
199	mpe->mpe_bus_info = bus_info;
200	mpe->mpe_parent_busid = parent_busid;
201	mpe->reserved[0] = 0;
202	mpe->reserved[1] = 0;
203	mpe->reserved[2] = 0;
204	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
205	}
206
207	void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
208	int addr_modifier, u32 range_list)
209	{
210	struct mp_ext_compat_address_space *mpe;
211
212	mpe = (struct mp_ext_compat_address_space *)mp_next_mpe_entry(mc);
213	mpe->mpe_type = MPE_COMPAT_ADDRESS_SPACE;
214	mpe->mpe_length = sizeof(*mpe);
215	mpe->mpe_busid = busid;
216	mpe->mpe_addr_modifier = addr_modifier;
217	mpe->mpe_range_list = range_list;
218	mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
219	}
220
221	u32 mptable_finalize(struct mp_config_table *mc)
222	{
e71ffd09	223	ulong end;
7f5df8d4 BM	224
	225	mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
	226	mc->mpe_length);
	227	mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
	228	end = mp_next_mpe_entry(mc);
	229
e71ffd09	230	debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
7f5df8d4 BM	231
	232	return end;
	233	}
07545d86 BM	234
	235	static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
	236	int apicid, int external_int2)
	237	{
	238	int i;
	239
	240	mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
	241	MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	242	bus_isa, 0, apicid, 0);
	243	mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	244	bus_isa, 1, apicid, 1);
	245	mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
	246	MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	247	bus_isa, 0, apicid, 2);
	248
53832bb8 BM	249	for (i = 3; i < 16; i++) {
	250	/*
	251	* Do not write ISA interrupt entry if it is already occupied
	252	* by the platform devices.
	253	*/
	254	if (isa_irq_occupied[i])
	255	continue;
	256
07545d86 BM	257	mp_write_intsrc(mc, MP_INT,
	258	MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	259	bus_isa, i, apicid, i);
53832bb8	260	}
07545d86 BM	261	}
	262
	263	/*
	264	* Check duplicated I/O interrupt assignment table entry, to make sure
	265	* there is only one entry with the given bus, device and interrupt pin.
	266	*/
	267	static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
	268	int entry_num, int bus, int device, int pin)
	269	{
	270	struct mpc_config_intsrc *intsrc = intsrc_base;
	271	int i;
	272
	273	for (i = 0; i < entry_num; i++) {
	274	if (intsrc->mpc_srcbus == bus &&
	275	intsrc->mpc_srcbusirq == ((device << 2) \| (pin - 1)))
	276	break;
	277	intsrc++;
	278	}
	279
	280	return (i == entry_num) ? false : true;
	281	}
	282
abab9128 BM	283	/* TODO: move this to driver model */
	284	__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
	285	{
	286	/* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */
	287	return pirq + 16;
	288	}
	289
07545d86 BM	290	static int mptable_add_intsrc(struct mp_config_table *mc,
	291	int bus_isa, int apicid)
	292	{
	293	struct mpc_config_intsrc *intsrc_base;
	294	int intsrc_entries = 0;
	295	const void *blob = gd->fdt_blob;
b565d66d	296	struct udevice *dev;
07545d86 BM	297	int len, count;
07545d86 BM	298	const u32 *cell;
b565d66d	299	int i, ret;
07545d86	300
3f603cbb	301	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
b565d66d	302	if (ret && ret != -ENODEV) {
07545d86	303	debug("%s: Cannot find irq router node\n", __func__);
b565d66d	304	return ret;
07545d86 BM	305	}
07545d86 BM	306
b565d66d	307	/* Get I/O interrupt information from device tree */
e160f7d4 SG	308	cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
e160f7d4 SG	309	&len);
07545d86 BM	310	if (!cell)
	311	return -ENOENT;
	312
	313	if ((len % sizeof(struct pirq_routing)) == 0)
	314	count = len / sizeof(struct pirq_routing);
	315	else
	316	return -EINVAL;
	317
	318	intsrc_base = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
	319
	320	for (i = 0; i < count; i++) {
	321	struct pirq_routing pr;
abab9128 BM	322	int bus, dev, func;
abab9128 BM	323	int dstirq;
07545d86 BM	324
	325	pr.bdf = fdt_addr_to_cpu(cell[0]);
	326	pr.pin = fdt_addr_to_cpu(cell[1]);
	327	pr.pirq = fdt_addr_to_cpu(cell[2]);
abab9128 BM	328	bus = PCI_BUS(pr.bdf);
	329	dev = PCI_DEV(pr.bdf);
	330	func = PCI_FUNC(pr.bdf);
07545d86 BM	331
07545d86 BM	332	if (check_dup_entry(intsrc_base, intsrc_entries,
abab9128	333	bus, dev, pr.pin)) {
07545d86	334	debug("found entry for bus %d device %d INT%c, skipping\n",
abab9128	335	bus, dev, 'A' + pr.pin - 1);
07545d86 BM	336	cell += sizeof(struct pirq_routing) / sizeof(u32);
	337	continue;
	338	}
	339
abab9128	340	dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq);
53832bb8 BM	341	/*
	342	* For PIRQ which is connected to I/O APIC interrupt pin#0-15,
	343	* mark it as occupied so that we can skip it later.
	344	*/
	345	if (dstirq < 16)
	346	isa_irq_occupied[dstirq] = true;
abab9128 BM	347	mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin,
abab9128 BM	348	apicid, dstirq);
07545d86 BM	349	intsrc_entries++;
	350	cell += sizeof(struct pirq_routing) / sizeof(u32);
	351	}
	352
53832bb8 BM	353	/* Legacy Interrupts */
	354	debug("Writing ISA IRQs\n");
	355	mptable_add_isa_interrupts(mc, bus_isa, apicid, 0);
	356
07545d86 BM	357	return 0;
	358	}
	359
	360	static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
	361	{
	362	mp_write_lintsrc(mc, MP_EXTINT,
	363	MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	364	bus_isa, 0, MP_APIC_ALL, 0);
	365	mp_write_lintsrc(mc, MP_NMI,
	366	MP_IRQ_TRIGGER_EDGE \| MP_IRQ_POLARITY_HIGH,
	367	bus_isa, 0, MP_APIC_ALL, 1);
	368	}
	369
42fd8c19	370	ulong write_mp_table(ulong addr)
07545d86 BM	371	{
	372	struct mp_config_table *mc;
	373	int ioapic_id, ioapic_ver;
	374	int bus_isa = 0xff;
	375	int ret;
e71ffd09	376	ulong end;
07545d86 BM	377
	378	/* 16 byte align the table address */
	379	addr = ALIGN(addr, 16);
	380
	381	/* Write floating table */
	382	mc = mp_write_floating_table((struct mp_floating_table *)addr);
	383
	384	/* Write configuration table header */
	385	mp_config_table_init(mc);
	386
	387	/* Write processor entry */
	388	mp_write_processor(mc);
	389
	390	/* Write bus entry */
	391	mp_write_bus(mc, bus_isa, BUSTYPE_ISA);
	392
	393	/* Write I/O APIC entry */
	394	ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
	395	ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
	396	mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
	397
	398	/* Write I/O interrupt assignment entry */
	399	ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
	400	if (ret)
	401	debug("Failed to write I/O interrupt assignment table\n");
	402
	403	/* Write local interrupt assignment entry */
	404	mptable_add_lintsrc(mc, bus_isa);
	405
	406	/* Finalize the MP table */
	407	end = mptable_finalize(mc);
	408
	409	return end;
	410	}