[u-boot.git] / arch / x86 / cpu / i386 / interrupt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008-2011
 * Graeme Russ, <[email protected]>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <[email protected]>
 *
 * Portions of this file are derived from the Linux kernel source
 *  Copyright (C) 1991, 1992  Linus Torvalds
 */

#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <hang.h>
#include <init.h>
#include <irq.h>
#include <irq_func.h>
#include <asm/control_regs.h>
#include <asm/global_data.h>
#include <asm/i8259.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/processor-flags.h>
#include <asm/ptrace.h>

DECLARE_GLOBAL_DATA_PTR;

#define DECLARE_INTERRUPT(x) \
	".globl irq_"#x"\n" \
	".hidden irq_"#x"\n" \
	".type irq_"#x", @function\n" \
	"irq_"#x":\n" \
	"pushl $"#x"\n" \
	"jmp.d32 irq_common_entry\n"

static char *exceptions[] = {
	"Divide Error",
	"Debug",
	"NMI Interrupt",
	"Breakpoint",
	"Overflow",
	"BOUND Range Exceeded",
	"Invalid Opcode (Undefined Opcode)",
	"Device Not Available (No Math Coprocessor)",
	"Double Fault",
	"Coprocessor Segment Overrun",
	"Invalid TSS",
	"Segment Not Present",
	"Stack Segment Fault",
	"General Protection",
	"Page Fault",
	"Reserved",
	"x87 FPU Floating-Point Error",
	"Alignment Check",
	"Machine Check",
	"SIMD Floating-Point Exception",
	"Virtualization Exception",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved"
};

/**
 * show_efi_loaded_images() - show loaded UEFI images
 *
 * List all loaded UEFI images.
 *
 * @eip:	instruction pointer
 */
static void show_efi_loaded_images(uintptr_t eip)
{
	efi_print_image_infos((void *)eip);
}

static void dump_regs(struct irq_regs *regs)
{
	unsigned long cs, eip, eflags;
	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
	unsigned long d0, d1, d2, d3, d6, d7;
	unsigned long sp;

	/*
	 * Some exceptions cause an error code to be saved on the current stack
	 * after the EIP value. We should extract CS/EIP/EFLAGS from different
	 * position on the stack based on the exception number.
	 */
	switch (regs->irq_id) {
	case EXC_DF:
	case EXC_TS:
	case EXC_NP:
	case EXC_SS:
	case EXC_GP:
	case EXC_PF:
	case EXC_AC:
		cs = regs->context.ctx2.xcs;
		eip = regs->context.ctx2.eip;
		eflags = regs->context.ctx2.eflags;
		/* We should fix up the ESP due to error code */
		regs->esp += 4;
		break;
	default:
		cs = regs->context.ctx1.xcs;
		eip = regs->context.ctx1.eip;
		eflags = regs->context.ctx1.eflags;
		break;
	}

	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
			(u16)cs, eip, eflags);
	if (gd->flags & GD_FLG_RELOC)
		printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);

	printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
		regs->eax, regs->ebx, regs->ecx, regs->edx);
	printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
		regs->esi, regs->edi, regs->ebp, regs->esp);
	printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
	       (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
	       (u16)regs->xgs, (u16)regs->xss);

	cr0 = read_cr0();
	cr2 = read_cr2();
	cr3 = read_cr3();
	cr4 = read_cr4();

	printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
			cr0, cr2, cr3, cr4);

	d0 = get_debugreg(0);
	d1 = get_debugreg(1);
	d2 = get_debugreg(2);
	d3 = get_debugreg(3);

	printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
			d0, d1, d2, d3);

	d6 = get_debugreg(6);
	d7 = get_debugreg(7);
	printf("DR6: %08lx DR7: %08lx\n",
			d6, d7);

	printf("Stack:\n");
	sp = regs->esp;

	sp += 64;

	while (sp > (regs->esp - 16)) {
		if (sp == regs->esp)
			printf("--->");
		else
			printf("    ");
		printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
		sp -= 4;
	}
	show_efi_loaded_images(eip);
}

static void do_exception(struct irq_regs *regs)
{
	printf("%s\n", exceptions[regs->irq_id]);
	dump_regs(regs);
	hang();
}

struct idt_entry {
	u16	base_low;
	u16	selector;
	u8	res;
	u8	access;
	u16	base_high;
} __packed;

struct idt_entry idt[256] __aligned(16);

struct idt_ptr idt_ptr;

static inline void load_idt(const struct idt_ptr *dtr)
{
	asm volatile("cs lidt %0" : : "m" (*dtr));
}

void set_vector(u8 intnum, void *routine)
{
	idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
	idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
}

/*
 * Ideally these would be defined static to avoid a checkpatch warning, but
 * the compiler cannot see them in the inline asm and complains that they
 * aren't defined
 */
void irq_0(void);
void irq_1(void);

int cpu_init_interrupts(void)
{
	int i;

	int irq_entry_size = irq_1 - irq_0;
	void *irq_entry = (void *)irq_0;

	/* Setup the IDT */
	for (i = 0; i < 256; i++) {
		idt[i].access = 0x8e;
		idt[i].res = 0;
		idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
		set_vector(i, irq_entry);
		irq_entry += irq_entry_size;
	}

	idt_ptr.size = 256 * 8 - 1;
	idt_ptr.address = (unsigned long) idt;

	load_idt(&idt_ptr);

	return 0;
}

void interrupt_read_idt(struct idt_ptr *ptr)
{
	asm volatile("sidt %0" : : "m" (*ptr));
}

void *x86_get_idt(void)
{
	return &idt_ptr;
}

void __do_irq(int irq)
{
	printf("Unhandled IRQ : %d\n", irq);
}
void do_irq(int irq) __attribute__((weak, alias("__do_irq")));

void enable_interrupts(void)
{
	asm("sti\n");
}

int disable_interrupts(void)
{
	long flags;

#if CONFIG_IS_ENABLED(X86_64)
	asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
#else
	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
#endif
	return flags & X86_EFLAGS_IF;
}

int interrupt_init(void)
{
	struct udevice *dev;
	int ret;

	if (!ll_boot_init())
		return 0;

	/* Try to set up the interrupt router, but don't require one */
	ret = irq_first_device_type(X86_IRQT_BASE, &dev);
	if (ret && ret != -ENODEV)
		return ret;

	/*
	 * When running as an EFI application we are not in control of
	 * interrupts and should leave them alone.
	 */
#ifndef CONFIG_EFI_APP
	/* Just in case... */
	disable_interrupts();

#ifdef CONFIG_I8259_PIC
	/* Initialize the master/slave i8259 pic */
	i8259_init();
#endif

#ifdef CONFIG_APIC
	lapic_setup();
#endif

	/* Initialize core interrupt and exception functionality of CPU */
	cpu_init_interrupts();

	/*
	 * It is now safe to enable interrupts.
	 *
	 * TODO([email protected]): But we don't handle these correctly when
	 * booted from EFI.
	 */
	enable_interrupts();
#endif

	return 0;
}

/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{
	/*
	 * For detailed description of each exception, refer to:
	 * Intel® 64 and IA-32 Architectures Software Developer's Manual
	 * Volume 1: Basic Architecture
	 * Order Number: 253665-029US, November 2008
	 * Table 6-1. Exceptions and Interrupts
	 */
	if (regs->irq_id < 32) {
		/* Architecture defined exception */
		do_exception(regs);
	} else {
		/* Hardware or User IRQ */
		do_irq(regs->irq_id);
	}
}

/*
 * OK - This looks really horrible, but it serves a purpose - It helps create
 * fully relocatable code.
 *  - The call to irq_llsr will be a relative jump
 *  - The IRQ entries will be guaranteed to be in order
 *  Interrupt entries are now very small (a push and a jump) but they are
 *  now slower (all registers pushed on stack which provides complete
 *  crash dumps in the low level handlers
 *
 * Interrupt Entry Point:
 *  - Interrupt has caused eflags, CS and EIP to be pushed
 *  - Interrupt Vector Handler has pushed orig_eax
 *  - pt_regs.esp needs to be adjusted by 40 bytes:
 *      12 bytes pushed by CPU (EFLAGSF, CS, EIP)
 *      4 bytes pushed by vector handler (irq_id)
 *      24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
 *      NOTE: Only longs are pushed on/popped off the stack!
 */
asm(".globl irq_common_entry\n" \
	".hidden irq_common_entry\n" \
	".type irq_common_entry, @function\n" \
	"irq_common_entry:\n" \
	"cld\n" \
	"pushl %ss\n" \
	"pushl %gs\n" \
	"pushl %fs\n" \
	"pushl %es\n" \
	"pushl %ds\n" \
	"pushl %eax\n" \
	"movl  %esp, %eax\n" \
	"addl  $40, %eax\n" \
	"pushl %eax\n" \
	"pushl %ebp\n" \
	"pushl %edi\n" \
	"pushl %esi\n" \
	"pushl %edx\n" \
	"pushl %ecx\n" \
	"pushl %ebx\n" \
	"mov   %esp, %eax\n" \
	"call irq_llsr\n" \
	"popl %ebx\n" \
	"popl %ecx\n" \
	"popl %edx\n" \
	"popl %esi\n" \
	"popl %edi\n" \
	"popl %ebp\n" \
	"popl %eax\n" \
	"popl %eax\n" \
	"popl %ds\n" \
	"popl %es\n" \
	"popl %fs\n" \
	"popl %gs\n" \
	"popl %ss\n" \
	"add  $4, %esp\n" \
	"iret\n" \
	DECLARE_INTERRUPT(0) \
	DECLARE_INTERRUPT(1) \
	DECLARE_INTERRUPT(2) \
	DECLARE_INTERRUPT(3) \
	DECLARE_INTERRUPT(4) \
	DECLARE_INTERRUPT(5) \
	DECLARE_INTERRUPT(6) \
	DECLARE_INTERRUPT(7) \
	DECLARE_INTERRUPT(8) \
	DECLARE_INTERRUPT(9) \
	DECLARE_INTERRUPT(10) \
	DECLARE_INTERRUPT(11) \
	DECLARE_INTERRUPT(12) \
	DECLARE_INTERRUPT(13) \
	DECLARE_INTERRUPT(14) \
	DECLARE_INTERRUPT(15) \
	DECLARE_INTERRUPT(16) \
	DECLARE_INTERRUPT(17) \
	DECLARE_INTERRUPT(18) \
	DECLARE_INTERRUPT(19) \
	DECLARE_INTERRUPT(20) \
	DECLARE_INTERRUPT(21) \
	DECLARE_INTERRUPT(22) \
	DECLARE_INTERRUPT(23) \
	DECLARE_INTERRUPT(24) \
	DECLARE_INTERRUPT(25) \
	DECLARE_INTERRUPT(26) \
	DECLARE_INTERRUPT(27) \
	DECLARE_INTERRUPT(28) \
	DECLARE_INTERRUPT(29) \
	DECLARE_INTERRUPT(30) \
	DECLARE_INTERRUPT(31) \
	DECLARE_INTERRUPT(32) \
	DECLARE_INTERRUPT(33) \
	DECLARE_INTERRUPT(34) \
	DECLARE_INTERRUPT(35) \
	DECLARE_INTERRUPT(36) \
	DECLARE_INTERRUPT(37) \
	DECLARE_INTERRUPT(38) \
	DECLARE_INTERRUPT(39) \
	DECLARE_INTERRUPT(40) \
	DECLARE_INTERRUPT(41) \
	DECLARE_INTERRUPT(42) \
	DECLARE_INTERRUPT(43) \
	DECLARE_INTERRUPT(44) \
	DECLARE_INTERRUPT(45) \
	DECLARE_INTERRUPT(46) \
	DECLARE_INTERRUPT(47) \
	DECLARE_INTERRUPT(48) \
	DECLARE_INTERRUPT(49) \
	DECLARE_INTERRUPT(50) \
	DECLARE_INTERRUPT(51) \
	DECLARE_INTERRUPT(52) \
	DECLARE_INTERRUPT(53) \
	DECLARE_INTERRUPT(54) \
	DECLARE_INTERRUPT(55) \
	DECLARE_INTERRUPT(56) \
	DECLARE_INTERRUPT(57) \
	DECLARE_INTERRUPT(58) \
	DECLARE_INTERRUPT(59) \
	DECLARE_INTERRUPT(60) \
	DECLARE_INTERRUPT(61) \
	DECLARE_INTERRUPT(62) \
	DECLARE_INTERRUPT(63) \
	DECLARE_INTERRUPT(64) \
	DECLARE_INTERRUPT(65) \
	DECLARE_INTERRUPT(66) \
	DECLARE_INTERRUPT(67) \
	DECLARE_INTERRUPT(68) \
	DECLARE_INTERRUPT(69) \
	DECLARE_INTERRUPT(70) \
	DECLARE_INTERRUPT(71) \
	DECLARE_INTERRUPT(72) \
	DECLARE_INTERRUPT(73) \
	DECLARE_INTERRUPT(74) \
	DECLARE_INTERRUPT(75) \
	DECLARE_INTERRUPT(76) \
	DECLARE_INTERRUPT(77) \
	DECLARE_INTERRUPT(78) \
	DECLARE_INTERRUPT(79) \
	DECLARE_INTERRUPT(80) \
	DECLARE_INTERRUPT(81) \
	DECLARE_INTERRUPT(82) \
	DECLARE_INTERRUPT(83) \
	DECLARE_INTERRUPT(84) \
	DECLARE_INTERRUPT(85) \
	DECLARE_INTERRUPT(86) \
	DECLARE_INTERRUPT(87) \
	DECLARE_INTERRUPT(88) \
	DECLARE_INTERRUPT(89) \
	DECLARE_INTERRUPT(90) \
	DECLARE_INTERRUPT(91) \
	DECLARE_INTERRUPT(92) \
	DECLARE_INTERRUPT(93) \
	DECLARE_INTERRUPT(94) \
	DECLARE_INTERRUPT(95) \
	DECLARE_INTERRUPT(97) \
	DECLARE_INTERRUPT(96) \
	DECLARE_INTERRUPT(98) \
	DECLARE_INTERRUPT(99) \
	DECLARE_INTERRUPT(100) \
	DECLARE_INTERRUPT(101) \
	DECLARE_INTERRUPT(102) \
	DECLARE_INTERRUPT(103) \
	DECLARE_INTERRUPT(104) \
	DECLARE_INTERRUPT(105) \
	DECLARE_INTERRUPT(106) \
	DECLARE_INTERRUPT(107) \
	DECLARE_INTERRUPT(108) \
	DECLARE_INTERRUPT(109) \
	DECLARE_INTERRUPT(110) \
	DECLARE_INTERRUPT(111) \
	DECLARE_INTERRUPT(112) \
	DECLARE_INTERRUPT(113) \
	DECLARE_INTERRUPT(114) \
	DECLARE_INTERRUPT(115) \
	DECLARE_INTERRUPT(116) \
	DECLARE_INTERRUPT(117) \
	DECLARE_INTERRUPT(118) \
	DECLARE_INTERRUPT(119) \
	DECLARE_INTERRUPT(120) \
	DECLARE_INTERRUPT(121) \
	DECLARE_INTERRUPT(122) \
	DECLARE_INTERRUPT(123) \
	DECLARE_INTERRUPT(124) \
	DECLARE_INTERRUPT(125) \
	DECLARE_INTERRUPT(126) \
	DECLARE_INTERRUPT(127) \
	DECLARE_INTERRUPT(128) \
	DECLARE_INTERRUPT(129) \
	DECLARE_INTERRUPT(130) \
	DECLARE_INTERRUPT(131) \
	DECLARE_INTERRUPT(132) \
	DECLARE_INTERRUPT(133) \
	DECLARE_INTERRUPT(134) \
	DECLARE_INTERRUPT(135) \
	DECLARE_INTERRUPT(136) \
	DECLARE_INTERRUPT(137) \
	DECLARE_INTERRUPT(138) \
	DECLARE_INTERRUPT(139) \
	DECLARE_INTERRUPT(140) \
	DECLARE_INTERRUPT(141) \
	DECLARE_INTERRUPT(142) \
	DECLARE_INTERRUPT(143) \
	DECLARE_INTERRUPT(144) \
	DECLARE_INTERRUPT(145) \
	DECLARE_INTERRUPT(146) \
	DECLARE_INTERRUPT(147) \
	DECLARE_INTERRUPT(148) \
	DECLARE_INTERRUPT(149) \
	DECLARE_INTERRUPT(150) \
	DECLARE_INTERRUPT(151) \
	DECLARE_INTERRUPT(152) \
	DECLARE_INTERRUPT(153) \
	DECLARE_INTERRUPT(154) \
	DECLARE_INTERRUPT(155) \
	DECLARE_INTERRUPT(156) \
	DECLARE_INTERRUPT(157) \
	DECLARE_INTERRUPT(158) \
	DECLARE_INTERRUPT(159) \
	DECLARE_INTERRUPT(160) \
	DECLARE_INTERRUPT(161) \
	DECLARE_INTERRUPT(162) \
	DECLARE_INTERRUPT(163) \
	DECLARE_INTERRUPT(164) \
	DECLARE_INTERRUPT(165) \
	DECLARE_INTERRUPT(166) \
	DECLARE_INTERRUPT(167) \
	DECLARE_INTERRUPT(168) \
	DECLARE_INTERRUPT(169) \
	DECLARE_INTERRUPT(170) \
	DECLARE_INTERRUPT(171) \
	DECLARE_INTERRUPT(172) \
	DECLARE_INTERRUPT(173) \
	DECLARE_INTERRUPT(174) \
	DECLARE_INTERRUPT(175) \
	DECLARE_INTERRUPT(176) \
	DECLARE_INTERRUPT(177) \
	DECLARE_INTERRUPT(178) \
	DECLARE_INTERRUPT(179) \
	DECLARE_INTERRUPT(180) \
	DECLARE_INTERRUPT(181) \
	DECLARE_INTERRUPT(182) \
	DECLARE_INTERRUPT(183) \
	DECLARE_INTERRUPT(184) \
	DECLARE_INTERRUPT(185) \
	DECLARE_INTERRUPT(186) \
	DECLARE_INTERRUPT(187) \
	DECLARE_INTERRUPT(188) \
	DECLARE_INTERRUPT(189) \
	DECLARE_INTERRUPT(190) \
	DECLARE_INTERRUPT(191) \
	DECLARE_INTERRUPT(192) \
	DECLARE_INTERRUPT(193) \
	DECLARE_INTERRUPT(194) \
	DECLARE_INTERRUPT(195) \
	DECLARE_INTERRUPT(196) \
	DECLARE_INTERRUPT(197) \
	DECLARE_INTERRUPT(198) \
	DECLARE_INTERRUPT(199) \
	DECLARE_INTERRUPT(200) \
	DECLARE_INTERRUPT(201) \
	DECLARE_INTERRUPT(202) \
	DECLARE_INTERRUPT(203) \
	DECLARE_INTERRUPT(204) \
	DECLARE_INTERRUPT(205) \
	DECLARE_INTERRUPT(206) \
	DECLARE_INTERRUPT(207) \
	DECLARE_INTERRUPT(208) \
	DECLARE_INTERRUPT(209) \
	DECLARE_INTERRUPT(210) \
	DECLARE_INTERRUPT(211) \
	DECLARE_INTERRUPT(212) \
	DECLARE_INTERRUPT(213) \
	DECLARE_INTERRUPT(214) \
	DECLARE_INTERRUPT(215) \
	DECLARE_INTERRUPT(216) \
	DECLARE_INTERRUPT(217) \
	DECLARE_INTERRUPT(218) \
	DECLARE_INTERRUPT(219) \
	DECLARE_INTERRUPT(220) \
	DECLARE_INTERRUPT(221) \
	DECLARE_INTERRUPT(222) \
	DECLARE_INTERRUPT(223) \
	DECLARE_INTERRUPT(224) \
	DECLARE_INTERRUPT(225) \
	DECLARE_INTERRUPT(226) \
	DECLARE_INTERRUPT(227) \
	DECLARE_INTERRUPT(228) \
	DECLARE_INTERRUPT(229) \
	DECLARE_INTERRUPT(230) \
	DECLARE_INTERRUPT(231) \
	DECLARE_INTERRUPT(232) \
	DECLARE_INTERRUPT(233) \
	DECLARE_INTERRUPT(234) \
	DECLARE_INTERRUPT(235) \
	DECLARE_INTERRUPT(236) \
	DECLARE_INTERRUPT(237) \
	DECLARE_INTERRUPT(238) \
	DECLARE_INTERRUPT(239) \
	DECLARE_INTERRUPT(240) \
	DECLARE_INTERRUPT(241) \
	DECLARE_INTERRUPT(242) \
	DECLARE_INTERRUPT(243) \
	DECLARE_INTERRUPT(244) \
	DECLARE_INTERRUPT(245) \
	DECLARE_INTERRUPT(246) \
	DECLARE_INTERRUPT(247) \
	DECLARE_INTERRUPT(248) \
	DECLARE_INTERRUPT(249) \
	DECLARE_INTERRUPT(250) \
	DECLARE_INTERRUPT(251) \
	DECLARE_INTERRUPT(252) \
	DECLARE_INTERRUPT(253) \
	DECLARE_INTERRUPT(254) \
	DECLARE_INTERRUPT(255));
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2262cfee	2	/*
dbf7115a GR	3	* (C) Copyright 2008-2011
dbf7115a GR	4	* Graeme Russ, <[email protected]>
564a9984	5	*
2262cfee	6	* (C) Copyright 2002
fa82f871	7	* Daniel Engström, Omicron Ceti AB, <[email protected]>
2262cfee	8	*
433ff2bd GR	9	* Portions of this file are derived from the Linux kernel source
433ff2bd GR	10	* Copyright (C) 1991, 1992 Linus Torvalds
2262cfee WD	11	*/
	12
	13	#include <common.h>
12d6929e	14	#include <dm.h>
74b76357	15	#include <efi_loader.h>
db41d65a	16	#include <hang.h>
35a3f871	17	#include <init.h>
69c2dc93	18	#include <irq.h>
c30b7adb	19	#include <irq_func.h>
095593c0	20	#include <asm/control_regs.h>
401d1c4f	21	#include <asm/global_data.h>
e2126711	22	#include <asm/i8259.h>
9933d609	23	#include <asm/interrupt.h>
ca56a4ce	24	#include <asm/io.h>
e2126711	25	#include <asm/lapic.h>
e2126711	26	#include <asm/processor-flags.h>
25a5818f	27	#include <asm/ptrace.h>
2262cfee	28
7282d834 SG	29	DECLARE_GLOBAL_DATA_PTR;
7282d834 SG	30
564a9984 GR	31	#define DECLARE_INTERRUPT(x) \
564a9984 GR	32	".globl irq_"#x"\n" \
0fc1b49e GR	33	".hidden irq_"#x"\n" \
0fc1b49e GR	34	".type irq_"#x", @function\n" \
564a9984	35	"irq_"#x":\n" \
564a9984	36	"pushl $"#x"\n" \
3c03f492	37	"jmp.d32 irq_common_entry\n"
2262cfee	38
3ccd49ca BM	39	static char *exceptions[] = {
	40	"Divide Error",
	41	"Debug",
	42	"NMI Interrupt",
	43	"Breakpoint",
	44	"Overflow",
	45	"BOUND Range Exceeded",
	46	"Invalid Opcode (Undefined Opcode)",
048a92ea	47	"Device Not Available (No Math Coprocessor)",
3ccd49ca BM	48	"Double Fault",
	49	"Coprocessor Segment Overrun",
	50	"Invalid TSS",
	51	"Segment Not Present",
	52	"Stack Segment Fault",
8aba36d8	53	"General Protection",
3ccd49ca BM	54	"Page Fault",
	55	"Reserved",
	56	"x87 FPU Floating-Point Error",
	57	"Alignment Check",
	58	"Machine Check",
	59	"SIMD Floating-Point Exception",
	60	"Virtualization Exception",
	61	"Reserved",
	62	"Reserved",
	63	"Reserved",
	64	"Reserved",
	65	"Reserved",
	66	"Reserved",
	67	"Reserved",
	68	"Reserved",
	69	"Reserved",
	70	"Reserved",
	71	"Reserved"
	72	};
	73
74b76357 HS	74	/**
	75	* show_efi_loaded_images() - show loaded UEFI images
	76	*
	77	* List all loaded UEFI images.
	78	*
	79	* @eip: instruction pointer
	80	*/
	81	static void show_efi_loaded_images(uintptr_t eip)
	82	{
	83	efi_print_image_infos((void *)eip);
	84	}
	85
e1ffd817	86	static void dump_regs(struct irq_regs *regs)
433ff2bd	87	{
013cf483	88	unsigned long cs, eip, eflags;
433ff2bd GR	89	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
433ff2bd GR	90	unsigned long d0, d1, d2, d3, d6, d7;
ca56a4ce	91	unsigned long sp;
433ff2bd	92
013cf483 BM	93	/*
	94	* Some exceptions cause an error code to be saved on the current stack
	95	* after the EIP value. We should extract CS/EIP/EFLAGS from different
	96	* position on the stack based on the exception number.
	97	*/
	98	switch (regs->irq_id) {
	99	case EXC_DF:
	100	case EXC_TS:
	101	case EXC_NP:
	102	case EXC_SS:
	103	case EXC_GP:
	104	case EXC_PF:
	105	case EXC_AC:
	106	cs = regs->context.ctx2.xcs;
	107	eip = regs->context.ctx2.eip;
	108	eflags = regs->context.ctx2.eflags;
	109	/* We should fix up the ESP due to error code */
	110	regs->esp += 4;
	111	break;
	112	default:
	113	cs = regs->context.ctx1.xcs;
	114	eip = regs->context.ctx1.eip;
	115	eflags = regs->context.ctx1.eflags;
	116	break;
	117	}
	118
433ff2bd	119	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
013cf483	120	(u16)cs, eip, eflags);
7399515d SG	121	if (gd->flags & GD_FLG_RELOC)
7399515d SG	122	printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
433ff2bd GR	123
	124	printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
	125	regs->eax, regs->ebx, regs->ecx, regs->edx);
	126	printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
	127	regs->esi, regs->edi, regs->ebp, regs->esp);
	128	printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
717979fd GR	129	(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
717979fd GR	130	(u16)regs->xgs, (u16)regs->xss);
433ff2bd GR	131
	132	cr0 = read_cr0();
	133	cr2 = read_cr2();
	134	cr3 = read_cr3();
	135	cr4 = read_cr4();
	136
	137	printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
	138	cr0, cr2, cr3, cr4);
	139
	140	d0 = get_debugreg(0);
	141	d1 = get_debugreg(1);
	142	d2 = get_debugreg(2);
	143	d3 = get_debugreg(3);
	144
	145	printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
	146	d0, d1, d2, d3);
	147
	148	d6 = get_debugreg(6);
	149	d7 = get_debugreg(7);
	150	printf("DR6: %08lx DR7: %08lx\n",
	151	d6, d7);
ca56a4ce GR	152
	153	printf("Stack:\n");
	154	sp = regs->esp;
	155
	156	sp += 64;
	157
	158	while (sp > (regs->esp - 16)) {
	159	if (sp == regs->esp)
	160	printf("--->");
	161	else
	162	printf(" ");
	163	printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
	164	sp -= 4;
	165	}
74b76357	166	show_efi_loaded_images(eip);
433ff2bd GR	167	}
433ff2bd GR	168
3ccd49ca BM	169	static void do_exception(struct irq_regs *regs)
	170	{
	171	printf("%s\n", exceptions[regs->irq_id]);
	172	dump_regs(regs);
	173	hang();
	174	}
	175
2262cfee WD	176	struct idt_entry {
	177	u16 base_low;
	178	u16 selector;
	179	u8 res;
	180	u8 access;
	181	u16 base_high;
717979fd	182	} __packed;
2262cfee	183
58c7a675	184	struct idt_entry idt[256] __aligned(16);
2262cfee	185
a0ed8003	186	struct idt_ptr idt_ptr;
2262cfee	187
a0ed8003	188	static inline void load_idt(const struct idt_ptr *dtr)
564a9984	189	{
717979fd	190	asm volatile("cs lidt %0" : : "m" (*dtr));
564a9984	191	}
2262cfee	192
abf0cd3d	193	void set_vector(u8 intnum, void *routine)
2262cfee	194	{
21b3b66a SG	195	idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
21b3b66a SG	196	idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
2262cfee WD	197	}
2262cfee WD	198
717979fd GR	199	/*
	200	* Ideally these would be defined static to avoid a checkpatch warning, but
	201	* the compiler cannot see them in the inline asm and complains that they
	202	* aren't defined
	203	*/
564a9984 GR	204	void irq_0(void);
564a9984 GR	205	void irq_1(void);
2262cfee	206
abf0cd3d	207	int cpu_init_interrupts(void)
2262cfee WD	208	{
2262cfee WD	209	int i;
8bde7f77	210
564a9984 GR	211	int irq_entry_size = irq_1 - irq_0;
	212	void irq_entry = (void )irq_0;
	213
2262cfee	214	/* Setup the IDT */
717979fd	215	for (i = 0; i < 256; i++) {
2262cfee	216	idt[i].access = 0x8e;
8bde7f77	217	idt[i].res = 0;
8aba36d8	218	idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
564a9984 GR	219	set_vector(i, irq_entry);
564a9984 GR	220	irq_entry += irq_entry_size;
8bde7f77 WD	221	}
8bde7f77 WD	222
8aba36d8	223	idt_ptr.size = 256 * 8 - 1;
564a9984	224	idt_ptr.address = (unsigned long) idt;
564a9984 GR	225
564a9984 GR	226	load_idt(&idt_ptr);
8bde7f77	227
2262cfee WD	228	return 0;
	229	}
	230
a0ed8003 SG	231	void interrupt_read_idt(struct idt_ptr *ptr)
	232	{
	233	asm volatile("sidt %0" : : "m" (*ptr));
	234	}
	235
6f41e0e7 SG	236	void *x86_get_idt(void)
	237	{
	238	return &idt_ptr;
	239	}
	240
564a9984 GR	241	void __do_irq(int irq)
	242	{
	243	printf("Unhandled IRQ : %d\n", irq);
	244	}
	245	void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
	246
2262cfee WD	247	void enable_interrupts(void)
	248	{
	249	asm("sti\n");
	250	}
	251
	252	int disable_interrupts(void)
	253	{
	254	long flags;
8bde7f77	255
34722da6	256	#if CONFIG_IS_ENABLED(X86_64)
35233da9 SG	257	asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
35233da9 SG	258	#else
2262cfee	259	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
35233da9	260	#endif
717979fd	261	return flags & X86_EFLAGS_IF;
2262cfee	262	}
564a9984	263
1dae2e0e BM	264	int interrupt_init(void)
1dae2e0e BM	265	{
12d6929e SG	266	struct udevice *dev;
	267	int ret;
	268
526aabec SG	269	if (!ll_boot_init())
	270	return 0;
	271
12d6929e	272	/* Try to set up the interrupt router, but don't require one */
69c2dc93	273	ret = irq_first_device_type(X86_IRQT_BASE, &dev);
12d6929e SG	274	if (ret && ret != -ENODEV)
	275	return ret;
	276
3dcdd17b BS	277	/*
	278	* When running as an EFI application we are not in control of
	279	* interrupts and should leave them alone.
	280	*/
	281	#ifndef CONFIG_EFI_APP
1dae2e0e BM	282	/* Just in case... */
	283	disable_interrupts();
	284
da3fe247	285	#ifdef CONFIG_I8259_PIC
1dae2e0e BM	286	/* Initialize the master/slave i8259 pic */
	287	i8259_init();
	288	#endif
	289
da4cfa6b	290	#ifdef CONFIG_APIC
e2126711	291	lapic_setup();
da4cfa6b	292	#endif
e2126711	293
1dae2e0e BM	294	/* Initialize core interrupt and exception functionality of CPU */
	295	cpu_init_interrupts();
	296
e49cceac SG	297	/*
	298	* It is now safe to enable interrupts.
	299	*
	300	* TODO([email protected]): But we don't handle these correctly when
	301	* booted from EFI.
	302	*/
526aabec	303	enable_interrupts();
3dcdd17b	304	#endif
1dae2e0e BM	305
	306	return 0;
	307	}
	308
564a9984	309	/* IRQ Low-Level Service Routine */
7228efa3	310	void irq_llsr(struct irq_regs *regs)
564a9984 GR	311	{
	312	/*
	313	* For detailed description of each exception, refer to:
fa82f871	314	* Intel® 64 and IA-32 Architectures Software Developer's Manual
564a9984 GR	315	* Volume 1: Basic Architecture
	316	* Order Number: 253665-029US, November 2008
	317	* Table 6-1. Exceptions and Interrupts
	318	*/
3ccd49ca BM	319	if (regs->irq_id < 32) {
	320	/* Architecture defined exception */
	321	do_exception(regs);
	322	} else {
564a9984	323	/* Hardware or User IRQ */
7228efa3	324	do_irq(regs->irq_id);
564a9984 GR	325	}
	326	}
	327
	328	/*
	329	* OK - This looks really horrible, but it serves a purpose - It helps create
	330	* fully relocatable code.
	331	* - The call to irq_llsr will be a relative jump
	332	* - The IRQ entries will be guaranteed to be in order
433ff2bd GR	333	* Interrupt entries are now very small (a push and a jump) but they are
	334	* now slower (all registers pushed on stack which provides complete
	335	* crash dumps in the low level handlers
7228efa3 GR	336	*
	337	* Interrupt Entry Point:
	338	* - Interrupt has caused eflags, CS and EIP to be pushed
	339	* - Interrupt Vector Handler has pushed orig_eax
	340	* - pt_regs.esp needs to be adjusted by 40 bytes:
	341	* 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
	342	* 4 bytes pushed by vector handler (irq_id)
	343	* 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
	344	* NOTE: Only longs are pushed on/popped off the stack!
564a9984 GR	345	*/
564a9984 GR	346	asm(".globl irq_common_entry\n" \
0fc1b49e GR	347	".hidden irq_common_entry\n" \
0fc1b49e GR	348	".type irq_common_entry, @function\n" \
564a9984	349	"irq_common_entry:\n" \
433ff2bd	350	"cld\n" \
7228efa3	351	"pushl %ss\n" \
433ff2bd GR	352	"pushl %gs\n" \
	353	"pushl %fs\n" \
	354	"pushl %es\n" \
	355	"pushl %ds\n" \
	356	"pushl %eax\n" \
7228efa3 GR	357	"movl %esp, %eax\n" \
	358	"addl $40, %eax\n" \
	359	"pushl %eax\n" \
433ff2bd GR	360	"pushl %ebp\n" \
	361	"pushl %edi\n" \
	362	"pushl %esi\n" \
	363	"pushl %edx\n" \
	364	"pushl %ecx\n" \
	365	"pushl %ebx\n" \
	366	"mov %esp, %eax\n" \
564a9984	367	"call irq_llsr\n" \
433ff2bd GR	368	"popl %ebx\n" \
	369	"popl %ecx\n" \
	370	"popl %edx\n" \
	371	"popl %esi\n" \
	372	"popl %edi\n" \
	373	"popl %ebp\n" \
	374	"popl %eax\n" \
7228efa3	375	"popl %eax\n" \
433ff2bd GR	376	"popl %ds\n" \
	377	"popl %es\n" \
	378	"popl %fs\n" \
	379	"popl %gs\n" \
7228efa3	380	"popl %ss\n" \
433ff2bd	381	"add $4, %esp\n" \
564a9984 GR	382	"iret\n" \
	383	DECLARE_INTERRUPT(0) \
	384	DECLARE_INTERRUPT(1) \
	385	DECLARE_INTERRUPT(2) \
	386	DECLARE_INTERRUPT(3) \
	387	DECLARE_INTERRUPT(4) \
	388	DECLARE_INTERRUPT(5) \
	389	DECLARE_INTERRUPT(6) \
	390	DECLARE_INTERRUPT(7) \
	391	DECLARE_INTERRUPT(8) \
	392	DECLARE_INTERRUPT(9) \
	393	DECLARE_INTERRUPT(10) \
	394	DECLARE_INTERRUPT(11) \
	395	DECLARE_INTERRUPT(12) \
	396	DECLARE_INTERRUPT(13) \
	397	DECLARE_INTERRUPT(14) \
	398	DECLARE_INTERRUPT(15) \
	399	DECLARE_INTERRUPT(16) \
	400	DECLARE_INTERRUPT(17) \
	401	DECLARE_INTERRUPT(18) \
	402	DECLARE_INTERRUPT(19) \
	403	DECLARE_INTERRUPT(20) \
	404	DECLARE_INTERRUPT(21) \
	405	DECLARE_INTERRUPT(22) \
	406	DECLARE_INTERRUPT(23) \
	407	DECLARE_INTERRUPT(24) \
	408	DECLARE_INTERRUPT(25) \
	409	DECLARE_INTERRUPT(26) \
	410	DECLARE_INTERRUPT(27) \
	411	DECLARE_INTERRUPT(28) \
	412	DECLARE_INTERRUPT(29) \
	413	DECLARE_INTERRUPT(30) \
	414	DECLARE_INTERRUPT(31) \
	415	DECLARE_INTERRUPT(32) \
	416	DECLARE_INTERRUPT(33) \
	417	DECLARE_INTERRUPT(34) \
	418	DECLARE_INTERRUPT(35) \
	419	DECLARE_INTERRUPT(36) \
	420	DECLARE_INTERRUPT(37) \
	421	DECLARE_INTERRUPT(38) \
	422	DECLARE_INTERRUPT(39) \
	423	DECLARE_INTERRUPT(40) \
	424	DECLARE_INTERRUPT(41) \
	425	DECLARE_INTERRUPT(42) \
	426	DECLARE_INTERRUPT(43) \
	427	DECLARE_INTERRUPT(44) \
	428	DECLARE_INTERRUPT(45) \
	429	DECLARE_INTERRUPT(46) \
	430	DECLARE_INTERRUPT(47) \
	431	DECLARE_INTERRUPT(48) \
	432	DECLARE_INTERRUPT(49) \
	433	DECLARE_INTERRUPT(50) \
	434	DECLARE_INTERRUPT(51) \
	435	DECLARE_INTERRUPT(52) \
	436	DECLARE_INTERRUPT(53) \
	437	DECLARE_INTERRUPT(54) \
	438	DECLARE_INTERRUPT(55) \
	439	DECLARE_INTERRUPT(56) \
	440	DECLARE_INTERRUPT(57) \
	441	DECLARE_INTERRUPT(58) \
	442	DECLARE_INTERRUPT(59) \
	443	DECLARE_INTERRUPT(60) \
	444	DECLARE_INTERRUPT(61) \
	445	DECLARE_INTERRUPT(62) \
446	DECLARE_INTERRUPT(63) \
447	DECLARE_INTERRUPT(64) \
448	DECLARE_INTERRUPT(65) \
449	DECLARE_INTERRUPT(66) \
450	DECLARE_INTERRUPT(67) \
451	DECLARE_INTERRUPT(68) \
452	DECLARE_INTERRUPT(69) \
453	DECLARE_INTERRUPT(70) \
454	DECLARE_INTERRUPT(71) \
455	DECLARE_INTERRUPT(72) \
456	DECLARE_INTERRUPT(73) \
457	DECLARE_INTERRUPT(74) \
458	DECLARE_INTERRUPT(75) \
459	DECLARE_INTERRUPT(76) \
460	DECLARE_INTERRUPT(77) \
461	DECLARE_INTERRUPT(78) \
462	DECLARE_INTERRUPT(79) \
463	DECLARE_INTERRUPT(80) \
464	DECLARE_INTERRUPT(81) \
465	DECLARE_INTERRUPT(82) \
466	DECLARE_INTERRUPT(83) \
467	DECLARE_INTERRUPT(84) \
468	DECLARE_INTERRUPT(85) \
469	DECLARE_INTERRUPT(86) \
470	DECLARE_INTERRUPT(87) \
471	DECLARE_INTERRUPT(88) \
472	DECLARE_INTERRUPT(89) \
473	DECLARE_INTERRUPT(90) \
474	DECLARE_INTERRUPT(91) \
475	DECLARE_INTERRUPT(92) \
476	DECLARE_INTERRUPT(93) \
477	DECLARE_INTERRUPT(94) \
478	DECLARE_INTERRUPT(95) \
479	DECLARE_INTERRUPT(97) \
480	DECLARE_INTERRUPT(96) \
481	DECLARE_INTERRUPT(98) \
482	DECLARE_INTERRUPT(99) \
483	DECLARE_INTERRUPT(100) \
484	DECLARE_INTERRUPT(101) \
485	DECLARE_INTERRUPT(102) \
486	DECLARE_INTERRUPT(103) \
487	DECLARE_INTERRUPT(104) \
488	DECLARE_INTERRUPT(105) \
489	DECLARE_INTERRUPT(106) \
490	DECLARE_INTERRUPT(107) \
491	DECLARE_INTERRUPT(108) \
492	DECLARE_INTERRUPT(109) \
493	DECLARE_INTERRUPT(110) \
494	DECLARE_INTERRUPT(111) \
495	DECLARE_INTERRUPT(112) \
496	DECLARE_INTERRUPT(113) \
497	DECLARE_INTERRUPT(114) \
498	DECLARE_INTERRUPT(115) \
499	DECLARE_INTERRUPT(116) \
500	DECLARE_INTERRUPT(117) \
501	DECLARE_INTERRUPT(118) \
502	DECLARE_INTERRUPT(119) \
503	DECLARE_INTERRUPT(120) \
504	DECLARE_INTERRUPT(121) \
505	DECLARE_INTERRUPT(122) \
506	DECLARE_INTERRUPT(123) \
507	DECLARE_INTERRUPT(124) \
508	DECLARE_INTERRUPT(125) \
509	DECLARE_INTERRUPT(126) \
510	DECLARE_INTERRUPT(127) \
511	DECLARE_INTERRUPT(128) \
512	DECLARE_INTERRUPT(129) \
513	DECLARE_INTERRUPT(130) \
514	DECLARE_INTERRUPT(131) \
515	DECLARE_INTERRUPT(132) \
516	DECLARE_INTERRUPT(133) \
517	DECLARE_INTERRUPT(134) \
518	DECLARE_INTERRUPT(135) \
519	DECLARE_INTERRUPT(136) \
520	DECLARE_INTERRUPT(137) \
521	DECLARE_INTERRUPT(138) \
522	DECLARE_INTERRUPT(139) \
523	DECLARE_INTERRUPT(140) \
524	DECLARE_INTERRUPT(141) \
525	DECLARE_INTERRUPT(142) \
526	DECLARE_INTERRUPT(143) \
527	DECLARE_INTERRUPT(144) \
528	DECLARE_INTERRUPT(145) \
529	DECLARE_INTERRUPT(146) \
530	DECLARE_INTERRUPT(147) \
531	DECLARE_INTERRUPT(148) \
532	DECLARE_INTERRUPT(149) \
533	DECLARE_INTERRUPT(150) \
534	DECLARE_INTERRUPT(151) \
535	DECLARE_INTERRUPT(152) \
536	DECLARE_INTERRUPT(153) \
537	DECLARE_INTERRUPT(154) \
538	DECLARE_INTERRUPT(155) \
539	DECLARE_INTERRUPT(156) \
540	DECLARE_INTERRUPT(157) \
541	DECLARE_INTERRUPT(158) \
542	DECLARE_INTERRUPT(159) \
543	DECLARE_INTERRUPT(160) \
544	DECLARE_INTERRUPT(161) \
545	DECLARE_INTERRUPT(162) \
546	DECLARE_INTERRUPT(163) \
547	DECLARE_INTERRUPT(164) \
548	DECLARE_INTERRUPT(165) \
549	DECLARE_INTERRUPT(166) \
550	DECLARE_INTERRUPT(167) \
551	DECLARE_INTERRUPT(168) \
552	DECLARE_INTERRUPT(169) \
553	DECLARE_INTERRUPT(170) \
554	DECLARE_INTERRUPT(171) \
555	DECLARE_INTERRUPT(172) \
556	DECLARE_INTERRUPT(173) \
557	DECLARE_INTERRUPT(174) \
558	DECLARE_INTERRUPT(175) \
559	DECLARE_INTERRUPT(176) \
560	DECLARE_INTERRUPT(177) \
561	DECLARE_INTERRUPT(178) \
562	DECLARE_INTERRUPT(179) \
563	DECLARE_INTERRUPT(180) \
564	DECLARE_INTERRUPT(181) \
565	DECLARE_INTERRUPT(182) \
566	DECLARE_INTERRUPT(183) \
567	DECLARE_INTERRUPT(184) \
568	DECLARE_INTERRUPT(185) \
569	DECLARE_INTERRUPT(186) \
570	DECLARE_INTERRUPT(187) \
571	DECLARE_INTERRUPT(188) \
572	DECLARE_INTERRUPT(189) \
573	DECLARE_INTERRUPT(190) \
574	DECLARE_INTERRUPT(191) \
575	DECLARE_INTERRUPT(192) \
576	DECLARE_INTERRUPT(193) \
577	DECLARE_INTERRUPT(194) \
578	DECLARE_INTERRUPT(195) \
579	DECLARE_INTERRUPT(196) \
580	DECLARE_INTERRUPT(197) \
581	DECLARE_INTERRUPT(198) \
582	DECLARE_INTERRUPT(199) \
583	DECLARE_INTERRUPT(200) \
584	DECLARE_INTERRUPT(201) \
585	DECLARE_INTERRUPT(202) \
586	DECLARE_INTERRUPT(203) \
587	DECLARE_INTERRUPT(204) \
588	DECLARE_INTERRUPT(205) \
589	DECLARE_INTERRUPT(206) \
590	DECLARE_INTERRUPT(207) \
591	DECLARE_INTERRUPT(208) \
592	DECLARE_INTERRUPT(209) \
593	DECLARE_INTERRUPT(210) \
594	DECLARE_INTERRUPT(211) \
595	DECLARE_INTERRUPT(212) \
596	DECLARE_INTERRUPT(213) \
597	DECLARE_INTERRUPT(214) \
598	DECLARE_INTERRUPT(215) \
599	DECLARE_INTERRUPT(216) \
600	DECLARE_INTERRUPT(217) \
601	DECLARE_INTERRUPT(218) \
602	DECLARE_INTERRUPT(219) \
603	DECLARE_INTERRUPT(220) \
604	DECLARE_INTERRUPT(221) \
605	DECLARE_INTERRUPT(222) \
606	DECLARE_INTERRUPT(223) \
607	DECLARE_INTERRUPT(224) \
608	DECLARE_INTERRUPT(225) \
609	DECLARE_INTERRUPT(226) \
610	DECLARE_INTERRUPT(227) \
611	DECLARE_INTERRUPT(228) \
612	DECLARE_INTERRUPT(229) \
613	DECLARE_INTERRUPT(230) \
614	DECLARE_INTERRUPT(231) \
615	DECLARE_INTERRUPT(232) \
616	DECLARE_INTERRUPT(233) \
617	DECLARE_INTERRUPT(234) \
618	DECLARE_INTERRUPT(235) \
619	DECLARE_INTERRUPT(236) \
620	DECLARE_INTERRUPT(237) \
621	DECLARE_INTERRUPT(238) \
622	DECLARE_INTERRUPT(239) \
623	DECLARE_INTERRUPT(240) \
624	DECLARE_INTERRUPT(241) \
625	DECLARE_INTERRUPT(242) \
626	DECLARE_INTERRUPT(243) \
627	DECLARE_INTERRUPT(244) \
628	DECLARE_INTERRUPT(245) \
629	DECLARE_INTERRUPT(246) \
630	DECLARE_INTERRUPT(247) \
631	DECLARE_INTERRUPT(248) \
632	DECLARE_INTERRUPT(249) \
633	DECLARE_INTERRUPT(250) \
634	DECLARE_INTERRUPT(251) \
635	DECLARE_INTERRUPT(252) \
636	DECLARE_INTERRUPT(253) \
637	DECLARE_INTERRUPT(254) \
638	DECLARE_INTERRUPT(255));