[u-boot.git] / arch / m68k / cpu / mcf5445x / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <linux/delay.h>

#include <asm/immap.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
	udelay(1000);
	out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
	udelay(10000);
	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);

	/* we don't return! */
	return 0;
};

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	ccm_t *ccm = (ccm_t *) MMAP_CCM;
	u16 msk;
	u16 id = 0;
	u8 ver;

	puts("CPU:   ");
	msk = (in_be16(&ccm->cir) >> 6);
	ver = (in_be16(&ccm->cir) & 0x003f);
	switch (msk) {
	case 0x48:
		id = 54455;
		break;
	case 0x49:
		id = 54454;
		break;
	case 0x4a:
		id = 54453;
		break;
	case 0x4b:
		id = 54452;
		break;
	case 0x4d:
		id = 54451;
		break;
	case 0x4f:
		id = 54450;
		break;
	case 0x9F:
		id = 54410;
		break;
	case 0xA0:
		id = 54415;
		break;
	case 0xA1:
		id = 54416;
		break;
	case 0xA2:
		id = 54417;
		break;
	case 0xA3:
		id = 54418;
		break;
	}

	if (id) {
		char buf1[32], buf2[32], buf3[32];

		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
		       ver);
		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
		       strmhz(buf1, gd->cpu_clk),
		       strmhz(buf2, gd->bus_clk),
		       strmhz(buf3, gd->arch.flb_clk));
#ifdef CONFIG_PCI
		printf("       PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
		       strmhz(buf1, gd->pci_clk),
		       strmhz(buf2, gd->arch.inp_clk),
		       strmhz(buf3, gd->arch.vco_clk));
#else
		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
		       strmhz(buf1, gd->arch.inp_clk),
		       strmhz(buf2, gd->arch.vco_clk));
#endif
	}

	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers.  To override,
 * create a board-specific function called:
 * 	int board_eth_init(struct bd_info *bis)
 */

int cpu_eth_init(struct bd_info *bis)
{
	return mcffec_initialize(bis);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8ae158cd TL	2	/*
	3	*
	4	* (C) Copyright 2000-2003
	5	* Wolfgang Denk, DENX Software Engineering, [email protected].
	6	*
198cafbf	7	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
8ae158cd	8	* TsiChung Liew ([email protected])
8ae158cd TL	9	*/
	10
	11	#include <common.h>
691d719d	12	#include <init.h>
90526e9f	13	#include <net.h>
2189d5f1	14	#include <vsprintf.h>
8ae158cd TL	15	#include <watchdog.h>
8ae158cd TL	16	#include <command.h>
89973f8a	17	#include <netdev.h>
401d1c4f	18	#include <asm/global_data.h>
c05ed00a	19	#include <linux/delay.h>
8ae158cd TL	20
8ae158cd TL	21	#include <asm/immap.h>
198cafbf	22	#include <asm/io.h>
8ae158cd TL	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
09140113	26	int do_reset(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
8ae158cd	27	{
198cafbf	28	rcm_t rcm = (rcm_t ) (MMAP_RCM);
8ae158cd	29	udelay(1000);
45370e18 AW	30	out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
45370e18 AW	31	udelay(10000);
198cafbf	32	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
8ae158cd TL	33
	34	/* we don't return! */
	35	return 0;
	36	};
	37
b9153fe3 AD	38	#if defined(CONFIG_DISPLAY_CPUINFO)
b9153fe3 AD	39	int print_cpuinfo(void)
8ae158cd	40	{
198cafbf	41	ccm_t ccm = (ccm_t ) MMAP_CCM;
8ae158cd TL	42	u16 msk;
	43	u16 id = 0;
	44	u8 ver;
	45
	46	puts("CPU: ");
198cafbf AW	47	msk = (in_be16(&ccm->cir) >> 6);
198cafbf AW	48	ver = (in_be16(&ccm->cir) & 0x003f);
8ae158cd TL	49	switch (msk) {
	50	case 0x48:
	51	id = 54455;
	52	break;
	53	case 0x49:
	54	id = 54454;
	55	break;
	56	case 0x4a:
	57	id = 54453;
	58	break;
	59	case 0x4b:
	60	id = 54452;
	61	break;
	62	case 0x4d:
	63	id = 54451;
	64	break;
	65	case 0x4f:
	66	id = 54450;
	67	break;
45370e18 AW	68	case 0x9F:
	69	id = 54410;
	70	break;
	71	case 0xA0:
	72	id = 54415;
	73	break;
	74	case 0xA1:
	75	id = 54416;
	76	break;
	77	case 0xA2:
	78	id = 54417;
	79	break;
	80	case 0xA3:
	81	id = 54418;
	82	break;
8ae158cd TL	83	}
	84
	85	if (id) {
08ef89ec WD	86	char buf1[32], buf2[32], buf3[32];
08ef89ec WD	87
8ae158cd TL	88	printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
8ae158cd TL	89	ver);
08ef89ec WD	90	printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
	91	strmhz(buf1, gd->cpu_clk),
	92	strmhz(buf2, gd->bus_clk),
7e2592fd	93	strmhz(buf3, gd->arch.flb_clk));
8ae158cd	94	#ifdef CONFIG_PCI
08ef89ec WD	95	printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
08ef89ec WD	96	strmhz(buf1, gd->pci_clk),
7e2592fd SG	97	strmhz(buf2, gd->arch.inp_clk),
7e2592fd SG	98	strmhz(buf3, gd->arch.vco_clk));
8ae158cd	99	#else
08ef89ec	100	printf(" INP CLK %s MHz VCO CLK %s MHz\n",
7e2592fd SG	101	strmhz(buf1, gd->arch.inp_clk),
7e2592fd SG	102	strmhz(buf2, gd->arch.vco_clk));
8ae158cd TL	103	#endif
	104	}
	105
	106	return 0;
	107	}
b9153fe3	108	#endif /* CONFIG_DISPLAY_CPUINFO */
86882b80 BW	109
	110	#if defined(CONFIG_MCFFEC)
	111	/* Default initializations for MCFFEC controllers. To override,
	112	* create a board-specific function called:
bb5a2cf9	113	* int board_eth_init(struct bd_info *bis)
86882b80 BW	114	*/
86882b80 BW	115
b75d8dc5	116	int cpu_eth_init(struct bd_info *bis)
86882b80 BW	117	{
	118	return mcffec_initialize(bis);
	119	}
	120	#endif