[u-boot.git] / arch / arm / dts / zynqmp-m-a2197-01-revA.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal a2197 RevA System Controller
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
 * Michal Simek <[email protected]>
 */
/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Versal System Controller on a2197 Memory Char board RevA";
	compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
		     "xlnx,zynqmp-a2197", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		nvmem0 = &eeprom;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &dcc;
		usb0 = &usb0;
		usb1 = &usb1;
		spi0 = &qspi;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
	};

	ina226-vcc-aux {
		compatible = "iio-hwmon";
		io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
	};
	ina226-vcc-ram {
		compatible = "iio-hwmon";
		io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
	};
	ina226-vcc1v1-lp4 {
		compatible = "iio-hwmon";
		io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
	};
	ina226-vcc1v2-lp4 {
		compatible = "iio-hwmon";
		io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
	};
	ina226-vdd1-1v8-lp4 {
		compatible = "iio-hwmon";
		io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
	};
	ina226-vcc0v6-lp4 {
		compatible = "iio-hwmon";
		io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
	};
};

&qspi {
	status = "okay";
	num-cs = <2>;
	flash@0 {
		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
		reg = <0>, <1>;
		parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
		#address-cells = <1>;
		#size-cells = <1>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <108000000>;
	};
};

&sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
	status = "okay";
	non-removable;
	disable-wp;
	no-sd;
	no-sdio;
	cap-mmc-hw-reset;
	bus-width = <8>;
	xlnx,mio-bank = <0>; /* FIXME tap delay */
};

&uart0 { /* uart0 MIO38-39 */
	status = "okay";
};

&uart1 { /* uart1 MIO40-41 */
	status = "okay";
};

&sdhci1 { /* sd1 MIO45-51 cd in place */
	status = "disabled";
	no-1-8-v;
	disable-wp;
	xlnx,mio-bank = <1>;
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "sgmii"; /* DTG generates this properly  1512 */
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
		phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
			reg = <0>;
/*		xlnx,phy-type = <PHY_TYPE_SGMII>; */
		};
	};
};

&gpio {
	status = "okay";
	gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
		  "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
		  "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
		  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
		  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
		  "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
		  "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
		  "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
		  "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
		  "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
		  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
		  "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
		  "", "", /* 78 - 79 */
		  "", "", "", "", "", /* 80 - 84 */
		  "", "", "", "", "", /* 85 - 89 */
		  "", "", "", "", "", /* 90 - 94 */
		  "", "", "", "", "", /* 95 - 99 */
		  "", "", "", "", "", /* 100 - 104 */
		  "", "", "", "", "", /* 105 - 109 */
		  "", "", "", "", "", /* 110 - 114 */
		  "", "", "", "", "", /* 115 - 119 */
		  "", "", "", "", "", /* 120 - 124 */
		  "", "", "", "", "", /* 125 - 129 */
		  "", "", "", "", "", /* 130 - 134 */
		  "", "", "", "", "", /* 135 - 139 */
		  "", "", "", "", "", /* 140 - 144 */
		  "", "", "", "", "", /* 145 - 149 */
		  "", "", "", "", "", /* 150 - 154 */
		  "", "", "", "", "", /* 155 - 159 */
		  "", "", "", "", "", /* 160 - 164 */
		  "", "", "", "", "", /* 165 - 169 */
		  "", "", "", ""; /* 170 - 173 */
};

&i2c0 { /* MIO 34-35 - can't stay here */
	status = "okay";
	clock-frequency = <400000>;
	i2c-mux@74 { /* u46 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
		i2c@0 { /* PMBUS  must be enabled via SW21 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			reg_vcc1v2_lp4: tps544@15 { /* u97 */
				compatible = "ti,tps544b25";
				reg = <0x15>;
			};
			reg_vcc1v1_lp4: tps544@16 { /* u95 */
				compatible = "ti,tps544b25";
				reg = <0x16>;
			};
			reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
				compatible = "ti,tps544b25";
				reg = <0x17>;
			};
			/* UTIL_PMBUS connection */
			reg_vcc1v8: tps544@13 { /* u92 */
				compatible = "ti,tps544b25";
				reg = <0x13>;
			};
			reg_vcc3v3: tps544@14 { /* u93 */
				compatible = "ti,tps544b25";
				reg = <0x14>;
			};
			reg_vcc5v0: tps544@1e { /* u94 */
				compatible = "ti,tps544b25";
				reg = <0x1e>;
			};
		};
		i2c@1 { /* PMBUS_INA226 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			vcc_aux: ina226@42 { /* u86 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vcc-aux";
				reg = <0x42>;
				shunt-resistor = <5000>;
			};
			vcc_ram: ina226@43 { /* u81 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vcc-ram";
				reg = <0x43>;
				shunt-resistor = <5000>;
			};
			vcc1v1_lp4: ina226@46 { /* u96 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vcc1v1-lp4";
				reg = <0x46>;
				shunt-resistor = <5000>;
			};
			vcc1v2_lp4: ina226@47 { /* u98 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vcc1v2-lp4";
				reg = <0x47>;
				shunt-resistor = <5000>;
			};
			vdd1_1v8_lp4: ina226@48 { /* u100 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vdd1-1v8-lp4";
				reg = <0x48>;
				shunt-resistor = <5000>;
			};
			vcc0v6_lp4: ina226@49 { /* u101 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-vcc0v6-lp4";
				reg = <0x49>;
				shunt-resistor = <5000>;
			};
		};
		i2c@2 { /* PMBUS1 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			reg_vccint: tps53681@60 { /* u69 - 0xc0 */
				compatible = "ti,tps53681", "ti,tps53679";
				reg = <0x60>;
			};
			reg_vcc_pmc: tps544@7 { /* u80 */
				compatible = "ti,tps544b25";
				reg = <0x7>;
			};
			reg_vcc_ram: tps544@8 { /* u82 */
				compatible = "ti,tps544b25";
				reg = <0x8>;
			};
			reg_vcc_pslp: tps544@9 { /* u83 */
				compatible = "ti,tps544b25";
				reg = <0x9>;
			};
			reg_vcc_psfp: tps544@a { /* u84 */
				compatible = "ti,tps544b25";
				reg = <0xa>;
			};
			reg_vccaux: tps544@d { /* u85 */
				compatible = "ti,tps544b25";
				reg = <0xd>;
			};
			reg_vccaux_pmc: tps544@e { /* u87 */
				compatible = "ti,tps544b25";
				reg = <0xe>;
			};
			reg_vcco_500: tps544@f { /* u88 */
				compatible = "ti,tps544b25";
				reg = <0xf>;
			};
			reg_vcco_501: tps544@10 { /* u89 */
				compatible = "ti,tps544b25";
				reg = <0x10>;
			};
			reg_vcco_502: tps544@11 { /* u90 */
				compatible = "ti,tps544b25";
				reg = <0x11>;
			};
			reg_vcco_503: tps544@12 { /* u91 */
				compatible = "ti,tps544b25";
				reg = <0x12>;
			};
		};
		i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
		i2c@4 { /* LP_I2C_SM */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			/* connected to U20G */
		};
		/* 5-7 unused */
	};
};

/* TODO sysctrl via J239 */
/* TODO samtec J212G/H via J242 */
/* TODO teensy via U30 PCA9543A bus 1 */
&i2c1 { /* i2c1 MIO 36-37 */
	status = "okay";
	clock-frequency = <400000>;

	/* Must be enabled via J242 */
	eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
		compatible = "atmel,24c02";
		reg = <0x51>;
	};

	i2c-mux@74 { /* u47 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
		dc_i2c: i2c@0 { /* DC_I2C */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* Use for storing information about SC board */
			eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
				compatible = "atmel,24c08";
				reg = <0x54>;
			};
			si570_ref_clk: clock-generator@5d { /* u26 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>; /* FIXME addr */
				temperature-stability = <50>;
				factory-fout = <33333333>;
				clock-frequency = <33333333>;
				clock-output-names = "REF_CLK"; /* FIXME */
				silabs,skip-recall;
			};
			/* Connection via Samtec U20D */
			/* Use for storing information about X-PRC card */
			x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
				compatible = "atmel,24c02";
				reg = <0x52>;
			};

			/* Use for setting up certain features on X-PRC card */
			x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
				compatible = "nxp,pca9534";
				reg = <0x22>;
				gpio-controller; /* IRQ not connected */
				#gpio-cells = <2>;
				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
						  "", "", "", "";
				gtr-sel0-hog {
					gpio-hog;
					gpios = <0 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_1";
				};
				gtr-sel1-hog {
					gpio-hog;
					gpios = <1 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_2";
				};
				gtr-sel2-hog {
					gpio-hog;
					gpios = <2 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_3";
				};
				gtr-sel3-hog {
					gpio-hog;
					gpios = <3 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_4";
				};
			};
		};
		i2c@2 { /* C0_LP4 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			si570_c0_lp4: clock-generator@55 { /* u10 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x55>;
				temperature-stability = <50>;
				factory-fout = <30000000>;
				clock-frequency = <30000000>;
				clock-output-names = "C0_LP4_SI570_CLK";
			};
		};
		i2c@3 { /* C1_LP4 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			si570_c1_lp4: clock-generator@5d { /* u10 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>; /* FIXME addr */
				temperature-stability = <50>;
				factory-fout = <30000000>;
				clock-frequency = <30000000>;
				clock-output-names = "C1_LP4_SI570_CLK";
			};
		};
		i2c@4 { /* C2_LP4 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			si570_c2_lp4: clock-generator@55 { /* u10 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x55>;
				temperature-stability = <50>;
				factory-fout = <30000000>;
				clock-frequency = <30000000>;
				clock-output-names = "C2_LP4_SI570_CLK";
			};
		};
		i2c@5 { /* C3_LP4 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			si570_c3_lp4: clock-generator@55 { /* u15 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x55>;
				temperature-stability = <50>;
				factory-fout = <30000000>;
				clock-frequency = <30000000>;
				clock-output-names = "C3_LP4_SI570_CLK";
			};
		};
		i2c@6 { /* HSDP_SI570 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			si570_hsdp: clock-generator@5d { /* u19 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>; /* FIXME addr */
				temperature-stability = <50>;
				factory-fout = <156250000>;
				clock-frequency = <156250000>;
				clock-output-names = "HSDP_SI570";
			};
		};
	};
};

&usb0 {
	status = "okay";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	/* dr_mode = "peripheral"; */
	maximum-speed = "high-speed";
};

&usb1 {
	status = "disabled"; /* not at mem board */
};

&dwc3_1 {
	/delete-property/ phy-names ;
	/delete-property/ phys ;
	maximum-speed = "high-speed";
	snps,dis_u2_susphy_quirk ;
	snps,dis_u3_susphy_quirk ;
	status = "disabled";
};
Commit	Line	Data
64eb13bf MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* dts file for Xilinx Versal a2197 RevA System Controller
	4	*
	5	* (C) Copyright 2019, Xilinx, Inc.
	6	*
174d7284	7	* Michal Simek <[email protected]>
64eb13bf MS	8	*/
	9	/dts-v1/;
	10
	11	#include "zynqmp.dtsi"
	12	#include "zynqmp-clk-ccf.dtsi"
	13	#include <dt-bindings/gpio/gpio.h>
	14
	15	/ {
	16	model = "Versal System Controller on a2197 Memory Char board RevA";
50d92833	17	compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
64eb13bf MS	18	"xlnx,zynqmp-a2197", "xlnx,zynqmp";
	19
	20	aliases {
	21	ethernet0 = &gem0;
64eb13bf MS	22	i2c0 = &i2c0;
	23	i2c1 = &i2c1;
	24	mmc0 = &sdhci0;
	25	mmc1 = &sdhci1;
531abcb7	26	nvmem0 = &eeprom;
64eb13bf MS	27	rtc0 = &rtc;
	28	serial0 = &uart0;
	29	serial1 = &uart1;
	30	serial2 = &dcc;
	31	usb0 = &usb0;
	32	usb1 = &usb1;
	33	spi0 = &qspi;
	34	};
	35
	36	chosen {
	37	bootargs = "earlycon";
	38	stdout-path = "serial0:115200n8";
64eb13bf MS	39	};
	40
	41	memory@0 {
	42	device_type = "memory";
	43	reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
	44	};
eaf96b1e MS	45
	46	ina226-vcc-aux {
	47	compatible = "iio-hwmon";
	48	io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
	49	};
	50	ina226-vcc-ram {
	51	compatible = "iio-hwmon";
	52	io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
	53	};
	54	ina226-vcc1v1-lp4 {
	55	compatible = "iio-hwmon";
	56	io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
	57	};
	58	ina226-vcc1v2-lp4 {
	59	compatible = "iio-hwmon";
	60	io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
	61	};
	62	ina226-vdd1-1v8-lp4 {
	63	compatible = "iio-hwmon";
	64	io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
	65	};
	66	ina226-vcc0v6-lp4 {
	67	compatible = "iio-hwmon";
	68	io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
	69	};
64eb13bf MS	70	};
	71
	72	&qspi {
	73	status = "okay";
0d3399df	74	num-cs = <2>;
64eb13bf	75	flash@0 {
b954e889	76	compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
0d3399df MS	77	reg = <0>, <1>;
0d3399df MS	78	parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
64eb13bf MS	79	#address-cells = <1>;
64eb13bf MS	80	#size-cells = <1>;
6e38e2ea	81	spi-tx-bus-width = <4>;
64eb13bf MS	82	spi-rx-bus-width = <4>;
	83	spi-max-frequency = <108000000>;
	84	};
	85	};
	86
	87	&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
	88	status = "okay";
	89	non-removable;
	90	disable-wp;
20136d13 PA	91	no-sd;
	92	no-sdio;
	93	cap-mmc-hw-reset;
64eb13bf	94	bus-width = <8>;
01a6da16	95	xlnx,mio-bank = <0>; /* FIXME tap delay */
64eb13bf MS	96	};
	97
	98	&uart0 { /* uart0 MIO38-39 */
	99	status = "okay";
64eb13bf MS	100	};
	101
	102	&uart1 { /* uart1 MIO40-41 */
	103	status = "okay";
64eb13bf MS	104	};
	105
	106	&sdhci1 { /* sd1 MIO45-51 cd in place */
2455af4c	107	status = "disabled";
64eb13bf MS	108	no-1-8-v;
64eb13bf MS	109	disable-wp;
01a6da16	110	xlnx,mio-bank = <1>;
64eb13bf MS	111	};
	112
	113	&gem0 {
	114	status = "okay";
	115	phy-handle = <&phy0>;
	116	phy-mode = "sgmii"; /* DTG generates this properly 1512 */
5c214bac MS	117	mdio: mdio {
	118	#address-cells = <1>;
	119	#size-cells = <0>;
	120	reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
	121	phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
	122	reg = <0>;
64eb13bf	123	/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
5c214bac	124	};
64eb13bf	125	};
64eb13bf MS	126	};
	127
	128	&gpio {
	129	status = "okay";
	130	gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
	131	"N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
	132	"SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
	133	"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
	134	"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
	135	"", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
	136	"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
	137	"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
	138	"UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
	139	"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
	140	"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
	141	"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
	142	"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
	143	"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
	144	"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
	145	"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
b065b283	146	"", "", /* 78 - 79 */
64eb13bf	147	"", "", "", "", "", /* 80 - 84 */
70642df6	148	"", "", "", "", "", /* 85 - 89 */
64eb13bf MS	149	"", "", "", "", "", /* 90 - 94 */
	150	"", "", "", "", "", /* 95 - 99 */
	151	"", "", "", "", "", /* 100 - 104 */
	152	"", "", "", "", "", /* 105 - 109 */
	153	"", "", "", "", "", /* 110 - 114 */
	154	"", "", "", "", "", /* 115 - 119 */
	155	"", "", "", "", "", /* 120 - 124 */
	156	"", "", "", "", "", /* 125 - 129 */
	157	"", "", "", "", "", /* 130 - 134 */
	158	"", "", "", "", "", /* 135 - 139 */
	159	"", "", "", "", "", /* 140 - 144 */
	160	"", "", "", "", "", /* 145 - 149 */
	161	"", "", "", "", "", /* 150 - 154 */
	162	"", "", "", "", "", /* 155 - 159 */
	163	"", "", "", "", "", /* 160 - 164 */
	164	"", "", "", "", "", /* 165 - 169 */
369d04d6	165	"", "", "", ""; /* 170 - 173 */
64eb13bf MS	166	};
	167
	168	&i2c0 { /* MIO 34-35 - can't stay here */
	169	status = "okay";
	170	clock-frequency = <400000>;
	171	i2c-mux@74 { /* u46 */
	172	compatible = "nxp,pca9548";
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	reg = <0x74>;
	176	/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
	177	i2c@0 { /* PMBUS must be enabled via SW21 */
	178	#address-cells = <1>;
	179	#size-cells = <0>;
	180	reg = <0>;
	181	reg_vcc1v2_lp4: tps544@15 { /* u97 */
	182	compatible = "ti,tps544b25";
	183	reg = <0x15>;
	184	};
	185	reg_vcc1v1_lp4: tps544@16 { /* u95 */
	186	compatible = "ti,tps544b25";
	187	reg = <0x16>;
	188	};
	189	reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
	190	compatible = "ti,tps544b25";
	191	reg = <0x17>;
	192	};
	193	/* UTIL_PMBUS connection */
	194	reg_vcc1v8: tps544@13 { /* u92 */
	195	compatible = "ti,tps544b25";
	196	reg = <0x13>;
	197	};
	198	reg_vcc3v3: tps544@14 { /* u93 */
	199	compatible = "ti,tps544b25";
	200	reg = <0x14>;
	201	};
	202	reg_vcc5v0: tps544@1e { /* u94 */
	203	compatible = "ti,tps544b25";
	204	reg = <0x1e>;
	205	};
	206	};
	207	i2c@1 { /* PMBUS_INA226 */
	208	#address-cells = <1>;
	209	#size-cells = <0>;
	210	reg = <1>;
	211	vcc_aux: ina226@42 { /* u86 */
	212	compatible = "ti,ina226";
eaf96b1e	213	#io-channel-cells = <1>;
33aaa093	214	label = "ina226-vcc-aux";
64eb13bf MS	215	reg = <0x42>;
	216	shunt-resistor = <5000>;
	217	};
	218	vcc_ram: ina226@43 { /* u81 */
	219	compatible = "ti,ina226";
eaf96b1e	220	#io-channel-cells = <1>;
33aaa093	221	label = "ina226-vcc-ram";
64eb13bf MS	222	reg = <0x43>;
	223	shunt-resistor = <5000>;
	224	};
	225	vcc1v1_lp4: ina226@46 { /* u96 */
	226	compatible = "ti,ina226";
eaf96b1e	227	#io-channel-cells = <1>;
33aaa093	228	label = "ina226-vcc1v1-lp4";
64eb13bf MS	229	reg = <0x46>;
	230	shunt-resistor = <5000>;
	231	};
	232	vcc1v2_lp4: ina226@47 { /* u98 */
	233	compatible = "ti,ina226";
eaf96b1e	234	#io-channel-cells = <1>;
33aaa093	235	label = "ina226-vcc1v2-lp4";
64eb13bf MS	236	reg = <0x47>;
	237	shunt-resistor = <5000>;
	238	};
	239	vdd1_1v8_lp4: ina226@48 { /* u100 */
	240	compatible = "ti,ina226";
eaf96b1e	241	#io-channel-cells = <1>;
33aaa093	242	label = "ina226-vdd1-1v8-lp4";
64eb13bf MS	243	reg = <0x48>;
	244	shunt-resistor = <5000>;
	245	};
	246	vcc0v6_lp4: ina226@49 { /* u101 */
	247	compatible = "ti,ina226";
eaf96b1e	248	#io-channel-cells = <1>;
33aaa093	249	label = "ina226-vcc0v6-lp4";
64eb13bf MS	250	reg = <0x49>;
	251	shunt-resistor = <5000>;
	252	};
	253	};
	254	i2c@2 { /* PMBUS1 */
	255	#address-cells = <1>;
	256	#size-cells = <0>;
	257	reg = <2>;
5f5979f4	258	reg_vccint: tps53681@60 { /* u69 - 0xc0 */
ebb28f2d	259	compatible = "ti,tps53681", "ti,tps53679";
5f5979f4	260	reg = <0x60>;
64eb13bf MS	261	};
	262	reg_vcc_pmc: tps544@7 { /* u80 */
	263	compatible = "ti,tps544b25";
	264	reg = <0x7>;
	265	};
	266	reg_vcc_ram: tps544@8 { /* u82 */
	267	compatible = "ti,tps544b25";
	268	reg = <0x8>;
	269	};
	270	reg_vcc_pslp: tps544@9 { /* u83 */
	271	compatible = "ti,tps544b25";
	272	reg = <0x9>;
	273	};
	274	reg_vcc_psfp: tps544@a { /* u84 */
	275	compatible = "ti,tps544b25";
	276	reg = <0xa>;
	277	};
	278	reg_vccaux: tps544@d { /* u85 */
	279	compatible = "ti,tps544b25";
	280	reg = <0xd>;
	281	};
	282	reg_vccaux_pmc: tps544@e { /* u87 */
	283	compatible = "ti,tps544b25";
	284	reg = <0xe>;
	285	};
	286	reg_vcco_500: tps544@f { /* u88 */
	287	compatible = "ti,tps544b25";
	288	reg = <0xf>;
	289	};
	290	reg_vcco_501: tps544@10 { /* u89 */
	291	compatible = "ti,tps544b25";
	292	reg = <0x10>;
	293	};
	294	reg_vcco_502: tps544@11 { /* u90 */
	295	compatible = "ti,tps544b25";
	296	reg = <0x11>;
	297	};
	298	reg_vcco_503: tps544@12 { /* u91 */
	299	compatible = "ti,tps544b25";
	300	reg = <0x12>;
	301	};
	302	};
	303	i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
	304	#address-cells = <1>;
	305	#size-cells = <0>;
50e84a7e	306	reg = <3>;
64eb13bf MS	307	};
	308	i2c@4 { /* LP_I2C_SM */
	309	#address-cells = <1>;
	310	#size-cells = <0>;
	311	reg = <4>;
	312	/* connected to U20G */
	313	};
	314	/* 5-7 unused */
	315	};
	316	};
	317
	318	/* TODO sysctrl via J239 */
	319	/* TODO samtec J212G/H via J242 */
	320	/* TODO teensy via U30 PCA9543A bus 1 */
	321	&i2c1 { /* i2c1 MIO 36-37 */
	322	status = "okay";
	323	clock-frequency = <400000>;
	324
	325	/* Must be enabled via J242 */
	326	eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
	327	compatible = "atmel,24c02";
	328	reg = <0x51>;
	329	};
	330
2703d4b4	331	i2c-mux@74 { /* u47 */
64eb13bf MS	332	compatible = "nxp,pca9548";
	333	#address-cells = <1>;
	334	#size-cells = <0>;
	335	reg = <0x74>;
	336	/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
	337	dc_i2c: i2c@0 { /* DC_I2C */
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	reg = <0>;
	341	/* Use for storing information about SC board */
	342	eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
	343	compatible = "atmel,24c08";
	344	reg = <0x54>;
	345	};
	346	si570_ref_clk: clock-generator@5d { /* u26 */
	347	#clock-cells = <0>;
	348	compatible = "silabs,si570";
	349	reg = <0x5d>; /* FIXME addr */
	350	temperature-stability = <50>;
a34a12fa	351	factory-fout = <33333333>;
64eb13bf MS	352	clock-frequency = <33333333>;
64eb13bf MS	353	clock-output-names = "REF_CLK"; /* FIXME */
a34a12fa	354	silabs,skip-recall;
64eb13bf MS	355	};
	356	/* Connection via Samtec U20D */
	357	/* Use for storing information about X-PRC card */
	358	x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
	359	compatible = "atmel,24c02";
	360	reg = <0x52>;
	361	};
	362
	363	/* Use for setting up certain features on X-PRC card */
	364	x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
	365	compatible = "nxp,pca9534";
	366	reg = <0x22>;
	367	gpio-controller; /* IRQ not connected */
	368	#gpio-cells = <2>;
	369	gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
	370	"", "", "", "";
57c2a636	371	gtr-sel0-hog {
64eb13bf MS	372	gpio-hog;
	373	gpios = <0 0>;
	374	input; /* FIXME add meaning */
	375	line-name = "sw4_1";
	376	};
57c2a636	377	gtr-sel1-hog {
64eb13bf MS	378	gpio-hog;
	379	gpios = <1 0>;
	380	input; /* FIXME add meaning */
	381	line-name = "sw4_2";
	382	};
57c2a636	383	gtr-sel2-hog {
64eb13bf MS	384	gpio-hog;
	385	gpios = <2 0>;
	386	input; /* FIXME add meaning */
	387	line-name = "sw4_3";
	388	};
57c2a636	389	gtr-sel3-hog {
64eb13bf MS	390	gpio-hog;
	391	gpios = <3 0>;
	392	input; /* FIXME add meaning */
	393	line-name = "sw4_4";
	394	};
	395	};
	396	};
64eb13bf MS	397	i2c@2 { /* C0_LP4 */
	398	#address-cells = <1>;
	399	#size-cells = <0>;
	400	reg = <2>;
2703d4b4	401	si570_c0_lp4: clock-generator@55 { /* u10 */
64eb13bf MS	402	#clock-cells = <0>;
64eb13bf MS	403	compatible = "silabs,si570";
2703d4b4	404	reg = <0x55>;
64eb13bf MS	405	temperature-stability = <50>;
	406	factory-fout = <30000000>;
	407	clock-frequency = <30000000>;
	408	clock-output-names = "C0_LP4_SI570_CLK";
	409	};
	410	};
	411	i2c@3 { /* C1_LP4 */
	412	#address-cells = <1>;
	413	#size-cells = <0>;
	414	reg = <3>;
	415	si570_c1_lp4: clock-generator@5d { /* u10 */
	416	#clock-cells = <0>;
	417	compatible = "silabs,si570";
	418	reg = <0x5d>; /* FIXME addr */
	419	temperature-stability = <50>;
	420	factory-fout = <30000000>;
	421	clock-frequency = <30000000>;
	422	clock-output-names = "C1_LP4_SI570_CLK";
	423	};
	424	};
	425	i2c@4 { /* C2_LP4 */
	426	#address-cells = <1>;
	427	#size-cells = <0>;
	428	reg = <4>;
2703d4b4	429	si570_c2_lp4: clock-generator@55 { /* u10 */
64eb13bf MS	430	#clock-cells = <0>;
64eb13bf MS	431	compatible = "silabs,si570";
2703d4b4	432	reg = <0x55>;
64eb13bf MS	433	temperature-stability = <50>;
	434	factory-fout = <30000000>;
	435	clock-frequency = <30000000>;
	436	clock-output-names = "C2_LP4_SI570_CLK";
	437	};
	438	};
	439	i2c@5 { /* C3_LP4 */
	440	#address-cells = <1>;
	441	#size-cells = <0>;
	442	reg = <5>;
2703d4b4	443	si570_c3_lp4: clock-generator@55 { /* u15 */
64eb13bf MS	444	#clock-cells = <0>;
64eb13bf MS	445	compatible = "silabs,si570";
2703d4b4	446	reg = <0x55>;
64eb13bf MS	447	temperature-stability = <50>;
	448	factory-fout = <30000000>;
	449	clock-frequency = <30000000>;
	450	clock-output-names = "C3_LP4_SI570_CLK";
	451	};
	452	};
	453	i2c@6 { /* HSDP_SI570 */
	454	#address-cells = <1>;
	455	#size-cells = <0>;
	456	reg = <6>;
	457	si570_hsdp: clock-generator@5d { /* u19 */
	458	#clock-cells = <0>;
	459	compatible = "silabs,si570";
	460	reg = <0x5d>; /* FIXME addr */
	461	temperature-stability = <50>;
2703d4b4 MS	462	factory-fout = <156250000>;
2703d4b4 MS	463	clock-frequency = <156250000>;
64eb13bf MS	464	clock-output-names = "HSDP_SI570";
	465	};
	466	};
	467	};
	468	};
	469
	470	&usb0 {
	471	status = "okay";
64eb13bf MS	472	};
	473
	474	&dwc3_0 {
	475	status = "okay";
	476	dr_mode = "host";
	477	/* dr_mode = "peripheral"; */
	478	maximum-speed = "high-speed";
	479	};
	480
	481	&usb1 {
	482	status = "disabled"; /* not at mem board */
64eb13bf MS	483	};
	484
	485	&dwc3_1 {
	486	/delete-property/ phy-names ;
	487	/delete-property/ phys ;
	488	maximum-speed = "high-speed";
	489	snps,dis_u2_susphy_quirk ;
	490	snps,dis_u3_susphy_quirk ;
	491	status = "disabled";
	492	};