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Merge tag 'xilinx-for-v2025.01-rc1-v2' of https://source.denx.de/u-boot/custodians...
[u-boot.git] / arch / arm / dts / k3-am65-main.dtsi
CommitLineData
ea8ad1d9
LV		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
e4978763 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
ea8ad1d9 6 */
476e9914 7#include <dt-bindings/phy/phy-am654-serdes.h>
476e9914 8
ea8ad1d9 9&cbass_main {
e4978763
LV		 10 msmc_ram: sram@70000000 {
11 compatible = "mmio-sram";
12 reg = <0x0 0x70000000 0x0 0x200000>;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
16
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
19 };
20
21 sysfw-sram@f0000 {
22 reg = <0xf0000 0x10000>;
23 };
24
25 l3cache-sram@100000 {
26 reg = <0x100000 0x100000>;
27 };
28 };
29
ea8ad1d9
LV		 30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
2d0eba3a
LV		 32 #address-cells = <2>;
33 #size-cells = <2>;
ea8ad1d9
LV		 34 ranges;
35 #interrupt-cells = <3>;
36 interrupt-controller;
2d0eba3a 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
4dbdc847
BB		 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
ea8ad1d9
LV		 42 /*
43 * vcpumntirq:
44 * virtual CPU interface maintenance interrupt
45 */
46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
47
e4978763 48 gic_its: msi-controller@1820000 {
ea8ad1d9 49 compatible = "arm,gic-v3-its";
2d0eba3a 50 reg = <0x00 0x01820000 0x00 0x10000>;
e4978763 51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
ea8ad1d9
LV		 52 msi-controller;
53 #msi-cells = <1>;
54 };
55 };
2d0eba3a 56
e4978763
LV		 57 serdes0: serdes@900000 {
58 compatible = "ti,phy-am654-serdes";
59 reg = <0x0 0x900000 0x0 0x2000>;
60 reg-names = "serdes";
61 #phy-cells = <2>;
62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
67 ti,serdes-clk = <&serdes0_clk>;
68 #clock-cells = <1>;
69 mux-controls = <&serdes_mux 0>;
70 };
71
72 serdes1: serdes@910000 {
73 compatible = "ti,phy-am654-serdes";
74 reg = <0x0 0x910000 0x0 0x2000>;
75 reg-names = "serdes";
76 #phy-cells = <2>;
77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
82 ti,serdes-clk = <&serdes1_clk>;
83 #clock-cells = <1>;
84 mux-controls = <&serdes_mux 1>;
2d0eba3a
LV		 85 };
86
87 main_uart0: serial@2800000 {
88 compatible = "ti,am654-uart";
89 reg = <0x00 0x02800000 0x00 0x100>;
2d0eba3a
LV		 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
91 clock-frequency = <48000000>;
92 current-speed = <115200>;
e4978763 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 94 status = "disabled";
2d0eba3a
LV		 95 };
96
97 main_uart1: serial@2810000 {
98 compatible = "ti,am654-uart";
99 reg = <0x00 0x02810000 0x00 0x100>;
2d0eba3a
LV		 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
101 clock-frequency = <48000000>;
e4978763 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 103 status = "disabled";
2d0eba3a
LV		 104 };
105
106 main_uart2: serial@2820000 {
107 compatible = "ti,am654-uart";
108 reg = <0x00 0x02820000 0x00 0x100>;
2d0eba3a
LV		 109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
110 clock-frequency = <48000000>;
e4978763 111 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 112 status = "disabled";
e4978763
LV		 113 };
114
115 crypto: crypto@4e00000 {
116 compatible = "ti,am654-sa2ul";
117 reg = <0x0 0x4e00000 0x0 0x1200>;
4dbdc847 118 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
e4978763
LV		 119 #address-cells = <2>;
120 #size-cells = <2>;
121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
122
4dbdc847
BB		 123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
124 <&main_udmap 0x4003>;
e4978763 125 dma-names = "tx", "rx1", "rx2";
e4978763
LV		 126
127 rng: rng@4e10000 {
128 compatible = "inside-secure,safexcel-eip76";
129 reg = <0x0 0x4e10000 0x0 0x7d>;
130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4dbdc847 131 status = "disabled"; /* Used by OP-TEE */
e4978763 132 };
2d0eba3a 133 };
3a1a0dfc 134
4dbdc847
BB		 135 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
136 main_timerio_input: pinctrl@104200 {
137 compatible = "pinctrl-single";
138 reg = <0x0 0x104200 0x0 0x30>;
139 #pinctrl-cells = <1>;
140 pinctrl-single,register-width = <32>;
141 pinctrl-single,function-mask = <0x0000001ff>;
142 };
143
144 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
145 main_timerio_output: pinctrl@104280 {
146 compatible = "pinctrl-single";
147 reg = <0x0 0x104280 0x0 0x20>;
148 #pinctrl-cells = <1>;
149 pinctrl-single,register-width = <32>;
150 pinctrl-single,function-mask = <0x0000000f>;
151 };
152
e4978763 153 main_pmx0: pinctrl@11c000 {
3a1a0dfc
FA		 154 compatible = "pinctrl-single";
155 reg = <0x0 0x11c000 0x0 0x2e4>;
156 #pinctrl-cells = <1>;
157 pinctrl-single,register-width = <32>;
158 pinctrl-single,function-mask = <0xffffffff>;
159 };
160
e4978763 161 main_pmx1: pinctrl@11c2e8 {
9bbdfdf2
AD		 162 compatible = "pinctrl-single";
163 reg = <0x0 0x11c2e8 0x0 0x24>;
164 #pinctrl-cells = <1>;
165 pinctrl-single,register-width = <32>;
166 pinctrl-single,function-mask = <0xffffffff>;
167 };
168
e4978763
LV		 169 main_i2c0: i2c@2000000 {
170 compatible = "ti,am654-i2c", "ti,omap4-i2c";
171 reg = <0x0 0x2000000 0x0 0x100>;
172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-names = "fck";
176 clocks = <&k3_clks 110 1>;
177 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 178 status = "disabled";
e4978763
LV		 179 };
180
181 main_i2c1: i2c@2010000 {
182 compatible = "ti,am654-i2c", "ti,omap4-i2c";
183 reg = <0x0 0x2010000 0x0 0x100>;
184 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 clock-names = "fck";
188 clocks = <&k3_clks 111 1>;
189 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 190 status = "disabled";
e4978763
LV		 191 };
192
193 main_i2c2: i2c@2020000 {
194 compatible = "ti,am654-i2c", "ti,omap4-i2c";
195 reg = <0x0 0x2020000 0x0 0x100>;
196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 clock-names = "fck";
200 clocks = <&k3_clks 112 1>;
201 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 202 status = "disabled";
e4978763
LV		 203 };
204
205 main_i2c3: i2c@2030000 {
206 compatible = "ti,am654-i2c", "ti,omap4-i2c";
207 reg = <0x0 0x2030000 0x0 0x100>;
208 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clock-names = "fck";
212 clocks = <&k3_clks 113 1>;
213 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 214 status = "disabled";
e4978763
LV		 215 };
216
217 ecap0: pwm@3100000 {
218 compatible = "ti,am654-ecap", "ti,am3352-ecap";
219 #pwm-cells = <3>;
220 reg = <0x0 0x03100000 0x0 0x60>;
221 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
222 clocks = <&k3_clks 39 0>;
223 clock-names = "fck";
4dbdc847 224 status = "disabled";
e4978763
LV		 225 };
226
227 main_spi0: spi@2100000 {
228 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
229 reg = <0x0 0x2100000 0x0 0x400>;
230 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&k3_clks 137 1>;
232 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
236 dma-names = "tx0", "rx0";
4dbdc847 237 status = "disabled";
e4978763
LV		 238 };
239
240 main_spi1: spi@2110000 {
241 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
242 reg = <0x0 0x2110000 0x0 0x400>;
243 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&k3_clks 138 1>;
245 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 assigned-clocks = <&k3_clks 137 1>;
249 assigned-clock-rates = <48000000>;
4dbdc847 250 status = "disabled";
e4978763
LV		 251 };
252
253 main_spi2: spi@2120000 {
254 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
255 reg = <0x0 0x2120000 0x0 0x400>;
256 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&k3_clks 139 1>;
258 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
259 #address-cells = <1>;
260 #size-cells = <0>;
4dbdc847 261 status = "disabled";
e4978763
LV		 262 };
263
264 main_spi3: spi@2130000 {
265 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
266 reg = <0x0 0x2130000 0x0 0x400>;
267 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&k3_clks 140 1>;
269 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
270 #address-cells = <1>;
271 #size-cells = <0>;
4dbdc847 272 status = "disabled";
e4978763
LV		 273 };
274
275 main_spi4: spi@2140000 {
276 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
277 reg = <0x0 0x2140000 0x0 0x400>;
278 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&k3_clks 141 1>;
280 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
281 #address-cells = <1>;
282 #size-cells = <0>;
4dbdc847
BB		 283 status = "disabled";
284 };
285
286 main_timer0: timer@2400000 {
287 compatible = "ti,am654-timer";
288 reg = <0x00 0x2400000 0x00 0x400>;
289 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&k3_clks 23 0>;
291 clock-names = "fck";
292 assigned-clocks = <&k3_clks 23 0>;
293 assigned-clock-parents = <&k3_clks 23 1>;
294 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
295 ti,timer-pwm;
296 };
297
298 main_timer1: timer@2410000 {
299 compatible = "ti,am654-timer";
300 reg = <0x00 0x2410000 0x00 0x400>;
301 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&k3_clks 24 0>;
303 clock-names = "fck";
304 assigned-clocks = <&k3_clks 24 0>;
305 assigned-clock-parents = <&k3_clks 24 1>;
306 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
307 ti,timer-pwm;
308 };
309
310 main_timer2: timer@2420000 {
311 compatible = "ti,am654-timer";
312 reg = <0x00 0x2420000 0x00 0x400>;
313 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&k3_clks 27 0>;
315 clock-names = "fck";
316 assigned-clocks = <&k3_clks 27 0>;
317 assigned-clock-parents = <&k3_clks 27 1>;
318 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
319 ti,timer-pwm;
320 };
321
322 main_timer3: timer@2430000 {
323 compatible = "ti,am654-timer";
324 reg = <0x00 0x2430000 0x00 0x400>;
325 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&k3_clks 28 0>;
327 clock-names = "fck";
328 assigned-clocks = <&k3_clks 28 0>;
329 assigned-clock-parents = <&k3_clks 28 1>;
330 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
331 ti,timer-pwm;
332 };
333
334 main_timer4: timer@2440000 {
335 compatible = "ti,am654-timer";
336 reg = <0x00 0x2440000 0x00 0x400>;
337 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&k3_clks 29 0>;
339 clock-names = "fck";
340 assigned-clocks = <&k3_clks 29 0>;
341 assigned-clock-parents = <&k3_clks 29 1>;
342 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
343 ti,timer-pwm;
344 };
345
346 main_timer5: timer@2450000 {
347 compatible = "ti,am654-timer";
348 reg = <0x00 0x2450000 0x00 0x400>;
349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&k3_clks 30 0>;
351 clock-names = "fck";
352 assigned-clocks = <&k3_clks 30 0>;
353 assigned-clock-parents = <&k3_clks 30 1>;
354 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
355 ti,timer-pwm;
356 };
357
358 main_timer6: timer@2460000 {
359 compatible = "ti,am654-timer";
360 reg = <0x00 0x2460000 0x00 0x400>;
361 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&k3_clks 31 0>;
363 assigned-clocks = <&k3_clks 31 0>;
364 assigned-clock-parents = <&k3_clks 31 1>;
365 clock-names = "fck";
366 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
367 ti,timer-pwm;
368 };
369
370 main_timer7: timer@2470000 {
371 compatible = "ti,am654-timer";
372 reg = <0x00 0x2470000 0x00 0x400>;
373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&k3_clks 32 0>;
375 clock-names = "fck";
376 assigned-clocks = <&k3_clks 32 0>;
377 assigned-clock-parents = <&k3_clks 32 1>;
378 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
379 ti,timer-pwm;
380 };
381
382 main_timer8: timer@2480000 {
383 compatible = "ti,am654-timer";
384 reg = <0x00 0x2480000 0x00 0x400>;
385 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&k3_clks 33 0>;
387 clock-names = "fck";
388 assigned-clocks = <&k3_clks 33 0>;
389 assigned-clock-parents = <&k3_clks 33 1>;
390 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
391 ti,timer-pwm;
392 };
393
394 main_timer9: timer@2490000 {
395 compatible = "ti,am654-timer";
396 reg = <0x00 0x2490000 0x00 0x400>;
397 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&k3_clks 34 0>;
399 clock-names = "fck";
400 assigned-clocks = <&k3_clks 34 0>;
401 assigned-clock-parents = <&k3_clks 34 1>;
402 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
403 ti,timer-pwm;
404 };
405
406 main_timer10: timer@24a0000 {
407 compatible = "ti,am654-timer";
408 reg = <0x00 0x24a0000 0x00 0x400>;
409 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&k3_clks 25 0>;
411 clock-names = "fck";
412 assigned-clocks = <&k3_clks 25 0>;
413 assigned-clock-parents = <&k3_clks 25 1>;
414 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
415 ti,timer-pwm;
416 };
417
418 main_timer11: timer@24b0000 {
419 compatible = "ti,am654-timer";
420 reg = <0x00 0x24b0000 0x00 0x400>;
421 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&k3_clks 26 0>;
423 clock-names = "fck";
424 assigned-clocks = <&k3_clks 26 0>;
425 assigned-clock-parents = <&k3_clks 26 1>;
426 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
427 ti,timer-pwm;
e4978763
LV		 428 };
429
fa09b12d 430 sdhci0: mmc@4f80000 {
3a1a0dfc
FA		 431 compatible = "ti,am654-sdhci-5.1";
432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
355be915 433 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
3a1a0dfc
FA		 434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
435 clock-names = "clk_ahb", "clk_xin";
436 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
437 mmc-ddr-1_8v;
438 mmc-hs200-1_8v;
c7d106b4
FA		 439 ti,otap-del-sel-legacy = <0x0>;
440 ti,otap-del-sel-mmc-hs = <0x0>;
441 ti,otap-del-sel-sd-hs = <0x0>;
442 ti,otap-del-sel-sdr12 = <0x0>;
443 ti,otap-del-sel-sdr25 = <0x0>;
444 ti,otap-del-sel-sdr50 = <0x8>;
fa09b12d 445 ti,otap-del-sel-sdr104 = <0x7>;
c7d106b4
FA		 446 ti,otap-del-sel-ddr50 = <0x5>;
447 ti,otap-del-sel-ddr52 = <0x5>;
448 ti,otap-del-sel-hs200 = <0x5>;
449 ti,otap-del-sel-hs400 = <0x0>;
3a1a0dfc
FA		 450 ti,trm-icp = <0x8>;
451 dma-coherent;
452 };
bbe59169 453
fa09b12d 454 sdhci1: mmc@4fa0000 {
2121c7e2
FA		 455 compatible = "ti,am654-sdhci-5.1";
456 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
457 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
458 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
459 clock-names = "clk_ahb", "clk_xin";
460 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
461 ti,otap-del-sel-legacy = <0x0>;
462 ti,otap-del-sel-mmc-hs = <0x0>;
463 ti,otap-del-sel-sd-hs = <0x0>;
464 ti,otap-del-sel-sdr12 = <0x0>;
465 ti,otap-del-sel-sdr25 = <0x0>;
466 ti,otap-del-sel-sdr50 = <0x8>;
467 ti,otap-del-sel-sdr104 = <0x7>;
468 ti,otap-del-sel-ddr50 = <0x4>;
469 ti,otap-del-sel-ddr52 = <0x4>;
470 ti,otap-del-sel-hs200 = <0x7>;
471 ti,clkbuf-sel = <0x7>;
472 ti,trm-icp = <0x8>;
473 dma-coherent;
474 };
475
e4978763 476 scm_conf: scm-conf@100000 {
476e9914
SN		 477 compatible = "syscon", "simple-mfd";
478 reg = <0 0x00100000 0 0x1c000>;
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges = <0x0 0x0 0x00100000 0x1c000>;
482
e4978763 483 serdes0_clk: clock@4080 {
476e9914 484 compatible = "syscon";
e4978763 485 reg = <0x00004080 0x4>;
476e9914
SN		 486 };
487
e4978763 488 serdes1_clk: clock@4090 {
476e9914 489 compatible = "syscon";
e4978763 490 reg = <0x00004090 0x4>;
476e9914 491 };
476e9914 492
e4978763
LV		 493 serdes_mux: mux-controller {
494 compatible = "mmio-mux";
495 #mux-control-cells = <1>;
496 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
497 <0x4090 0x3>; /* SERDES1 lane select */
498 };
476e9914 499
e4978763
LV		 500 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
501 compatible = "syscon";
4dbdc847 502 reg = <0x000041e0 0x14>;
e4978763 503 };
476e9914 504
4dbdc847
BB		 505 ehrpwm_tbclk: clock-controller@4140 {
506 compatible = "ti,am654-ehrpwm-tbclk";
e4978763
LV		 507 reg = <0x4140 0x18>;
508 #clock-cells = <1>;
476e9914
SN		 509 };
510 };
a1ac85da
VR		 511
512 dwc3_0: dwc3@4000000 {
513 compatible = "ti,am654-dwc3";
514 reg = <0x0 0x4000000 0x0 0x4000>;
515 #address-cells = <1>;
516 #size-cells = <1>;
517 ranges = <0x0 0x0 0x4000000 0x20000>;
518 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
519 dma-coherent;
520 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
e4978763 521 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
a1ac85da
VR		 522 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
523 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
524 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
525
526 usb0: usb@10000 {
527 compatible = "snps,dwc3";
528 reg = <0x10000 0x10000>;
529 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
532 interrupt-names = "peripheral",
533 "host",
534 "otg";
535 maximum-speed = "high-speed";
536 dr_mode = "otg";
537 phys = <&usb0_phy>;
538 phy-names = "usb2-phy";
539 snps,dis_u3_susphy_quirk;
540 };
541 };
542
543 usb0_phy: phy@4100000 {
544 compatible = "ti,am654-usb2", "ti,omap-usb2";
545 reg = <0x0 0x4100000 0x0 0x54>;
546 syscon-phy-power = <&scm_conf 0x4000>;
547 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
548 clock-names = "wkupclk", "refclk";
549 #phy-cells = <0>;
a1ac85da
VR		 550 };
551
552 dwc3_1: dwc3@4020000 {
553 compatible = "ti,am654-dwc3";
554 reg = <0x0 0x4020000 0x0 0x4000>;
555 #address-cells = <1>;
556 #size-cells = <1>;
557 ranges = <0x0 0x0 0x4020000 0x20000>;
558 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
559 dma-coherent;
560 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
e4978763 561 clocks = <&k3_clks 152 2>;
a1ac85da
VR		 562 assigned-clocks = <&k3_clks 152 2>;
563 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
564
565 usb1: usb@10000 {
566 compatible = "snps,dwc3";
567 reg = <0x10000 0x10000>;
568 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-names = "peripheral",
572 "host",
573 "otg";
574 maximum-speed = "high-speed";
575 dr_mode = "otg";
576 phys = <&usb1_phy>;
577 phy-names = "usb2-phy";
578 };
579 };
580
581 usb1_phy: phy@4110000 {
582 compatible = "ti,am654-usb2", "ti,omap-usb2";
583 reg = <0x0 0x4110000 0x0 0x54>;
584 syscon-phy-power = <&scm_conf 0x4020>;
585 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
586 clock-names = "wkupclk", "refclk";
587 #phy-cells = <0>;
e4978763
LV		 588 };
589
fa09b12d 590 intr_main_gpio: interrupt-controller@a00000 {
e4978763 591 compatible = "ti,sci-intr";
fa09b12d 592 reg = <0x0 0x00a00000 0x0 0x400>;
e4978763
LV		 593 ti,intr-trigger-type = <1>;
594 interrupt-controller;
595 interrupt-parent = <&gic500>;
596 #interrupt-cells = <1>;
597 ti,sci = <&dmsc>;
598 ti,sci-dev-id = <100>;
599 ti,interrupt-ranges = <0 392 32>;
600 };
601
fa09b12d 602 main_navss: bus@30800000 {
4dbdc847 603 compatible = "simple-bus";
e4978763
LV		 604 #address-cells = <2>;
605 #size-cells = <2>;
fa09b12d 606 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
e4978763
LV		 607 dma-coherent;
608 dma-ranges;
609
610 ti,sci-dev-id = <118>;
611
fa09b12d 612 intr_main_navss: interrupt-controller@310e0000 {
e4978763 613 compatible = "ti,sci-intr";
fa09b12d 614 reg = <0x0 0x310e0000 0x0 0x2000>;
e4978763
LV		 615 ti,intr-trigger-type = <4>;
616 interrupt-controller;
617 interrupt-parent = <&gic500>;
618 #interrupt-cells = <1>;
619 ti,sci = <&dmsc>;
620 ti,sci-dev-id = <182>;
621 ti,interrupt-ranges = <0 64 64>,
622 <64 448 64>;
623 };
624
625 inta_main_udmass: interrupt-controller@33d00000 {
626 compatible = "ti,sci-inta";
627 reg = <0x0 0x33d00000 0x0 0x100000>;
628 interrupt-controller;
629 interrupt-parent = <&intr_main_navss>;
630 msi-controller;
631 #interrupt-cells = <0>;
632 ti,sci = <&dmsc>;
633 ti,sci-dev-id = <179>;
634 ti,interrupt-ranges = <0 0 256>;
635 };
636
637 secure_proxy_main: mailbox@32c00000 {
638 compatible = "ti,am654-secure-proxy";
639 #mbox-cells = <1>;
640 reg-names = "target_data", "rt", "scfg";
641 reg = <0x00 0x32c00000 0x00 0x100000>,
642 <0x00 0x32400000 0x00 0x100000>,
643 <0x00 0x32800000 0x00 0x100000>;
644 interrupt-names = "rx_011";
645 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
646 };
647
648 hwspinlock: spinlock@30e00000 {
649 compatible = "ti,am654-hwspinlock";
650 reg = <0x00 0x30e00000 0x00 0x1000>;
651 #hwlock-cells = <1>;
652 };
653
654 mailbox0_cluster0: mailbox@31f80000 {
655 compatible = "ti,am654-mailbox";
656 reg = <0x00 0x31f80000 0x00 0x200>;
657 #mbox-cells = <1>;
658 ti,mbox-num-users = <4>;
659 ti,mbox-num-fifos = <16>;
660 interrupt-parent = <&intr_main_navss>;
4dbdc847 661 status = "disabled";
e4978763
LV		 662 };
663
664 mailbox0_cluster1: mailbox@31f81000 {
665 compatible = "ti,am654-mailbox";
666 reg = <0x00 0x31f81000 0x00 0x200>;
667 #mbox-cells = <1>;
668 ti,mbox-num-users = <4>;
669 ti,mbox-num-fifos = <16>;
670 interrupt-parent = <&intr_main_navss>;
4dbdc847 671 status = "disabled";
e4978763
LV		 672 };
673
674 mailbox0_cluster2: mailbox@31f82000 {
675 compatible = "ti,am654-mailbox";
676 reg = <0x00 0x31f82000 0x00 0x200>;
677 #mbox-cells = <1>;
678 ti,mbox-num-users = <4>;
679 ti,mbox-num-fifos = <16>;
680 interrupt-parent = <&intr_main_navss>;
4dbdc847 681 status = "disabled";
e4978763
LV		 682 };
683
684 mailbox0_cluster3: mailbox@31f83000 {
685 compatible = "ti,am654-mailbox";
686 reg = <0x00 0x31f83000 0x00 0x200>;
687 #mbox-cells = <1>;
688 ti,mbox-num-users = <4>;
689 ti,mbox-num-fifos = <16>;
690 interrupt-parent = <&intr_main_navss>;
4dbdc847 691 status = "disabled";
e4978763
LV		 692 };
693
694 mailbox0_cluster4: mailbox@31f84000 {
695 compatible = "ti,am654-mailbox";
696 reg = <0x00 0x31f84000 0x00 0x200>;
697 #mbox-cells = <1>;
698 ti,mbox-num-users = <4>;
699 ti,mbox-num-fifos = <16>;
700 interrupt-parent = <&intr_main_navss>;
4dbdc847 701 status = "disabled";
e4978763
LV		 702 };
703
704 mailbox0_cluster5: mailbox@31f85000 {
705 compatible = "ti,am654-mailbox";
706 reg = <0x00 0x31f85000 0x00 0x200>;
707 #mbox-cells = <1>;
708 ti,mbox-num-users = <4>;
709 ti,mbox-num-fifos = <16>;
710 interrupt-parent = <&intr_main_navss>;
4dbdc847 711 status = "disabled";
e4978763
LV		 712 };
713
714 mailbox0_cluster6: mailbox@31f86000 {
715 compatible = "ti,am654-mailbox";
716 reg = <0x00 0x31f86000 0x00 0x200>;
717 #mbox-cells = <1>;
718 ti,mbox-num-users = <4>;
719 ti,mbox-num-fifos = <16>;
720 interrupt-parent = <&intr_main_navss>;
4dbdc847 721 status = "disabled";
e4978763
LV		 722 };
723
724 mailbox0_cluster7: mailbox@31f87000 {
725 compatible = "ti,am654-mailbox";
726 reg = <0x00 0x31f87000 0x00 0x200>;
727 #mbox-cells = <1>;
728 ti,mbox-num-users = <4>;
729 ti,mbox-num-fifos = <16>;
730 interrupt-parent = <&intr_main_navss>;
4dbdc847 731 status = "disabled";
e4978763
LV		 732 };
733
734 mailbox0_cluster8: mailbox@31f88000 {
735 compatible = "ti,am654-mailbox";
736 reg = <0x00 0x31f88000 0x00 0x200>;
737 #mbox-cells = <1>;
738 ti,mbox-num-users = <4>;
739 ti,mbox-num-fifos = <16>;
740 interrupt-parent = <&intr_main_navss>;
4dbdc847 741 status = "disabled";
e4978763
LV		 742 };
743
744 mailbox0_cluster9: mailbox@31f89000 {
745 compatible = "ti,am654-mailbox";
746 reg = <0x00 0x31f89000 0x00 0x200>;
747 #mbox-cells = <1>;
748 ti,mbox-num-users = <4>;
749 ti,mbox-num-fifos = <16>;
750 interrupt-parent = <&intr_main_navss>;
4dbdc847 751 status = "disabled";
e4978763
LV		 752 };
753
754 mailbox0_cluster10: mailbox@31f8a000 {
755 compatible = "ti,am654-mailbox";
756 reg = <0x00 0x31f8a000 0x00 0x200>;
757 #mbox-cells = <1>;
758 ti,mbox-num-users = <4>;
759 ti,mbox-num-fifos = <16>;
760 interrupt-parent = <&intr_main_navss>;
4dbdc847 761 status = "disabled";
e4978763
LV		 762 };
763
764 mailbox0_cluster11: mailbox@31f8b000 {
765 compatible = "ti,am654-mailbox";
766 reg = <0x00 0x31f8b000 0x00 0x200>;
767 #mbox-cells = <1>;
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <16>;
770 interrupt-parent = <&intr_main_navss>;
4dbdc847 771 status = "disabled";
e4978763
LV		 772 };
773
774 ringacc: ringacc@3c000000 {
775 compatible = "ti,am654-navss-ringacc";
4dbdc847
BB		 776 reg = <0x0 0x3c000000 0x0 0x400000>,
777 <0x0 0x38000000 0x0 0x400000>,
778 <0x0 0x31120000 0x0 0x100>,
779 <0x0 0x33000000 0x0 0x40000>,
780 <0x0 0x31080000 0x0 0x40000>;
781 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
e4978763
LV		 782 ti,num-rings = <818>;
783 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
784 ti,sci = <&dmsc>;
785 ti,sci-dev-id = <187>;
786 msi-parent = <&inta_main_udmass>;
787 };
788
789 main_udmap: dma-controller@31150000 {
790 compatible = "ti,am654-navss-main-udmap";
4dbdc847
BB		 791 reg = <0x0 0x31150000 0x0 0x100>,
792 <0x0 0x34000000 0x0 0x100000>,
793 <0x0 0x35000000 0x0 0x100000>;
e4978763
LV		 794 reg-names = "gcfg", "rchanrt", "tchanrt";
795 msi-parent = <&inta_main_udmass>;
796 #dma-cells = <1>;
797
798 ti,sci = <&dmsc>;
799 ti,sci-dev-id = <188>;
800 ti,ringacc = <&ringacc>;
801
802 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
803 <0xd>; /* TX_CHAN */
804 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
805 <0xa>; /* RX_CHAN */
806 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
807 };
808
809 cpts@310d0000 {
810 compatible = "ti,am65-cpts";
811 reg = <0x0 0x310d0000 0x0 0x400>;
812 reg-names = "cpts";
813 clocks = <&main_cpts_mux>;
814 clock-names = "cpts";
815 interrupts-extended = <&intr_main_navss 391>;
816 interrupt-names = "cpts";
817 ti,cpts-periodic-outputs = <6>;
818 ti,cpts-ext-ts-inputs = <8>;
819
820 main_cpts_mux: refclk-mux {
821 #clock-cells = <0>;
822 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
823 <&k3_clks 118 6>, <&k3_clks 118 3>,
824 <&k3_clks 118 8>, <&k3_clks 118 14>,
825 <&k3_clks 120 3>, <&k3_clks 121 3>;
826 assigned-clocks = <&main_cpts_mux>;
827 assigned-clock-parents = <&k3_clks 118 5>;
828 };
829 };
830 };
831
832 main_gpio0: gpio@600000 {
833 compatible = "ti,am654-gpio", "ti,keystone-gpio";
834 reg = <0x0 0x600000 0x0 0x100>;
835 gpio-controller;
836 #gpio-cells = <2>;
837 interrupt-parent = <&intr_main_gpio>;
838 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
839 interrupt-controller;
840 #interrupt-cells = <2>;
841 ti,ngpio = <96>;
842 ti,davinci-gpio-unbanked = <0>;
843 clocks = <&k3_clks 57 0>;
844 clock-names = "gpio";
845 };
846
847 main_gpio1: gpio@601000 {
848 compatible = "ti,am654-gpio", "ti,keystone-gpio";
849 reg = <0x0 0x601000 0x0 0x100>;
850 gpio-controller;
851 #gpio-cells = <2>;
852 interrupt-parent = <&intr_main_gpio>;
853 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
854 interrupt-controller;
855 #interrupt-cells = <2>;
856 ti,ngpio = <90>;
857 ti,davinci-gpio-unbanked = <0>;
858 clocks = <&k3_clks 58 0>;
859 clock-names = "gpio";
860 };
861
862 pcie0_rc: pcie@5500000 {
863 compatible = "ti,am654-pcie-rc";
4dbdc847 864 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
e4978763
LV		 865 reg-names = "app", "dbics", "config", "atu";
866 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
867 #address-cells = <3>;
868 #size-cells = <2>;
4dbdc847
BB		 869 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
870 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
871 ti,syscon-pcie-id = <&scm_conf 0x210>;
872 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
e4978763
LV		 873 bus-range = <0x0 0xff>;
874 num-viewport = <16>;
875 max-link-speed = <2>;
876 dma-coherent;
877 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
878 msi-map = <0x0 &gic_its 0x0 0x10000>;
fa09b12d 879 device_type = "pci";
4dbdc847 880 status = "disabled";
e4978763
LV		 881 };
882
883 pcie0_ep: pcie-ep@5500000 {
884 compatible = "ti,am654-pcie-ep";
4dbdc847 885 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
e4978763
LV		 886 reg-names = "app", "dbics", "addr_space", "atu";
887 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 888 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
e4978763
LV		 889 num-ib-windows = <16>;
890 num-ob-windows = <16>;
891 max-link-speed = <2>;
892 dma-coherent;
893 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
4dbdc847 894 status = "disabled";
e4978763
LV		 895 };
896
897 pcie1_rc: pcie@5600000 {
898 compatible = "ti,am654-pcie-rc";
4dbdc847 899 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
e4978763
LV		 900 reg-names = "app", "dbics", "config", "atu";
901 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
902 #address-cells = <3>;
903 #size-cells = <2>;
4dbdc847
BB		 904 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
905 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
906 ti,syscon-pcie-id = <&scm_conf 0x210>;
907 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
e4978763
LV		 908 bus-range = <0x0 0xff>;
909 num-viewport = <16>;
910 max-link-speed = <2>;
911 dma-coherent;
912 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
913 msi-map = <0x0 &gic_its 0x10000 0x10000>;
fa09b12d 914 device_type = "pci";
4dbdc847 915 status = "disabled";
e4978763
LV		 916 };
917
918 pcie1_ep: pcie-ep@5600000 {
919 compatible = "ti,am654-pcie-ep";
4dbdc847 920 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
e4978763
LV		 921 reg-names = "app", "dbics", "addr_space", "atu";
922 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 923 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
e4978763
LV		 924 num-ib-windows = <16>;
925 num-ob-windows = <16>;
926 max-link-speed = <2>;
927 dma-coherent;
928 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
4dbdc847 929 status = "disabled";
e4978763
LV		 930 };
931
932 mcasp0: mcasp@2b00000 {
933 compatible = "ti,am33xx-mcasp-audio";
934 reg = <0x0 0x02b00000 0x0 0x2000>,
935 <0x0 0x02b08000 0x0 0x1000>;
936 reg-names = "mpu","dat";
937 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "tx", "rx";
940
941 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
942 dma-names = "tx", "rx";
943
944 clocks = <&k3_clks 104 0>;
945 clock-names = "fck";
946 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 947 status = "disabled";
e4978763
LV		 948 };
949
950 mcasp1: mcasp@2b10000 {
951 compatible = "ti,am33xx-mcasp-audio";
952 reg = <0x0 0x02b10000 0x0 0x2000>,
953 <0x0 0x02b18000 0x0 0x1000>;
954 reg-names = "mpu","dat";
955 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
957 interrupt-names = "tx", "rx";
958
959 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
960 dma-names = "tx", "rx";
961
962 clocks = <&k3_clks 105 0>;
963 clock-names = "fck";
964 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 965 status = "disabled";
e4978763
LV		 966 };
967
968 mcasp2: mcasp@2b20000 {
969 compatible = "ti,am33xx-mcasp-audio";
970 reg = <0x0 0x02b20000 0x0 0x2000>,
971 <0x0 0x02b28000 0x0 0x1000>;
972 reg-names = "mpu","dat";
973 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
975 interrupt-names = "tx", "rx";
976
977 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
978 dma-names = "tx", "rx";
979
980 clocks = <&k3_clks 106 0>;
981 clock-names = "fck";
982 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
4dbdc847 983 status = "disabled";
e4978763
LV		 984 };
985
986 cal: cal@6f03000 {
987 compatible = "ti,am654-cal";
988 reg = <0x0 0x06f03000 0x0 0x400>,
989 <0x0 0x06f03800 0x0 0x40>;
990 reg-names = "cal_top",
991 "cal_rx_core0";
992 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
993 ti,camerrx-control = <&scm_conf 0x40c0>;
994 clock-names = "fck";
995 clocks = <&k3_clks 2 0>;
996 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
997
998 ports {
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001
1002 csi2_0: port@0 {
1003 reg = <0>;
1004 };
1005 };
1006 };
1007
1008 dss: dss@4a00000 {
1009 compatible = "ti,am65x-dss";
4dbdc847
BB		 1010 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
1011 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1012 <0x0 0x04a06000 0x0 0x1000>, /* vid */
1013 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1014 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1015 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1016 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
e4978763
LV		 1017 reg-names = "common", "vidl1", "vid",
1018 "ovr1", "ovr2", "vp1", "vp2";
1019
1020 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
1021
1022 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1023
4dbdc847
BB		 1024 clocks = <&k3_clks 67 1>,
1025 <&k3_clks 216 1>,
1026 <&k3_clks 67 2>;
e4978763
LV		 1027 clock-names = "fck", "vp1", "vp2";
1028
1029 /*
1030 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
1031 * DIV1. See "Figure 12-3365. DSS Integration"
1032 * in AM65x TRM for details.
1033 */
1034 assigned-clocks = <&k3_clks 67 2>;
1035 assigned-clock-parents = <&k3_clks 67 5>;
1036
1037 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
1038
1039 dma-coherent;
1040
1041 dss_ports: ports {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 };
1045 };
1046
1047 ehrpwm0: pwm@3000000 {
1048 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1049 #pwm-cells = <3>;
1050 reg = <0x0 0x3000000 0x0 0x100>;
1051 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
1052 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1053 clock-names = "tbclk", "fck";
4dbdc847 1054 status = "disabled";
e4978763
LV		 1055 };
1056
1057 ehrpwm1: pwm@3010000 {
1058 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1059 #pwm-cells = <3>;
1060 reg = <0x0 0x3010000 0x0 0x100>;
1061 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
1062 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1063 clock-names = "tbclk", "fck";
4dbdc847 1064 status = "disabled";
e4978763
LV		 1065 };
1066
1067 ehrpwm2: pwm@3020000 {
1068 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1069 #pwm-cells = <3>;
1070 reg = <0x0 0x3020000 0x0 0x100>;
1071 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
1072 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1073 clock-names = "tbclk", "fck";
4dbdc847 1074 status = "disabled";
e4978763
LV		 1075 };
1076
1077 ehrpwm3: pwm@3030000 {
1078 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1079 #pwm-cells = <3>;
1080 reg = <0x0 0x3030000 0x0 0x100>;
1081 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
1082 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1083 clock-names = "tbclk", "fck";
4dbdc847 1084 status = "disabled";
e4978763
LV		 1085 };
1086
1087 ehrpwm4: pwm@3040000 {
1088 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1089 #pwm-cells = <3>;
1090 reg = <0x0 0x3040000 0x0 0x100>;
1091 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
1092 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1093 clock-names = "tbclk", "fck";
4dbdc847 1094 status = "disabled";
e4978763
LV		 1095 };
1096
1097 ehrpwm5: pwm@3050000 {
1098 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1099 #pwm-cells = <3>;
1100 reg = <0x0 0x3050000 0x0 0x100>;
1101 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
1102 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1103 clock-names = "tbclk", "fck";
4dbdc847 1104 status = "disabled";
a1ac85da 1105 };
c81e7f8d
LV		 1106
1107 icssg0: icssg@b000000 {
1108 compatible = "ti,am654-icssg";
1109 reg = <0x00 0xb000000 0x00 0x80000>;
1110 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1111 #address-cells = <1>;
1112 #size-cells = <1>;
1113 ranges = <0x0 0x00 0xb000000 0x80000>;
1114
1115 icssg0_mem: memories@0 {
1116 reg = <0x0 0x2000>,
1117 <0x2000 0x2000>,
1118 <0x10000 0x10000>;
1119 reg-names = "dram0", "dram1",
1120 "shrdram2";
1121 };
1122
1123 icssg0_cfg: cfg@26000 {
1124 compatible = "ti,pruss-cfg", "syscon";
1125 reg = <0x26000 0x200>;
1126 #address-cells = <1>;
1127 #size-cells = <1>;
1128 ranges = <0x0 0x26000 0x2000>;
1129
1130 clocks {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133
1134 icssg0_coreclk_mux: coreclk-mux@3c {
1135 reg = <0x3c>;
1136 #clock-cells = <0>;
1137 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
1138 <&k3_clks 62 3>; /* icssg0_iclk */
1139 assigned-clocks = <&icssg0_coreclk_mux>;
1140 assigned-clock-parents = <&k3_clks 62 3>;
1141 };
1142
1143 icssg0_iepclk_mux: iepclk-mux@30 {
1144 reg = <0x30>;
1145 #clock-cells = <0>;
1146 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
1147 <&icssg0_coreclk_mux>; /* core_clk */
1148 assigned-clocks = <&icssg0_iepclk_mux>;
1149 assigned-clock-parents = <&icssg0_coreclk_mux>;
1150 };
1151 };
1152 };
1153
4dbdc847
BB		 1154 icssg0_iep0: iep@2e000 {
1155 compatible = "ti,am654-icss-iep";
1156 reg = <0x2e000 0x1000>;
1157 clocks = <&icssg0_iepclk_mux>;
1158 };
1159
1160 icssg0_iep1: iep@2f000 {
1161 compatible = "ti,am654-icss-iep";
1162 reg = <0x2f000 0x1000>;
1163 clocks = <&icssg0_iepclk_mux>;
1164 };
1165
c81e7f8d
LV		 1166 icssg0_mii_rt: mii-rt@32000 {
1167 compatible = "ti,pruss-mii", "syscon";
1168 reg = <0x32000 0x100>;
1169 };
1170
1171 icssg0_mii_g_rt: mii-g-rt@33000 {
1172 compatible = "ti,pruss-mii-g", "syscon";
1173 reg = <0x33000 0x1000>;
1174 };
1175
1176 icssg0_intc: interrupt-controller@20000 {
1177 compatible = "ti,icssg-intc";
1178 reg = <0x20000 0x2000>;
1179 interrupt-controller;
1180 #interrupt-cells = <3>;
1181 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1189 interrupt-names = "host_intr0", "host_intr1",
1190 "host_intr2", "host_intr3",
1191 "host_intr4", "host_intr5",
1192 "host_intr6", "host_intr7";
1193 };
1194
1195 pru0_0: pru@34000 {
1196 compatible = "ti,am654-pru";
1197 reg = <0x34000 0x4000>,
1198 <0x22000 0x100>,
1199 <0x22400 0x100>;
1200 reg-names = "iram", "control", "debug";
1201 firmware-name = "am65x-pru0_0-fw";
1202 };
1203
1204 rtu0_0: rtu@4000 {
1205 compatible = "ti,am654-rtu";
1206 reg = <0x4000 0x2000>,
1207 <0x23000 0x100>,
1208 <0x23400 0x100>;
1209 reg-names = "iram", "control", "debug";
1210 firmware-name = "am65x-rtu0_0-fw";
1211 };
1212
1213 tx_pru0_0: txpru@a000 {
1214 compatible = "ti,am654-tx-pru";
1215 reg = <0xa000 0x1800>,
1216 <0x25000 0x100>,
1217 <0x25400 0x100>;
1218 reg-names = "iram", "control", "debug";
1219 firmware-name = "am65x-txpru0_0-fw";
1220 };
1221
1222 pru0_1: pru@38000 {
1223 compatible = "ti,am654-pru";
1224 reg = <0x38000 0x4000>,
1225 <0x24000 0x100>,
1226 <0x24400 0x100>;
1227 reg-names = "iram", "control", "debug";
1228 firmware-name = "am65x-pru0_1-fw";
1229 };
1230
1231 rtu0_1: rtu@6000 {
1232 compatible = "ti,am654-rtu";
1233 reg = <0x6000 0x2000>,
1234 <0x23800 0x100>,
1235 <0x23c00 0x100>;
1236 reg-names = "iram", "control", "debug";
1237 firmware-name = "am65x-rtu0_1-fw";
1238 };
1239
1240 tx_pru0_1: txpru@c000 {
1241 compatible = "ti,am654-tx-pru";
1242 reg = <0xc000 0x1800>,
1243 <0x25800 0x100>,
1244 <0x25c00 0x100>;
1245 reg-names = "iram", "control", "debug";
1246 firmware-name = "am65x-txpru0_1-fw";
1247 };
1248
1249 icssg0_mdio: mdio@32400 {
1250 compatible = "ti,davinci_mdio";
1251 reg = <0x32400 0x100>;
1252 clocks = <&k3_clks 62 3>;
1253 clock-names = "fck";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 bus_freq = <1000000>;
4dbdc847 1257 status = "disabled";
c81e7f8d
LV		 1258 };
1259 };
1260
1261 icssg1: icssg@b100000 {
1262 compatible = "ti,am654-icssg";
1263 reg = <0x00 0xb100000 0x00 0x80000>;
1264 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1265 #address-cells = <1>;
1266 #size-cells = <1>;
1267 ranges = <0x0 0x00 0xb100000 0x80000>;
1268
1269 icssg1_mem: memories@0 {
1270 reg = <0x0 0x2000>,
1271 <0x2000 0x2000>,
1272 <0x10000 0x10000>;
1273 reg-names = "dram0", "dram1",
1274 "shrdram2";
1275 };
1276
1277 icssg1_cfg: cfg@26000 {
1278 compatible = "ti,pruss-cfg", "syscon";
1279 reg = <0x26000 0x200>;
1280 #address-cells = <1>;
1281 #size-cells = <1>;
1282 ranges = <0x0 0x26000 0x2000>;
1283
1284 clocks {
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1287
1288 icssg1_coreclk_mux: coreclk-mux@3c {
1289 reg = <0x3c>;
1290 #clock-cells = <0>;
1291 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1292 <&k3_clks 63 3>; /* icssg1_iclk */
1293 assigned-clocks = <&icssg1_coreclk_mux>;
1294 assigned-clock-parents = <&k3_clks 63 3>;
1295 };
1296
1297 icssg1_iepclk_mux: iepclk-mux@30 {
1298 reg = <0x30>;
1299 #clock-cells = <0>;
1300 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
1301 <&icssg1_coreclk_mux>; /* core_clk */
1302 assigned-clocks = <&icssg1_iepclk_mux>;
1303 assigned-clock-parents = <&icssg1_coreclk_mux>;
1304 };
1305 };
1306 };
1307
4dbdc847
BB		 1308 icssg1_iep0: iep@2e000 {
1309 compatible = "ti,am654-icss-iep";
1310 reg = <0x2e000 0x1000>;
1311 clocks = <&icssg1_iepclk_mux>;
1312 };
1313
1314 icssg1_iep1: iep@2f000 {
1315 compatible = "ti,am654-icss-iep";
1316 reg = <0x2f000 0x1000>;
1317 clocks = <&icssg1_iepclk_mux>;
1318 };
1319
c81e7f8d
LV		 1320 icssg1_mii_rt: mii-rt@32000 {
1321 compatible = "ti,pruss-mii", "syscon";
1322 reg = <0x32000 0x100>;
1323 };
1324
1325 icssg1_mii_g_rt: mii-g-rt@33000 {
1326 compatible = "ti,pruss-mii-g", "syscon";
1327 reg = <0x33000 0x1000>;
1328 };
1329
1330 icssg1_intc: interrupt-controller@20000 {
1331 compatible = "ti,icssg-intc";
1332 reg = <0x20000 0x2000>;
1333 interrupt-controller;
1334 #interrupt-cells = <3>;
1335 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1343 interrupt-names = "host_intr0", "host_intr1",
1344 "host_intr2", "host_intr3",
1345 "host_intr4", "host_intr5",
1346 "host_intr6", "host_intr7";
1347 };
1348
1349 pru1_0: pru@34000 {
1350 compatible = "ti,am654-pru";
1351 reg = <0x34000 0x4000>,
1352 <0x22000 0x100>,
1353 <0x22400 0x100>;
1354 reg-names = "iram", "control", "debug";
1355 firmware-name = "am65x-pru1_0-fw";
1356 };
1357
1358 rtu1_0: rtu@4000 {
1359 compatible = "ti,am654-rtu";
1360 reg = <0x4000 0x2000>,
1361 <0x23000 0x100>,
1362 <0x23400 0x100>;
1363 reg-names = "iram", "control", "debug";
1364 firmware-name = "am65x-rtu1_0-fw";
1365 };
1366
1367 tx_pru1_0: txpru@a000 {
1368 compatible = "ti,am654-tx-pru";
1369 reg = <0xa000 0x1800>,
1370 <0x25000 0x100>,
1371 <0x25400 0x100>;
1372 reg-names = "iram", "control", "debug";
1373 firmware-name = "am65x-txpru1_0-fw";
1374 };
1375
1376 pru1_1: pru@38000 {
1377 compatible = "ti,am654-pru";
1378 reg = <0x38000 0x4000>,
1379 <0x24000 0x100>,
1380 <0x24400 0x100>;
1381 reg-names = "iram", "control", "debug";
1382 firmware-name = "am65x-pru1_1-fw";
1383 };
1384
1385 rtu1_1: rtu@6000 {
1386 compatible = "ti,am654-rtu";
1387 reg = <0x6000 0x2000>,
1388 <0x23800 0x100>,
1389 <0x23c00 0x100>;
1390 reg-names = "iram", "control", "debug";
1391 firmware-name = "am65x-rtu1_1-fw";
1392 };
1393
1394 tx_pru1_1: txpru@c000 {
1395 compatible = "ti,am654-tx-pru";
1396 reg = <0xc000 0x1800>,
1397 <0x25800 0x100>,
1398 <0x25c00 0x100>;
1399 reg-names = "iram", "control", "debug";
1400 firmware-name = "am65x-txpru1_1-fw";
1401 };
1402
1403 icssg1_mdio: mdio@32400 {
1404 compatible = "ti,davinci_mdio";
1405 reg = <0x32400 0x100>;
1406 clocks = <&k3_clks 63 3>;
1407 clock-names = "fck";
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1410 bus_freq = <1000000>;
4dbdc847 1411 status = "disabled";
c81e7f8d
LV		 1412 };
1413 };
1414
1415 icssg2: icssg@b200000 {
1416 compatible = "ti,am654-icssg";
1417 reg = <0x00 0xb200000 0x00 0x80000>;
1418 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1419 #address-cells = <1>;
1420 #size-cells = <1>;
1421 ranges = <0x0 0x00 0xb200000 0x80000>;
1422
1423 icssg2_mem: memories@0 {
1424 reg = <0x0 0x2000>,
1425 <0x2000 0x2000>,
1426 <0x10000 0x10000>;
1427 reg-names = "dram0", "dram1",
1428 "shrdram2";
1429 };
1430
1431 icssg2_cfg: cfg@26000 {
1432 compatible = "ti,pruss-cfg", "syscon";
1433 reg = <0x26000 0x200>;
1434 #address-cells = <1>;
1435 #size-cells = <1>;
1436 ranges = <0x0 0x26000 0x2000>;
1437
1438 clocks {
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1441
1442 icssg2_coreclk_mux: coreclk-mux@3c {
1443 reg = <0x3c>;
1444 #clock-cells = <0>;
1445 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1446 <&k3_clks 64 3>; /* icssg1_iclk */
1447 assigned-clocks = <&icssg2_coreclk_mux>;
1448 assigned-clock-parents = <&k3_clks 64 3>;
1449 };
1450
1451 icssg2_iepclk_mux: iepclk-mux@30 {
1452 reg = <0x30>;
1453 #clock-cells = <0>;
1454 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
1455 <&icssg2_coreclk_mux>; /* core_clk */
1456 assigned-clocks = <&icssg2_iepclk_mux>;
1457 assigned-clock-parents = <&icssg2_coreclk_mux>;
1458 };
1459 };
1460 };
1461
4dbdc847
BB		 1462 icssg2_iep0: iep@2e000 {
1463 compatible = "ti,am654-icss-iep";
1464 reg = <0x2e000 0x1000>;
1465 clocks = <&icssg2_iepclk_mux>;
1466 };
1467
1468 icssg2_iep1: iep@2f000 {
1469 compatible = "ti,am654-icss-iep";
1470 reg = <0x2f000 0x1000>;
1471 clocks = <&icssg2_iepclk_mux>;
1472 };
1473
c81e7f8d
LV		 1474 icssg2_mii_rt: mii-rt@32000 {
1475 compatible = "ti,pruss-mii", "syscon";
1476 reg = <0x32000 0x100>;
1477 };
1478
1479 icssg2_mii_g_rt: mii-g-rt@33000 {
1480 compatible = "ti,pruss-mii-g", "syscon";
1481 reg = <0x33000 0x1000>;
1482 };
1483
1484 icssg2_intc: interrupt-controller@20000 {
1485 compatible = "ti,icssg-intc";
1486 reg = <0x20000 0x2000>;
1487 interrupt-controller;
1488 #interrupt-cells = <3>;
1489 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1497 interrupt-names = "host_intr0", "host_intr1",
1498 "host_intr2", "host_intr3",
1499 "host_intr4", "host_intr5",
1500 "host_intr6", "host_intr7";
1501 };
1502
1503 pru2_0: pru@34000 {
1504 compatible = "ti,am654-pru";
1505 reg = <0x34000 0x4000>,
1506 <0x22000 0x100>,
1507 <0x22400 0x100>;
1508 reg-names = "iram", "control", "debug";
1509 firmware-name = "am65x-pru2_0-fw";
1510 };
1511
1512 rtu2_0: rtu@4000 {
1513 compatible = "ti,am654-rtu";
1514 reg = <0x4000 0x2000>,
1515 <0x23000 0x100>,
1516 <0x23400 0x100>;
1517 reg-names = "iram", "control", "debug";
1518 firmware-name = "am65x-rtu2_0-fw";
1519 };
1520
1521 tx_pru2_0: txpru@a000 {
1522 compatible = "ti,am654-tx-pru";
1523 reg = <0xa000 0x1800>,
1524 <0x25000 0x100>,
1525 <0x25400 0x100>;
1526 reg-names = "iram", "control", "debug";
1527 firmware-name = "am65x-txpru2_0-fw";
1528 };
1529
1530 pru2_1: pru@38000 {
1531 compatible = "ti,am654-pru";
1532 reg = <0x38000 0x4000>,
1533 <0x24000 0x100>,
1534 <0x24400 0x100>;
1535 reg-names = "iram", "control", "debug";
1536 firmware-name = "am65x-pru2_1-fw";
1537 };
1538
1539 rtu2_1: rtu@6000 {
1540 compatible = "ti,am654-rtu";
1541 reg = <0x6000 0x2000>,
1542 <0x23800 0x100>,
1543 <0x23c00 0x100>;
1544 reg-names = "iram", "control", "debug";
1545 firmware-name = "am65x-rtu2_1-fw";
1546 };
1547
1548 tx_pru2_1: txpru@c000 {
1549 compatible = "ti,am654-tx-pru";
1550 reg = <0xc000 0x1800>,
1551 <0x25800 0x100>,
1552 <0x25c00 0x100>;
1553 reg-names = "iram", "control", "debug";
1554 firmware-name = "am65x-txpru2_1-fw";
1555 };
1556
1557 icssg2_mdio: mdio@32400 {
1558 compatible = "ti,davinci_mdio";
1559 reg = <0x32400 0x100>;
1560 clocks = <&k3_clks 64 3>;
1561 clock-names = "fck";
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1564 bus_freq = <1000000>;
4dbdc847 1565 status = "disabled";
c81e7f8d
LV		 1566 };
1567 };
ea8ad1d9 1568};
Empty description
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