[u-boot.git] / arch / arm / dts / imx6ull-myir-mys-6ulx.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Linumiz
 * Author: Parthiban Nallathambi <[email protected]>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "MYiR MYS-6ULX Single Board Computer";
	compatible = "fsl,imx6ull";

	chosen {
		stdout-path = &uart1;
	};

	reg_vdd_5v: regulator-vdd-5v {
		compatible = "regulator-fixed";
		regulator-name = "VDD_5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_vdd_3v3: regulator-vdd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VDD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		vin-supply = <&reg_vdd_5v>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_vdd_3v3>;
	status = "okay";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
			interrupt-parent = <&gpio5>;
			interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_vdd_3v3>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <8>;
	non-removable;
	keep-power-in-suspend;
	vmmc-supply = <&reg_vdd_3v3>;
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
		>;
	};
};
Commit	Line	Data
10e959a1 PN	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2020 Linumiz
	4	* Author: Parthiban Nallathambi <[email protected]>
	5	*/
	6
	7	#include <dt-bindings/gpio/gpio.h>
	8	#include <dt-bindings/interrupt-controller/irq.h>
	9	#include <dt-bindings/pwm/pwm.h>
	10
	11	/ {
	12	model = "MYiR MYS-6ULX Single Board Computer";
	13	compatible = "fsl,imx6ull";
	14
	15	chosen {
	16	stdout-path = &uart1;
	17	};
	18
	19	reg_vdd_5v: regulator-vdd-5v {
	20	compatible = "regulator-fixed";
	21	regulator-name = "VDD_5V";
	22	regulator-min-microvolt = <5000000>;
	23	regulator-max-microvolt = <5000000>;
	24	regulator-always-on;
	25	regulator-boot-on;
	26	};
	27
	28	reg_vdd_3v3: regulator-vdd-3v3 {
	29	compatible = "regulator-fixed";
	30	regulator-name = "VDD_3V3";
	31	regulator-min-microvolt = <3300000>;
	32	regulator-max-microvolt = <3300000>;
	33	regulator-always-on;
	34	vin-supply = <&reg_vdd_5v>;
	35	};
	36	};
	37
	38	&fec1 {
	39	pinctrl-names = "default";
	40	pinctrl-0 = <&pinctrl_enet1>;
	41	phy-mode = "rmii";
	42	phy-handle = <&ethphy0>;
	43	phy-supply = <&reg_vdd_3v3>;
	44	status = "okay";
	45
	46	mdio: mdio {
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
	50	ethphy0: ethernet-phy@0 {
	51	reg = <0>;
	52	interrupt-parent = <&gpio5>;
	53	interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
	54	clocks = <&clks IMX6UL_CLK_ENET_REF>;
	55	clock-names = "rmii-ref";
	56	};
	57	};
	58	};
	59
	60	&gpmi {
	61	pinctrl-names = "default";
	62	pinctrl-0 = <&pinctrl_gpmi_nand>;
	63	nand-on-flash-bbt;
	64	status = "disabled";
65	};
66
67	&uart1 {
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_uart1>;
70	status = "okay";
71	};
72
73	&usbotg1 {
74	pinctrl-names = "default";
75	pinctrl-0 = <&pinctrl_usb_otg1_id>;
76	dr_mode = "otg";
77	status = "okay";
78	};
79
80	&usbotg2 {
81	dr_mode = "host";
82	disable-over-current;
83	status = "okay";
84	};
85
86	&usdhc1 {
87	pinctrl-names = "default", "state_100mhz", "state_200mhz";
88	pinctrl-0 = <&pinctrl_usdhc1>;
89	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
90	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
91	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
92	no-1-8-v;
93	keep-power-in-suspend;
94	wakeup-source;
95	vmmc-supply = <&reg_vdd_3v3>;
96	status = "okay";
97	};
98
99	&usdhc2 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pinctrl_usdhc2>;
102	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
103	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
104	bus-width = <8>;
105	non-removable;
106	keep-power-in-suspend;
107	vmmc-supply = <&reg_vdd_3v3>;
108	};
109
110	&iomuxc {
111	pinctrl_enet1: enet1grp {
112	fsl,pins = <
113	MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
114	MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
115	MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
116	MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
117	MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
118	MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
119	MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
120	MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
121	MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
122	MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
123	MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
124	>;
125	};
126
127	pinctrl_gpmi_nand: gpminandgrp {
128	fsl,pins = <
129	MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
130	MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
131	MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
132	MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
133	MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
134	MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
135	MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
136	MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
137	MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
138	MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
139	MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
140	MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
141	MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
142	MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
143	MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
144	>;
145	};
146
147	pinctrl_uart1: uart1grp {
148	fsl,pins = <
149	MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
150	MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
151	>;
152	};
153
154	pinctrl_usb_otg1_id: usbotg1idgrp {
155	fsl,pins = <
156	MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
157	>;
158	};
159
160	pinctrl_usdhc1: usdhc1grp {
161	fsl,pins = <
162	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
163	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
164	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
165	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
166	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
167	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
168	MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
169	>;
170	};
171
172	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
173	fsl,pins = <
174	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
175	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
176	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
177	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
178	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
179	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
180	>;
181	};
182
183	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
184	fsl,pins = <
185	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
186	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
187	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
188	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
189	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
190	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
191	>;
192	};
193
194	pinctrl_usdhc2: usdhc2grp {
195	fsl,pins = <
196	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
197	MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
198	MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
199	MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
200	MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
201	MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
202	MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
203	MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
204	MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
205	MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
206	>;
207	};
208
209	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
210	fsl,pins = <
211	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
212	MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
213	MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
214	MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
215	MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
216	MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
217	MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
218	MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
219	MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
220	MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
221	>;
222	};
223
224	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
225	fsl,pins = <
226	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
227	MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
228	MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
229	MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
230	MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
231	MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
232	MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
233	MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
234	MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
235	MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
236	>;
237	};
238	};