projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 854d489e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 57cd681b TR |
2 | /* |
| 3 | * Device Tree Source for DRA7xx clock data | |
| 4 | * | |
| 5 | * Copyright (C) 2013 Texas Instruments, Inc. | |
| 57cd681b TR |
6 | */ |
| 7 | &cm_core_aon_clocks { | |
| f8ae3e60 | 8 | atl_clkin0_ck: clock-atl-clkin0 { |
| 57cd681b TR |
9 | #clock-cells = <0>; |
| 10 | compatible = "ti,dra7-atl-clock"; | |
| 11 | clocks = <&atl_gfclk_mux>; | |
| 12 | }; | |
| 13 | ||
| f8ae3e60 | 14 | atl_clkin1_ck: clock-atl-clkin1 { |
| 57cd681b TR |
15 | #clock-cells = <0>; |
| 16 | compatible = "ti,dra7-atl-clock"; | |
| 17 | clocks = <&atl_gfclk_mux>; | |
| 18 | }; | |
| 19 | ||
| f8ae3e60 | 20 | atl_clkin2_ck: clock-atl-clkin2 { |
| 57cd681b TR |
21 | #clock-cells = <0>; |
| 22 | compatible = "ti,dra7-atl-clock"; | |
| 23 | clocks = <&atl_gfclk_mux>; | |
| 24 | }; | |
| 25 | ||
| f8ae3e60 | 26 | atl_clkin3_ck: clock-atl-clkin3 { |
| 57cd681b TR |
27 | #clock-cells = <0>; |
| 28 | compatible = "ti,dra7-atl-clock"; | |
| 29 | clocks = <&atl_gfclk_mux>; | |
| 30 | }; | |
| 31 | ||
| f8ae3e60 | 32 | hdmi_clkin_ck: clock-hdmi-clkin { |
| 57cd681b TR |
33 | #clock-cells = <0>; |
| 34 | compatible = "fixed-clock"; | |
| 35 | clock-frequency = <0>; | |
| 36 | }; | |
| 37 | ||
| f8ae3e60 | 38 | mlb_clkin_ck: clock-mlb-clkin { |
| 57cd681b TR |
39 | #clock-cells = <0>; |
| 40 | compatible = "fixed-clock"; | |
| 41 | clock-frequency = <0>; | |
| 42 | }; | |
| 43 | ||
| f8ae3e60 | 44 | mlbp_clkin_ck: clock-mlbp-clkin { |
| 57cd681b TR |
45 | #clock-cells = <0>; |
| 46 | compatible = "fixed-clock"; | |
| 47 | clock-frequency = <0>; | |
| 48 | }; | |
| 49 | ||
| f8ae3e60 | 50 | pciesref_acs_clk_ck: clock-pciesref-acs { |
| 57cd681b TR |
51 | #clock-cells = <0>; |
| 52 | compatible = "fixed-clock"; | |
| 53 | clock-frequency = <100000000>; | |
| 54 | }; | |
| 55 | ||
| f8ae3e60 | 56 | ref_clkin0_ck: clock-ref-clkin0 { |
| 57cd681b TR |
57 | #clock-cells = <0>; |
| 58 | compatible = "fixed-clock"; | |
| 59 | clock-frequency = <0>; | |
| 60 | }; | |
| 61 | ||
| f8ae3e60 | 62 | ref_clkin1_ck: clock-ref-clkin1 { |
| 57cd681b TR |
63 | #clock-cells = <0>; |
| 64 | compatible = "fixed-clock"; | |
| 65 | clock-frequency = <0>; | |
| 66 | }; | |
| 67 | ||
| f8ae3e60 | 68 | ref_clkin2_ck: clock-ref-clkin2 { |
| 57cd681b TR |
69 | #clock-cells = <0>; |
| 70 | compatible = "fixed-clock"; | |
| 71 | clock-frequency = <0>; | |
| 72 | }; | |
| 73 | ||
| f8ae3e60 | 74 | ref_clkin3_ck: clock-ref-clkin3 { |
| 57cd681b TR |
75 | #clock-cells = <0>; |
| 76 | compatible = "fixed-clock"; | |
| 77 | clock-frequency = <0>; | |
| 78 | }; | |
| 79 | ||
| f8ae3e60 | 80 | rmii_clk_ck: clock-rmii { |
| 57cd681b TR |
81 | #clock-cells = <0>; |
| 82 | compatible = "fixed-clock"; | |
| 83 | clock-frequency = <0>; | |
| 84 | }; | |
| 85 | ||
| f8ae3e60 | 86 | sdvenc_clkin_ck: clock-sdvenc-clkin { |
| 57cd681b TR |
87 | #clock-cells = <0>; |
| 88 | compatible = "fixed-clock"; | |
| 89 | clock-frequency = <0>; | |
| 90 | }; | |
| 91 | ||
| f8ae3e60 | 92 | secure_32k_clk_src_ck: clock-secure-32k-clk-src { |
| 57cd681b TR |
93 | #clock-cells = <0>; |
| 94 | compatible = "fixed-clock"; | |
| 95 | clock-frequency = <32768>; | |
| 96 | }; | |
| 97 | ||
| f8ae3e60 | 98 | sys_clk32_crystal_ck: clock-sys-clk32-crystal { |
| 57cd681b TR |
99 | #clock-cells = <0>; |
| 100 | compatible = "fixed-clock"; | |
| 101 | clock-frequency = <32768>; | |
| 102 | }; | |
| 103 | ||
| f8ae3e60 | 104 | sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { |
| 7aa1a408 LV |
105 | #clock-cells = <0>; |
| 106 | compatible = "fixed-factor-clock"; | |
| 107 | clocks = <&sys_clkin1>; | |
| 108 | clock-mult = <1>; | |
| 109 | clock-div = <610>; | |
| 110 | }; | |
| 111 | ||
| f8ae3e60 | 112 | virt_12000000_ck: clock-virt-12000000 { |
| 57cd681b TR |
113 | #clock-cells = <0>; |
| 114 | compatible = "fixed-clock"; | |
| 115 | clock-frequency = <12000000>; | |
| 116 | }; | |
| 117 | ||
| f8ae3e60 | 118 | virt_13000000_ck: clock-virt-13000000 { |
| 57cd681b TR |
119 | #clock-cells = <0>; |
| 120 | compatible = "fixed-clock"; | |
| 121 | clock-frequency = <13000000>; | |
| 122 | }; | |
| 123 | ||
| f8ae3e60 | 124 | virt_16800000_ck: clock-virt-16800000 { |
| 57cd681b TR |
125 | #clock-cells = <0>; |
| 126 | compatible = "fixed-clock"; | |
| 127 | clock-frequency = <16800000>; | |
| 128 | }; | |
| 129 | ||
| f8ae3e60 | 130 | virt_19200000_ck: clock-virt-19200000 { |
| 57cd681b TR |
131 | #clock-cells = <0>; |
| 132 | compatible = "fixed-clock"; | |
| 133 | clock-frequency = <19200000>; | |
| 134 | }; | |
| 135 | ||
| f8ae3e60 | 136 | virt_20000000_ck: clock-virt-20000000 { |
| 57cd681b TR |
137 | #clock-cells = <0>; |
| 138 | compatible = "fixed-clock"; | |
| 139 | clock-frequency = <20000000>; | |
| 140 | }; | |
| 141 | ||
| f8ae3e60 | 142 | virt_26000000_ck: clock-virt-26000000 { |
| 57cd681b TR |
143 | #clock-cells = <0>; |
| 144 | compatible = "fixed-clock"; | |
| 145 | clock-frequency = <26000000>; | |
| 146 | }; | |
| 147 | ||
| f8ae3e60 | 148 | virt_27000000_ck: clock-virt-27000000 { |
| 57cd681b TR |
149 | #clock-cells = <0>; |
| 150 | compatible = "fixed-clock"; | |
| 151 | clock-frequency = <27000000>; | |
| 152 | }; | |
| 153 | ||
| f8ae3e60 | 154 | virt_38400000_ck: clock-virt-38400000 { |
| 57cd681b TR |
155 | #clock-cells = <0>; |
| 156 | compatible = "fixed-clock"; | |
| 157 | clock-frequency = <38400000>; | |
| 158 | }; | |
| 159 | ||
| f8ae3e60 | 160 | sys_clkin2: clock-sys-clkin2 { |
| 57cd681b TR |
161 | #clock-cells = <0>; |
| 162 | compatible = "fixed-clock"; | |
| 163 | clock-frequency = <22579200>; | |
| 164 | }; | |
| 165 | ||
| f8ae3e60 | 166 | usb_otg_clkin_ck: clock-usb-otg-clkin { |
| 57cd681b TR |
167 | #clock-cells = <0>; |
| 168 | compatible = "fixed-clock"; | |
| 169 | clock-frequency = <0>; | |
| 170 | }; | |
| 171 | ||
| f8ae3e60 | 172 | video1_clkin_ck: clock-video1-clkin { |
| 57cd681b TR |
173 | #clock-cells = <0>; |
| 174 | compatible = "fixed-clock"; | |
| 175 | clock-frequency = <0>; | |
| 176 | }; | |
| 177 | ||
| f8ae3e60 | 178 | video1_m2_clkin_ck: clock-video1-m2-clkin { |
| 57cd681b TR |
179 | #clock-cells = <0>; |
| 180 | compatible = "fixed-clock"; | |
| 181 | clock-frequency = <0>; | |
| 182 | }; | |
| 183 | ||
| f8ae3e60 | 184 | video2_clkin_ck: clock-video2-clkin { |
| 57cd681b TR |
185 | #clock-cells = <0>; |
| 186 | compatible = "fixed-clock"; | |
| 187 | clock-frequency = <0>; | |
| 188 | }; | |
| 189 | ||
| f8ae3e60 | 190 | video2_m2_clkin_ck: clock-video2-m2-clkin { |
| 57cd681b TR |
191 | #clock-cells = <0>; |
| 192 | compatible = "fixed-clock"; | |
| 193 | clock-frequency = <0>; | |
| 194 | }; | |
| 195 | ||
| f8ae3e60 | 196 | dpll_abe_ck: clock@1e0 { |
| 57cd681b TR |
197 | #clock-cells = <0>; |
| 198 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
| 199 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
| 200 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
| 201 | }; | |
| 202 | ||
| f8ae3e60 | 203 | dpll_abe_x2_ck: clock-dpll-abe-x2 { |
| 57cd681b TR |
204 | #clock-cells = <0>; |
| 205 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 206 | clocks = <&dpll_abe_ck>; | |
| 207 | }; | |
| 208 | ||
| f8ae3e60 | 209 | dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { |
| 57cd681b TR |
210 | #clock-cells = <0>; |
| 211 | compatible = "ti,divider-clock"; | |
| 212 | clocks = <&dpll_abe_x2_ck>; | |
| 213 | ti,max-div = <31>; | |
| 214 | ti,autoidle-shift = <8>; | |
| 215 | reg = <0x01f0>; | |
| 216 | ti,index-starts-at-one; | |
| 217 | ti,invert-autoidle-bit; | |
| 218 | }; | |
| 219 | ||
| f8ae3e60 | 220 | abe_clk: clock-abe@108 { |
| 57cd681b TR |
221 | #clock-cells = <0>; |
| 222 | compatible = "ti,divider-clock"; | |
| 223 | clocks = <&dpll_abe_m2x2_ck>; | |
| 224 | ti,max-div = <4>; | |
| 225 | reg = <0x0108>; | |
| 226 | ti,index-power-of-two; | |
| 227 | }; | |
| 228 | ||
| f8ae3e60 | 229 | dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { |
| 57cd681b TR |
230 | #clock-cells = <0>; |
| 231 | compatible = "ti,divider-clock"; | |
| 232 | clocks = <&dpll_abe_ck>; | |
| 233 | ti,max-div = <31>; | |
| 234 | ti,autoidle-shift = <8>; | |
| 235 | reg = <0x01f0>; | |
| 236 | ti,index-starts-at-one; | |
| 237 | ti,invert-autoidle-bit; | |
| 238 | }; | |
| 239 | ||
| f8ae3e60 | 240 | dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { |
| 57cd681b TR |
241 | #clock-cells = <0>; |
| 242 | compatible = "ti,divider-clock"; | |
| 243 | clocks = <&dpll_abe_x2_ck>; | |
| 244 | ti,max-div = <31>; | |
| 245 | ti,autoidle-shift = <8>; | |
| 246 | reg = <0x01f4>; | |
| 247 | ti,index-starts-at-one; | |
| 248 | ti,invert-autoidle-bit; | |
| 249 | }; | |
| 250 | ||
| f8ae3e60 | 251 | dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { |
| 57cd681b TR |
252 | #clock-cells = <0>; |
| 253 | compatible = "ti,mux-clock"; | |
| 254 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
| 255 | ti,bit-shift = <23>; | |
| 256 | reg = <0x012c>; | |
| 257 | }; | |
| 258 | ||
| f8ae3e60 | 259 | dpll_core_ck: clock@120 { |
| 57cd681b TR |
260 | #clock-cells = <0>; |
| 261 | compatible = "ti,omap4-dpll-core-clock"; | |
| 262 | clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; | |
| 263 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; | |
| 264 | }; | |
| 265 | ||
| f8ae3e60 | 266 | dpll_core_x2_ck: clock-dpll-core-x2 { |
| 57cd681b TR |
267 | #clock-cells = <0>; |
| 268 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 269 | clocks = <&dpll_core_ck>; | |
| 270 | }; | |
| 271 | ||
| f8ae3e60 | 272 | dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { |
| 57cd681b TR |
273 | #clock-cells = <0>; |
| 274 | compatible = "ti,divider-clock"; | |
| 275 | clocks = <&dpll_core_x2_ck>; | |
| 276 | ti,max-div = <63>; | |
| 277 | ti,autoidle-shift = <8>; | |
| 278 | reg = <0x013c>; | |
| 279 | ti,index-starts-at-one; | |
| 280 | ti,invert-autoidle-bit; | |
| 281 | }; | |
| 282 | ||
| f8ae3e60 | 283 | mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { |
| 57cd681b TR |
284 | #clock-cells = <0>; |
| 285 | compatible = "fixed-factor-clock"; | |
| 286 | clocks = <&dpll_core_h12x2_ck>; | |
| 287 | clock-mult = <1>; | |
| 288 | clock-div = <1>; | |
| 289 | }; | |
| 290 | ||
| f8ae3e60 | 291 | dpll_mpu_ck: clock@160 { |
| 57cd681b TR |
292 | #clock-cells = <0>; |
| 293 | compatible = "ti,omap5-mpu-dpll-clock"; | |
| 294 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; | |
| 295 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
| 296 | }; | |
| 297 | ||
| f8ae3e60 | 298 | dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { |
| 57cd681b TR |
299 | #clock-cells = <0>; |
| 300 | compatible = "ti,divider-clock"; | |
| 301 | clocks = <&dpll_mpu_ck>; | |
| 302 | ti,max-div = <31>; | |
| 303 | ti,autoidle-shift = <8>; | |
| 304 | reg = <0x0170>; | |
| 305 | ti,index-starts-at-one; | |
| 306 | ti,invert-autoidle-bit; | |
| 307 | }; | |
| 308 | ||
| f8ae3e60 | 309 | mpu_dclk_div: clock-mpu-dclk-div { |
| 57cd681b TR |
310 | #clock-cells = <0>; |
| 311 | compatible = "fixed-factor-clock"; | |
| 312 | clocks = <&dpll_mpu_m2_ck>; | |
| 313 | clock-mult = <1>; | |
| 314 | clock-div = <1>; | |
| 315 | }; | |
| 316 | ||
| f8ae3e60 | 317 | dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { |
| 57cd681b TR |
318 | #clock-cells = <0>; |
| 319 | compatible = "fixed-factor-clock"; | |
| 320 | clocks = <&dpll_core_h12x2_ck>; | |
| 321 | clock-mult = <1>; | |
| 322 | clock-div = <1>; | |
| 323 | }; | |
| 324 | ||
| f8ae3e60 | 325 | dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { |
| 57cd681b TR |
326 | #clock-cells = <0>; |
| 327 | compatible = "ti,mux-clock"; | |
| 328 | clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; | |
| 329 | ti,bit-shift = <23>; | |
| 330 | reg = <0x0240>; | |
| 331 | }; | |
| 332 | ||
| f8ae3e60 | 333 | dpll_dsp_ck: clock@234 { |
| 57cd681b TR |
334 | #clock-cells = <0>; |
| 335 | compatible = "ti,omap4-dpll-clock"; | |
| 336 | clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; | |
| 337 | reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; | |
| 4ddaa6ce LV |
338 | assigned-clocks = <&dpll_dsp_ck>; |
| 339 | assigned-clock-rates = <600000000>; | |
| 57cd681b TR |
340 | }; |
| 341 | ||
| f8ae3e60 | 342 | dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { |
| 57cd681b TR |
343 | #clock-cells = <0>; |
| 344 | compatible = "ti,divider-clock"; | |
| 345 | clocks = <&dpll_dsp_ck>; | |
| 346 | ti,max-div = <31>; | |
| 347 | ti,autoidle-shift = <8>; | |
| 348 | reg = <0x0244>; | |
| 349 | ti,index-starts-at-one; | |
| 350 | ti,invert-autoidle-bit; | |
| 4ddaa6ce LV |
351 | assigned-clocks = <&dpll_dsp_m2_ck>; |
| 352 | assigned-clock-rates = <600000000>; | |
| 57cd681b TR |
353 | }; |
| 354 | ||
| f8ae3e60 | 355 | iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { |
| 57cd681b TR |
356 | #clock-cells = <0>; |
| 357 | compatible = "fixed-factor-clock"; | |
| 358 | clocks = <&dpll_core_h12x2_ck>; | |
| 359 | clock-mult = <1>; | |
| 360 | clock-div = <1>; | |
| 361 | }; | |
| 362 | ||
| f8ae3e60 | 363 | dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { |
| 57cd681b TR |
364 | #clock-cells = <0>; |
| 365 | compatible = "ti,mux-clock"; | |
| 366 | clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; | |
| 367 | ti,bit-shift = <23>; | |
| 368 | reg = <0x01ac>; | |
| 369 | }; | |
| 370 | ||
| f8ae3e60 | 371 | dpll_iva_ck: clock@1a0 { |
| 57cd681b TR |
372 | #clock-cells = <0>; |
| 373 | compatible = "ti,omap4-dpll-clock"; | |
| 374 | clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; | |
| 375 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; | |
| 4ddaa6ce LV |
376 | assigned-clocks = <&dpll_iva_ck>; |
| 377 | assigned-clock-rates = <1165000000>; | |
| 57cd681b TR |
378 | }; |
| 379 | ||
| f8ae3e60 | 380 | dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { |
| 57cd681b TR |
381 | #clock-cells = <0>; |
| 382 | compatible = "ti,divider-clock"; | |
| 383 | clocks = <&dpll_iva_ck>; | |
| 384 | ti,max-div = <31>; | |
| 385 | ti,autoidle-shift = <8>; | |
| 386 | reg = <0x01b0>; | |
| 387 | ti,index-starts-at-one; | |
| 388 | ti,invert-autoidle-bit; | |
| 4ddaa6ce LV |
389 | assigned-clocks = <&dpll_iva_m2_ck>; |
| 390 | assigned-clock-rates = <388333334>; | |
| 57cd681b TR |
391 | }; |
| 392 | ||
| f8ae3e60 | 393 | iva_dclk: clock-iva-dclk { |
| 57cd681b TR |
394 | #clock-cells = <0>; |
| 395 | compatible = "fixed-factor-clock"; | |
| 396 | clocks = <&dpll_iva_m2_ck>; | |
| 397 | clock-mult = <1>; | |
| 398 | clock-div = <1>; | |
| 399 | }; | |
| 400 | ||
| f8ae3e60 | 401 | dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { |
| 57cd681b TR |
402 | #clock-cells = <0>; |
| 403 | compatible = "ti,mux-clock"; | |
| 404 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
| 405 | ti,bit-shift = <23>; | |
| 406 | reg = <0x02e4>; | |
| 407 | }; | |
| 408 | ||
| f8ae3e60 | 409 | dpll_gpu_ck: clock@2d8 { |
| 57cd681b TR |
410 | #clock-cells = <0>; |
| 411 | compatible = "ti,omap4-dpll-clock"; | |
| 412 | clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; | |
| 413 | reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; | |
| 4ddaa6ce LV |
414 | assigned-clocks = <&dpll_gpu_ck>; |
| 415 | assigned-clock-rates = <1277000000>; | |
| 57cd681b TR |
416 | }; |
| 417 | ||
| f8ae3e60 | 418 | dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { |
| 57cd681b TR |
419 | #clock-cells = <0>; |
| 420 | compatible = "ti,divider-clock"; | |
| 421 | clocks = <&dpll_gpu_ck>; | |
| 422 | ti,max-div = <31>; | |
| 423 | ti,autoidle-shift = <8>; | |
| 424 | reg = <0x02e8>; | |
| 425 | ti,index-starts-at-one; | |
| 426 | ti,invert-autoidle-bit; | |
| 4ddaa6ce LV |
427 | assigned-clocks = <&dpll_gpu_m2_ck>; |
| 428 | assigned-clock-rates = <425666667>; | |
| 57cd681b TR |
429 | }; |
| 430 | ||
| f8ae3e60 | 431 | dpll_core_m2_ck: clock-dpll-core-m2-8@130 { |
| 57cd681b TR |
432 | #clock-cells = <0>; |
| 433 | compatible = "ti,divider-clock"; | |
| 434 | clocks = <&dpll_core_ck>; | |
| 435 | ti,max-div = <31>; | |
| 436 | ti,autoidle-shift = <8>; | |
| 437 | reg = <0x0130>; | |
| 438 | ti,index-starts-at-one; | |
| 439 | ti,invert-autoidle-bit; | |
| 440 | }; | |
| 441 | ||
| f8ae3e60 | 442 | core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { |
| 57cd681b TR |
443 | #clock-cells = <0>; |
| 444 | compatible = "fixed-factor-clock"; | |
| 445 | clocks = <&dpll_core_m2_ck>; | |
| 446 | clock-mult = <1>; | |
| 447 | clock-div = <1>; | |
| 448 | }; | |
| 449 | ||
| f8ae3e60 | 450 | dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { |
| 57cd681b TR |
451 | #clock-cells = <0>; |
| 452 | compatible = "ti,mux-clock"; | |
| 453 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
| 454 | ti,bit-shift = <23>; | |
| 455 | reg = <0x021c>; | |
| 456 | }; | |
| 457 | ||
| f8ae3e60 | 458 | dpll_ddr_ck: clock@210 { |
| 57cd681b TR |
459 | #clock-cells = <0>; |
| 460 | compatible = "ti,omap4-dpll-clock"; | |
| 461 | clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; | |
| 462 | reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; | |
| 463 | }; | |
| 464 | ||
| f8ae3e60 | 465 | dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { |
| 57cd681b TR |
466 | #clock-cells = <0>; |
| 467 | compatible = "ti,divider-clock"; | |
| 468 | clocks = <&dpll_ddr_ck>; | |
| 469 | ti,max-div = <31>; | |
| 470 | ti,autoidle-shift = <8>; | |
| 471 | reg = <0x0220>; | |
| 472 | ti,index-starts-at-one; | |
| 473 | ti,invert-autoidle-bit; | |
| 474 | }; | |
| 475 | ||
| f8ae3e60 | 476 | dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { |
| 57cd681b TR |
477 | #clock-cells = <0>; |
| 478 | compatible = "ti,mux-clock"; | |
| 479 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
| 480 | ti,bit-shift = <23>; | |
| 481 | reg = <0x02b4>; | |
| 482 | }; | |
| 483 | ||
| f8ae3e60 | 484 | dpll_gmac_ck: clock@2a8 { |
| 57cd681b TR |
485 | #clock-cells = <0>; |
| 486 | compatible = "ti,omap4-dpll-clock"; | |
| 487 | clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; | |
| 488 | reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; | |
| 489 | }; | |
| 490 | ||
| f8ae3e60 | 491 | dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { |
| 57cd681b TR |
492 | #clock-cells = <0>; |
| 493 | compatible = "ti,divider-clock"; | |
| 494 | clocks = <&dpll_gmac_ck>; | |
| 495 | ti,max-div = <31>; | |
| 496 | ti,autoidle-shift = <8>; | |
| 497 | reg = <0x02b8>; | |
| 498 | ti,index-starts-at-one; | |
| 499 | ti,invert-autoidle-bit; | |
| 500 | }; | |
| 501 | ||
| f8ae3e60 | 502 | video2_dclk_div: clock-video2-dclk-div { |
| 57cd681b TR |
503 | #clock-cells = <0>; |
| 504 | compatible = "fixed-factor-clock"; | |
| 505 | clocks = <&video2_m2_clkin_ck>; | |
| 506 | clock-mult = <1>; | |
| 507 | clock-div = <1>; | |
| 508 | }; | |
| 509 | ||
| f8ae3e60 | 510 | video1_dclk_div: clock-video1-dclk-div { |
| 57cd681b TR |
511 | #clock-cells = <0>; |
| 512 | compatible = "fixed-factor-clock"; | |
| 513 | clocks = <&video1_m2_clkin_ck>; | |
| 514 | clock-mult = <1>; | |
| 515 | clock-div = <1>; | |
| 516 | }; | |
| 517 | ||
| f8ae3e60 | 518 | hdmi_dclk_div: clock-hdmi-dclk-div { |
| 57cd681b TR |
519 | #clock-cells = <0>; |
| 520 | compatible = "fixed-factor-clock"; | |
| 521 | clocks = <&hdmi_clkin_ck>; | |
| 522 | clock-mult = <1>; | |
| 523 | clock-div = <1>; | |
| 524 | }; | |
| 525 | ||
| f8ae3e60 | 526 | per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { |
| 57cd681b TR |
527 | #clock-cells = <0>; |
| 528 | compatible = "fixed-factor-clock"; | |
| 529 | clocks = <&dpll_abe_m3x2_ck>; | |
| 530 | clock-mult = <1>; | |
| 531 | clock-div = <2>; | |
| 532 | }; | |
| 533 | ||
| f8ae3e60 | 534 | usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { |
| 57cd681b TR |
535 | #clock-cells = <0>; |
| 536 | compatible = "fixed-factor-clock"; | |
| 537 | clocks = <&dpll_abe_m3x2_ck>; | |
| 538 | clock-mult = <1>; | |
| 539 | clock-div = <3>; | |
| 540 | }; | |
| 541 | ||
| f8ae3e60 | 542 | eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { |
| 57cd681b TR |
543 | #clock-cells = <0>; |
| 544 | compatible = "fixed-factor-clock"; | |
| 545 | clocks = <&dpll_core_h12x2_ck>; | |
| 546 | clock-mult = <1>; | |
| 547 | clock-div = <1>; | |
| 548 | }; | |
| 549 | ||
| f8ae3e60 | 550 | dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { |
| 57cd681b TR |
551 | #clock-cells = <0>; |
| 552 | compatible = "ti,mux-clock"; | |
| 553 | clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; | |
| 554 | ti,bit-shift = <23>; | |
| 555 | reg = <0x0290>; | |
| 556 | }; | |
| 557 | ||
| f8ae3e60 | 558 | dpll_eve_ck: clock@284 { |
| 57cd681b TR |
559 | #clock-cells = <0>; |
| 560 | compatible = "ti,omap4-dpll-clock"; | |
| 561 | clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; | |
| 562 | reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; | |
| 563 | }; | |
| 564 | ||
| f8ae3e60 | 565 | dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { |
| 57cd681b TR |
566 | #clock-cells = <0>; |
| 567 | compatible = "ti,divider-clock"; | |
| 568 | clocks = <&dpll_eve_ck>; | |
| 569 | ti,max-div = <31>; | |
| 570 | ti,autoidle-shift = <8>; | |
| 571 | reg = <0x0294>; | |
| 572 | ti,index-starts-at-one; | |
| 573 | ti,invert-autoidle-bit; | |
| 574 | }; | |
| 575 | ||
| f8ae3e60 | 576 | eve_dclk_div: clock-eve-dclk-div { |
| 57cd681b TR |
577 | #clock-cells = <0>; |
| 578 | compatible = "fixed-factor-clock"; | |
| 579 | clocks = <&dpll_eve_m2_ck>; | |
| 580 | clock-mult = <1>; | |
| 581 | clock-div = <1>; | |
| 582 | }; | |
| 583 | ||
| f8ae3e60 | 584 | dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { |
| 57cd681b TR |
585 | #clock-cells = <0>; |
| 586 | compatible = "ti,divider-clock"; | |
| 587 | clocks = <&dpll_core_x2_ck>; | |
| 588 | ti,max-div = <63>; | |
| 589 | ti,autoidle-shift = <8>; | |
| 590 | reg = <0x0140>; | |
| 591 | ti,index-starts-at-one; | |
| 592 | ti,invert-autoidle-bit; | |
| 593 | }; | |
| 594 | ||
| f8ae3e60 | 595 | dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { |
| 57cd681b TR |
596 | #clock-cells = <0>; |
| 597 | compatible = "ti,divider-clock"; | |
| 598 | clocks = <&dpll_core_x2_ck>; | |
| 599 | ti,max-div = <63>; | |
| 600 | ti,autoidle-shift = <8>; | |
| 601 | reg = <0x0144>; | |
| 602 | ti,index-starts-at-one; | |
| 603 | ti,invert-autoidle-bit; | |
| 604 | }; | |
| 605 | ||
| f8ae3e60 | 606 | dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { |
| 57cd681b TR |
607 | #clock-cells = <0>; |
| 608 | compatible = "ti,divider-clock"; | |
| 609 | clocks = <&dpll_core_x2_ck>; | |
| 610 | ti,max-div = <63>; | |
| 611 | ti,autoidle-shift = <8>; | |
| 612 | reg = <0x0154>; | |
| 613 | ti,index-starts-at-one; | |
| 614 | ti,invert-autoidle-bit; | |
| 615 | }; | |
| 616 | ||
| f8ae3e60 | 617 | dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { |
| 57cd681b TR |
618 | #clock-cells = <0>; |
| 619 | compatible = "ti,divider-clock"; | |
| 620 | clocks = <&dpll_core_x2_ck>; | |
| 621 | ti,max-div = <63>; | |
| 622 | ti,autoidle-shift = <8>; | |
| 623 | reg = <0x0158>; | |
| 624 | ti,index-starts-at-one; | |
| 625 | ti,invert-autoidle-bit; | |
| 626 | }; | |
| 627 | ||
| f8ae3e60 | 628 | dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { |
| 57cd681b TR |
629 | #clock-cells = <0>; |
| 630 | compatible = "ti,divider-clock"; | |
| 631 | clocks = <&dpll_core_x2_ck>; | |
| 632 | ti,max-div = <63>; | |
| 633 | ti,autoidle-shift = <8>; | |
| 634 | reg = <0x015c>; | |
| 635 | ti,index-starts-at-one; | |
| 636 | ti,invert-autoidle-bit; | |
| 637 | }; | |
| 638 | ||
| f8ae3e60 | 639 | dpll_ddr_x2_ck: clock-dpll-ddr-x2 { |
| 57cd681b TR |
640 | #clock-cells = <0>; |
| 641 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 642 | clocks = <&dpll_ddr_ck>; | |
| 643 | }; | |
| 644 | ||
| f8ae3e60 | 645 | dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { |
| 57cd681b TR |
646 | #clock-cells = <0>; |
| 647 | compatible = "ti,divider-clock"; | |
| 648 | clocks = <&dpll_ddr_x2_ck>; | |
| 649 | ti,max-div = <63>; | |
| 650 | ti,autoidle-shift = <8>; | |
| 651 | reg = <0x0228>; | |
| 652 | ti,index-starts-at-one; | |
| 653 | ti,invert-autoidle-bit; | |
| 654 | }; | |
| 655 | ||
| f8ae3e60 | 656 | dpll_dsp_x2_ck: clock-dpll-dsp-x2 { |
| 57cd681b TR |
657 | #clock-cells = <0>; |
| 658 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 659 | clocks = <&dpll_dsp_ck>; | |
| 660 | }; | |
| 661 | ||
| f8ae3e60 | 662 | dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { |
| 57cd681b TR |
663 | #clock-cells = <0>; |
| 664 | compatible = "ti,divider-clock"; | |
| 665 | clocks = <&dpll_dsp_x2_ck>; | |
| 666 | ti,max-div = <31>; | |
| 667 | ti,autoidle-shift = <8>; | |
| 668 | reg = <0x0248>; | |
| 669 | ti,index-starts-at-one; | |
| 670 | ti,invert-autoidle-bit; | |
| 4ddaa6ce LV |
671 | assigned-clocks = <&dpll_dsp_m3x2_ck>; |
| 672 | assigned-clock-rates = <400000000>; | |
| 57cd681b TR |
673 | }; |
| 674 | ||
| f8ae3e60 | 675 | dpll_gmac_x2_ck: clock-dpll-gmac-x2 { |
| 57cd681b TR |
676 | #clock-cells = <0>; |
| 677 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 678 | clocks = <&dpll_gmac_ck>; | |
| 679 | }; | |
| 680 | ||
| f8ae3e60 | 681 | dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { |
| 57cd681b TR |
682 | #clock-cells = <0>; |
| 683 | compatible = "ti,divider-clock"; | |
| 684 | clocks = <&dpll_gmac_x2_ck>; | |
| 685 | ti,max-div = <63>; | |
| 686 | ti,autoidle-shift = <8>; | |
| 687 | reg = <0x02c0>; | |
| 688 | ti,index-starts-at-one; | |
| 689 | ti,invert-autoidle-bit; | |
| 690 | }; | |
| 691 | ||
| f8ae3e60 | 692 | dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { |
| 57cd681b TR |
693 | #clock-cells = <0>; |
| 694 | compatible = "ti,divider-clock"; | |
| 695 | clocks = <&dpll_gmac_x2_ck>; | |
| 696 | ti,max-div = <63>; | |
| 697 | ti,autoidle-shift = <8>; | |
| 698 | reg = <0x02c4>; | |
| 699 | ti,index-starts-at-one; | |
| 700 | ti,invert-autoidle-bit; | |
| 701 | }; | |
| 702 | ||
| f8ae3e60 | 703 | dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { |
| 57cd681b TR |
704 | #clock-cells = <0>; |
| 705 | compatible = "ti,divider-clock"; | |
| 706 | clocks = <&dpll_gmac_x2_ck>; | |
| 707 | ti,max-div = <63>; | |
| 708 | ti,autoidle-shift = <8>; | |
| 709 | reg = <0x02c8>; | |
| 710 | ti,index-starts-at-one; | |
| 711 | ti,invert-autoidle-bit; | |
| 712 | }; | |
| 713 | ||
| f8ae3e60 | 714 | dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { |
| 57cd681b TR |
715 | #clock-cells = <0>; |
| 716 | compatible = "ti,divider-clock"; | |
| 717 | clocks = <&dpll_gmac_x2_ck>; | |
| 718 | ti,max-div = <31>; | |
| 719 | ti,autoidle-shift = <8>; | |
| 720 | reg = <0x02bc>; | |
| 721 | ti,index-starts-at-one; | |
| 722 | ti,invert-autoidle-bit; | |
| 723 | }; | |
| 724 | ||
| f8ae3e60 | 725 | gmii_m_clk_div: clock-gmii-m-clk-div { |
| 57cd681b TR |
726 | #clock-cells = <0>; |
| 727 | compatible = "fixed-factor-clock"; | |
| 728 | clocks = <&dpll_gmac_h11x2_ck>; | |
| 729 | clock-mult = <1>; | |
| 730 | clock-div = <2>; | |
| 731 | }; | |
| 732 | ||
| f8ae3e60 | 733 | hdmi_clk2_div: clock-hdmi-clk2-div { |
| 57cd681b TR |
734 | #clock-cells = <0>; |
| 735 | compatible = "fixed-factor-clock"; | |
| 736 | clocks = <&hdmi_clkin_ck>; | |
| 737 | clock-mult = <1>; | |
| 738 | clock-div = <1>; | |
| 739 | }; | |
| 740 | ||
| f8ae3e60 | 741 | hdmi_div_clk: clock-hdmi-div { |
| 57cd681b TR |
742 | #clock-cells = <0>; |
| 743 | compatible = "fixed-factor-clock"; | |
| 744 | clocks = <&hdmi_clkin_ck>; | |
| 745 | clock-mult = <1>; | |
| 746 | clock-div = <1>; | |
| 747 | }; | |
| 748 | ||
| f8ae3e60 | 749 | l3_iclk_div: clock-l3-iclk-div-4@100 { |
| 57cd681b TR |
750 | #clock-cells = <0>; |
| 751 | compatible = "ti,divider-clock"; | |
| 752 | ti,max-div = <2>; | |
| 753 | ti,bit-shift = <4>; | |
| 754 | reg = <0x0100>; | |
| 755 | clocks = <&dpll_core_h12x2_ck>; | |
| 756 | ti,index-power-of-two; | |
| 757 | }; | |
| 758 | ||
| f8ae3e60 | 759 | l4_root_clk_div: clock-l4-root-clk-div { |
| 57cd681b TR |
760 | #clock-cells = <0>; |
| 761 | compatible = "fixed-factor-clock"; | |
| 762 | clocks = <&l3_iclk_div>; | |
| 763 | clock-mult = <1>; | |
| 764 | clock-div = <2>; | |
| 765 | }; | |
| 766 | ||
| f8ae3e60 | 767 | video1_clk2_div: clock-video1-clk2-div { |
| 57cd681b TR |
768 | #clock-cells = <0>; |
| 769 | compatible = "fixed-factor-clock"; | |
| 770 | clocks = <&video1_clkin_ck>; | |
| 771 | clock-mult = <1>; | |
| 772 | clock-div = <1>; | |
| 773 | }; | |
| 774 | ||
| f8ae3e60 | 775 | video1_div_clk: clock-video1-div { |
| 57cd681b TR |
776 | #clock-cells = <0>; |
| 777 | compatible = "fixed-factor-clock"; | |
| 778 | clocks = <&video1_clkin_ck>; | |
| 779 | clock-mult = <1>; | |
| 780 | clock-div = <1>; | |
| 781 | }; | |
| 782 | ||
| f8ae3e60 | 783 | video2_clk2_div: clock-video2-clk2-div { |
| 57cd681b TR |
784 | #clock-cells = <0>; |
| 785 | compatible = "fixed-factor-clock"; | |
| 786 | clocks = <&video2_clkin_ck>; | |
| 787 | clock-mult = <1>; | |
| 788 | clock-div = <1>; | |
| 789 | }; | |
| 790 | ||
| f8ae3e60 | 791 | video2_div_clk: clock-video2-div { |
| 57cd681b TR |
792 | #clock-cells = <0>; |
| 793 | compatible = "fixed-factor-clock"; | |
| 794 | clocks = <&video2_clkin_ck>; | |
| 795 | clock-mult = <1>; | |
| 796 | clock-div = <1>; | |
| 797 | }; | |
| 798 | ||
| 7aa1a408 | 799 | ipu1_gfclk_mux: ipu1_gfclk_mux@520 { |
| 57cd681b TR |
800 | #clock-cells = <0>; |
| 801 | compatible = "ti,mux-clock"; | |
| 802 | clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; | |
| 803 | ti,bit-shift = <24>; | |
| 804 | reg = <0x0520>; | |
| 4ddaa6ce LV |
805 | assigned-clocks = <&ipu1_gfclk_mux>; |
| 806 | assigned-clock-parents = <&dpll_core_h22x2_ck>; | |
| 57cd681b TR |
807 | }; |
| 808 | ||
| 7aa1a408 | 809 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { |
| 57cd681b TR |
810 | #clock-cells = <0>; |
| 811 | compatible = "ti,mux-clock"; | |
| 812 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 813 | ti,bit-shift = <28>; | |
| 814 | reg = <0x0550>; | |
| 815 | }; | |
| 816 | ||
| 7aa1a408 | 817 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 { |
| 57cd681b TR |
818 | #clock-cells = <0>; |
| 819 | compatible = "ti,mux-clock"; | |
| 820 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 821 | ti,bit-shift = <24>; | |
| 822 | reg = <0x0550>; | |
| 823 | }; | |
| 824 | ||
| 7aa1a408 | 825 | mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 { |
| 57cd681b TR |
826 | #clock-cells = <0>; |
| 827 | compatible = "ti,mux-clock"; | |
| 828 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 829 | ti,bit-shift = <22>; | |
| 830 | reg = <0x0550>; | |
| 831 | }; | |
| 832 | ||
| 7aa1a408 | 833 | timer5_gfclk_mux: timer5_gfclk_mux@558 { |
| 57cd681b TR |
834 | #clock-cells = <0>; |
| 835 | compatible = "ti,mux-clock"; | |
| 836 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
| 837 | ti,bit-shift = <24>; | |
| 838 | reg = <0x0558>; | |
| 839 | }; | |
| 840 | ||
| 7aa1a408 | 841 | timer6_gfclk_mux: timer6_gfclk_mux@560 { |
| 57cd681b TR |
842 | #clock-cells = <0>; |
| 843 | compatible = "ti,mux-clock"; | |
| 844 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
| 845 | ti,bit-shift = <24>; | |
| 846 | reg = <0x0560>; | |
| 847 | }; | |
| 848 | ||
| 7aa1a408 | 849 | timer7_gfclk_mux: timer7_gfclk_mux@568 { |
| 57cd681b TR |
850 | #clock-cells = <0>; |
| 851 | compatible = "ti,mux-clock"; | |
| 852 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
| 853 | ti,bit-shift = <24>; | |
| 854 | reg = <0x0568>; | |
| 855 | }; | |
| 856 | ||
| 7aa1a408 | 857 | timer8_gfclk_mux: timer8_gfclk_mux@570 { |
| 57cd681b TR |
858 | #clock-cells = <0>; |
| 859 | compatible = "ti,mux-clock"; | |
| 860 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
| 861 | ti,bit-shift = <24>; | |
| 862 | reg = <0x0570>; | |
| 863 | }; | |
| 864 | ||
| 7aa1a408 | 865 | uart6_gfclk_mux: uart6_gfclk_mux@580 { |
| 57cd681b TR |
866 | #clock-cells = <0>; |
| 867 | compatible = "ti,mux-clock"; | |
| 868 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 869 | ti,bit-shift = <24>; | |
| 870 | reg = <0x0580>; | |
| 871 | }; | |
| 872 | ||
| f8ae3e60 | 873 | dummy_ck: clock-dummy { |
| 57cd681b TR |
874 | #clock-cells = <0>; |
| 875 | compatible = "fixed-clock"; | |
| 876 | clock-frequency = <0>; | |
| 877 | }; | |
| 878 | }; | |
| 879 | &prm_clocks { | |
| f8ae3e60 | 880 | sys_clkin1: clock-sys-clkin1@110 { |
| 57cd681b TR |
881 | #clock-cells = <0>; |
| 882 | compatible = "ti,mux-clock"; | |
| 883 | clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
| 884 | reg = <0x0110>; | |
| 885 | ti,index-starts-at-one; | |
| 886 | }; | |
| 887 | ||
| f8ae3e60 | 888 | abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { |
| 57cd681b TR |
889 | #clock-cells = <0>; |
| 890 | compatible = "ti,mux-clock"; | |
| 891 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
| 892 | reg = <0x0118>; | |
| 893 | }; | |
| 894 | ||
| f8ae3e60 | 895 | abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { |
| 57cd681b TR |
896 | #clock-cells = <0>; |
| 897 | compatible = "ti,mux-clock"; | |
| 898 | clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; | |
| 899 | reg = <0x0114>; | |
| 900 | }; | |
| 901 | ||
| f8ae3e60 | 902 | abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { |
| 57cd681b TR |
903 | #clock-cells = <0>; |
| 904 | compatible = "ti,mux-clock"; | |
| 905 | clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; | |
| 906 | reg = <0x010c>; | |
| 907 | }; | |
| 908 | ||
| f8ae3e60 | 909 | abe_24m_fclk: clock-abe-24m@11c { |
| 57cd681b TR |
910 | #clock-cells = <0>; |
| 911 | compatible = "ti,divider-clock"; | |
| 912 | clocks = <&dpll_abe_m2x2_ck>; | |
| 913 | reg = <0x011c>; | |
| 914 | ti,dividers = <8>, <16>; | |
| 915 | }; | |
| 916 | ||
| f8ae3e60 | 917 | aess_fclk: clock-aess@178 { |
| 57cd681b TR |
918 | #clock-cells = <0>; |
| 919 | compatible = "ti,divider-clock"; | |
| 920 | clocks = <&abe_clk>; | |
| 921 | reg = <0x0178>; | |
| 922 | ti,max-div = <2>; | |
| 923 | }; | |
| 924 | ||
| f8ae3e60 | 925 | abe_giclk_div: clock-abe-giclk-div@174 { |
| 57cd681b TR |
926 | #clock-cells = <0>; |
| 927 | compatible = "ti,divider-clock"; | |
| 928 | clocks = <&aess_fclk>; | |
| 929 | reg = <0x0174>; | |
| 930 | ti,max-div = <2>; | |
| 931 | }; | |
| 932 | ||
| f8ae3e60 | 933 | abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { |
| 57cd681b TR |
934 | #clock-cells = <0>; |
| 935 | compatible = "ti,divider-clock"; | |
| 936 | clocks = <&dpll_abe_m2x2_ck>; | |
| 937 | reg = <0x01d8>; | |
| 938 | ti,dividers = <16>, <32>; | |
| 939 | }; | |
| 940 | ||
| f8ae3e60 | 941 | abe_sys_clk_div: clock-abe-sys-clk-div@120 { |
| 57cd681b TR |
942 | #clock-cells = <0>; |
| 943 | compatible = "ti,divider-clock"; | |
| 944 | clocks = <&sys_clkin1>; | |
| 945 | reg = <0x0120>; | |
| 946 | ti,max-div = <2>; | |
| 947 | }; | |
| 948 | ||
| f8ae3e60 | 949 | adc_gfclk_mux: clock-adc-gfclk-mux@1dc { |
| 57cd681b TR |
950 | #clock-cells = <0>; |
| 951 | compatible = "ti,mux-clock"; | |
| 952 | clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; | |
| 953 | reg = <0x01dc>; | |
| 954 | }; | |
| 955 | ||
| f8ae3e60 | 956 | sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { |
| 57cd681b TR |
957 | #clock-cells = <0>; |
| 958 | compatible = "ti,divider-clock"; | |
| 959 | clocks = <&sys_clkin1>; | |
| 960 | ti,max-div = <64>; | |
| 961 | reg = <0x01c8>; | |
| 962 | ti,index-power-of-two; | |
| 963 | }; | |
| 964 | ||
| f8ae3e60 | 965 | sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { |
| 57cd681b TR |
966 | #clock-cells = <0>; |
| 967 | compatible = "ti,divider-clock"; | |
| 968 | clocks = <&sys_clkin2>; | |
| 969 | ti,max-div = <64>; | |
| 970 | reg = <0x01cc>; | |
| 971 | ti,index-power-of-two; | |
| 972 | }; | |
| 973 | ||
| f8ae3e60 | 974 | per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { |
| 57cd681b TR |
975 | #clock-cells = <0>; |
| 976 | compatible = "ti,divider-clock"; | |
| 977 | clocks = <&dpll_abe_m2_ck>; | |
| 978 | ti,max-div = <64>; | |
| 979 | reg = <0x01bc>; | |
| 980 | ti,index-power-of-two; | |
| 981 | }; | |
| 982 | ||
| f8ae3e60 | 983 | dsp_gclk_div: clock-dsp-gclk-div@18c { |
| 57cd681b TR |
984 | #clock-cells = <0>; |
| 985 | compatible = "ti,divider-clock"; | |
| 986 | clocks = <&dpll_dsp_m2_ck>; | |
| 987 | ti,max-div = <64>; | |
| 988 | reg = <0x018c>; | |
| 989 | ti,index-power-of-two; | |
| 990 | }; | |
| 991 | ||
| f8ae3e60 | 992 | gpu_dclk: clock-gpu-dclk@1a0 { |
| 57cd681b TR |
993 | #clock-cells = <0>; |
| 994 | compatible = "ti,divider-clock"; | |
| 995 | clocks = <&dpll_gpu_m2_ck>; | |
| 996 | ti,max-div = <64>; | |
| 997 | reg = <0x01a0>; | |
| 998 | ti,index-power-of-two; | |
| 999 | }; | |
| 1000 | ||
| f8ae3e60 | 1001 | emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { |
| 57cd681b TR |
1002 | #clock-cells = <0>; |
| 1003 | compatible = "ti,divider-clock"; | |
| 1004 | clocks = <&dpll_ddr_m2_ck>; | |
| 1005 | ti,max-div = <64>; | |
| 1006 | reg = <0x0190>; | |
| 1007 | ti,index-power-of-two; | |
| 1008 | }; | |
| 1009 | ||
| f8ae3e60 | 1010 | gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { |
| 57cd681b TR |
1011 | #clock-cells = <0>; |
| 1012 | compatible = "ti,divider-clock"; | |
| 1013 | clocks = <&dpll_gmac_m2_ck>; | |
| 1014 | ti,max-div = <64>; | |
| 1015 | reg = <0x019c>; | |
| 1016 | ti,index-power-of-two; | |
| 1017 | }; | |
| 1018 | ||
| f8ae3e60 | 1019 | gmac_main_clk: clock-gmac-main { |
| 7aa1a408 LV |
1020 | #clock-cells = <0>; |
| 1021 | compatible = "fixed-factor-clock"; | |
| 1022 | clocks = <&gmac_250m_dclk_div>; | |
| 1023 | clock-mult = <1>; | |
| 1024 | clock-div = <2>; | |
| 1025 | }; | |
| 1026 | ||
| f8ae3e60 | 1027 | l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { |
| 57cd681b TR |
1028 | #clock-cells = <0>; |
| 1029 | compatible = "ti,divider-clock"; | |
| 1030 | clocks = <&dpll_usb_m2_ck>; | |
| 1031 | ti,max-div = <64>; | |
| 1032 | reg = <0x01ac>; | |
| 1033 | ti,index-power-of-two; | |
| 1034 | }; | |
| 1035 | ||
| f8ae3e60 | 1036 | usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { |
| 57cd681b TR |
1037 | #clock-cells = <0>; |
| 1038 | compatible = "ti,divider-clock"; | |
| 1039 | clocks = <&usb_otg_clkin_ck>; | |
| 1040 | ti,max-div = <64>; | |
| 1041 | reg = <0x0184>; | |
| 1042 | ti,index-power-of-two; | |
| 1043 | }; | |
| 1044 | ||
| f8ae3e60 | 1045 | sata_dclk_div: clock-sata-dclk-div@1c0 { |
| 57cd681b TR |
1046 | #clock-cells = <0>; |
| 1047 | compatible = "ti,divider-clock"; | |
| 1048 | clocks = <&sys_clkin1>; | |
| 1049 | ti,max-div = <64>; | |
| 1050 | reg = <0x01c0>; | |
| 1051 | ti,index-power-of-two; | |
| 1052 | }; | |
| 1053 | ||
| f8ae3e60 | 1054 | pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { |
| 57cd681b TR |
1055 | #clock-cells = <0>; |
| 1056 | compatible = "ti,divider-clock"; | |
| 1057 | clocks = <&dpll_pcie_ref_m2_ck>; | |
| 1058 | ti,max-div = <64>; | |
| 1059 | reg = <0x01b8>; | |
| 1060 | ti,index-power-of-two; | |
| 1061 | }; | |
| 1062 | ||
| f8ae3e60 | 1063 | pcie_dclk_div: clock-pcie-dclk-div@1b4 { |
| 57cd681b TR |
1064 | #clock-cells = <0>; |
| 1065 | compatible = "ti,divider-clock"; | |
| 1066 | clocks = <&apll_pcie_m2_ck>; | |
| 1067 | ti,max-div = <64>; | |
| 1068 | reg = <0x01b4>; | |
| 1069 | ti,index-power-of-two; | |
| 1070 | }; | |
| 1071 | ||
| f8ae3e60 | 1072 | emu_dclk_div: clock-emu-dclk-div@194 { |
| 57cd681b TR |
1073 | #clock-cells = <0>; |
| 1074 | compatible = "ti,divider-clock"; | |
| 1075 | clocks = <&sys_clkin1>; | |
| 1076 | ti,max-div = <64>; | |
| 1077 | reg = <0x0194>; | |
| 1078 | ti,index-power-of-two; | |
| 1079 | }; | |
| 1080 | ||
| f8ae3e60 | 1081 | secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { |
| 57cd681b TR |
1082 | #clock-cells = <0>; |
| 1083 | compatible = "ti,divider-clock"; | |
| 1084 | clocks = <&secure_32k_clk_src_ck>; | |
| 1085 | ti,max-div = <64>; | |
| 1086 | reg = <0x01c4>; | |
| 1087 | ti,index-power-of-two; | |
| 1088 | }; | |
| 1089 | ||
| f8ae3e60 | 1090 | clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { |
| 57cd681b TR |
1091 | #clock-cells = <0>; |
| 1092 | compatible = "ti,mux-clock"; | |
| 1093 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
| 1094 | reg = <0x0158>; | |
| 1095 | }; | |
| 1096 | ||
| f8ae3e60 | 1097 | clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { |
| 57cd681b TR |
1098 | #clock-cells = <0>; |
| 1099 | compatible = "ti,mux-clock"; | |
| 1100 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
| 1101 | reg = <0x015c>; | |
| 1102 | }; | |
| 1103 | ||
| f8ae3e60 | 1104 | clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { |
| 57cd681b TR |
1105 | #clock-cells = <0>; |
| 1106 | compatible = "ti,mux-clock"; | |
| 1107 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
| 1108 | reg = <0x0160>; | |
| 1109 | }; | |
| 1110 | ||
| f8ae3e60 | 1111 | custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { |
| 57cd681b TR |
1112 | #clock-cells = <0>; |
| 1113 | compatible = "fixed-factor-clock"; | |
| 1114 | clocks = <&sys_clkin1>; | |
| 1115 | clock-mult = <1>; | |
| 1116 | clock-div = <2>; | |
| 1117 | }; | |
| 1118 | ||
| f8ae3e60 | 1119 | eve_clk: clock-eve@180 { |
| 57cd681b TR |
1120 | #clock-cells = <0>; |
| 1121 | compatible = "ti,mux-clock"; | |
| 1122 | clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; | |
| 1123 | reg = <0x0180>; | |
| 1124 | }; | |
| 1125 | ||
| f8ae3e60 | 1126 | hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { |
| 57cd681b TR |
1127 | #clock-cells = <0>; |
| 1128 | compatible = "ti,mux-clock"; | |
| 1129 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
| 1130 | reg = <0x0164>; | |
| 1131 | }; | |
| 1132 | ||
| f8ae3e60 | 1133 | mlb_clk: clock-mlb@134 { |
| 57cd681b TR |
1134 | #clock-cells = <0>; |
| 1135 | compatible = "ti,divider-clock"; | |
| 1136 | clocks = <&mlb_clkin_ck>; | |
| 1137 | ti,max-div = <64>; | |
| 1138 | reg = <0x0134>; | |
| 1139 | ti,index-power-of-two; | |
| 1140 | }; | |
| 1141 | ||
| f8ae3e60 | 1142 | mlbp_clk: clock-mlbp@130 { |
| 57cd681b TR |
1143 | #clock-cells = <0>; |
| 1144 | compatible = "ti,divider-clock"; | |
| 1145 | clocks = <&mlbp_clkin_ck>; | |
| 1146 | ti,max-div = <64>; | |
| 1147 | reg = <0x0130>; | |
| 1148 | ti,index-power-of-two; | |
| 1149 | }; | |
| 1150 | ||
| f8ae3e60 | 1151 | per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { |
| 57cd681b TR |
1152 | #clock-cells = <0>; |
| 1153 | compatible = "ti,divider-clock"; | |
| 1154 | clocks = <&dpll_abe_m2_ck>; | |
| 1155 | ti,max-div = <64>; | |
| 1156 | reg = <0x0138>; | |
| 1157 | ti,index-power-of-two; | |
| 1158 | }; | |
| 1159 | ||
| f8ae3e60 | 1160 | timer_sys_clk_div: clock-timer-sys-clk-div@144 { |
| 57cd681b TR |
1161 | #clock-cells = <0>; |
| 1162 | compatible = "ti,divider-clock"; | |
| 1163 | clocks = <&sys_clkin1>; | |
| 1164 | reg = <0x0144>; | |
| 1165 | ti,max-div = <2>; | |
| 1166 | }; | |
| 1167 | ||
| f8ae3e60 | 1168 | video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { |
| 57cd681b TR |
1169 | #clock-cells = <0>; |
| 1170 | compatible = "ti,mux-clock"; | |
| 1171 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
| 1172 | reg = <0x0168>; | |
| 1173 | }; | |
| 1174 | ||
| f8ae3e60 | 1175 | video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { |
| 57cd681b TR |
1176 | #clock-cells = <0>; |
| 1177 | compatible = "ti,mux-clock"; | |
| 1178 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
| 1179 | reg = <0x016c>; | |
| 1180 | }; | |
| 1181 | ||
| f8ae3e60 | 1182 | wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { |
| 57cd681b TR |
1183 | #clock-cells = <0>; |
| 1184 | compatible = "ti,mux-clock"; | |
| 1185 | clocks = <&sys_clkin1>, <&abe_lp_clk_div>; | |
| 1186 | reg = <0x0108>; | |
| 1187 | }; | |
| 1188 | ||
| 7aa1a408 | 1189 | gpio1_dbclk: gpio1_dbclk@1838 { |
| 57cd681b TR |
1190 | #clock-cells = <0>; |
| 1191 | compatible = "ti,gate-clock"; | |
| 1192 | clocks = <&sys_32k_ck>; | |
| 1193 | ti,bit-shift = <8>; | |
| 1194 | reg = <0x1838>; | |
| 1195 | }; | |
| 1196 | ||
| 7aa1a408 | 1197 | dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 { |
| 57cd681b TR |
1198 | #clock-cells = <0>; |
| 1199 | compatible = "ti,mux-clock"; | |
| 1200 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
| 1201 | ti,bit-shift = <24>; | |
| 1202 | reg = <0x1888>; | |
| 1203 | }; | |
| 1204 | ||
| 7aa1a408 | 1205 | timer1_gfclk_mux: timer1_gfclk_mux@1840 { |
| 57cd681b TR |
1206 | #clock-cells = <0>; |
| 1207 | compatible = "ti,mux-clock"; | |
| 1208 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 1209 | ti,bit-shift = <24>; | |
| 1210 | reg = <0x1840>; | |
| 1211 | }; | |
| 1212 | ||
| 7aa1a408 | 1213 | uart10_gfclk_mux: uart10_gfclk_mux@1880 { |
| 57cd681b TR |
1214 | #clock-cells = <0>; |
| 1215 | compatible = "ti,mux-clock"; | |
| 1216 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 1217 | ti,bit-shift = <24>; | |
| 1218 | reg = <0x1880>; | |
| 1219 | }; | |
| 1220 | }; | |
| 1221 | &cm_core_clocks { | |
| f8ae3e60 | 1222 | dpll_pcie_ref_ck: clock@200 { |
| 57cd681b TR |
1223 | #clock-cells = <0>; |
| 1224 | compatible = "ti,omap4-dpll-clock"; | |
| 1225 | clocks = <&sys_clkin1>, <&sys_clkin1>; | |
| 1226 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
| 1227 | }; | |
| 1228 | ||
| f8ae3e60 | 1229 | dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { |
| 57cd681b TR |
1230 | #clock-cells = <0>; |
| 1231 | compatible = "ti,divider-clock"; | |
| 1232 | clocks = <&dpll_pcie_ref_ck>; | |
| 1233 | ti,max-div = <31>; | |
| 1234 | ti,autoidle-shift = <8>; | |
| 1235 | reg = <0x0210>; | |
| 1236 | ti,index-starts-at-one; | |
| 1237 | ti,invert-autoidle-bit; | |
| 1238 | }; | |
| 1239 | ||
| f8ae3e60 | 1240 | apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { |
| 57cd681b TR |
1241 | compatible = "ti,mux-clock"; |
| 1242 | clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; | |
| 1243 | #clock-cells = <0>; | |
| 1244 | reg = <0x021c 0x4>; | |
| 1245 | ti,bit-shift = <7>; | |
| 1246 | }; | |
| 1247 | ||
| f8ae3e60 | 1248 | apll_pcie_ck: clock@21c { |
| 57cd681b TR |
1249 | #clock-cells = <0>; |
| 1250 | compatible = "ti,dra7-apll-clock"; | |
| 1251 | clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; | |
| 1252 | reg = <0x021c>, <0x0220>; | |
| 1253 | }; | |
| 1254 | ||
| 1255 | optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { | |
| 1256 | compatible = "ti,gate-clock"; | |
| 1257 | clocks = <&sys_32k_ck>; | |
| 1258 | #clock-cells = <0>; | |
| 1259 | reg = <0x13b0>; | |
| 1260 | ti,bit-shift = <8>; | |
| 1261 | }; | |
| 1262 | ||
| 1263 | optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { | |
| 1264 | compatible = "ti,gate-clock"; | |
| 1265 | clocks = <&sys_32k_ck>; | |
| 1266 | #clock-cells = <0>; | |
| 1267 | reg = <0x13b8>; | |
| 1268 | ti,bit-shift = <8>; | |
| 1269 | }; | |
| 1270 | ||
| f8ae3e60 | 1271 | optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { |
| 57cd681b TR |
1272 | compatible = "ti,divider-clock"; |
| 1273 | clocks = <&apll_pcie_ck>; | |
| 1274 | #clock-cells = <0>; | |
| 1275 | reg = <0x021c>; | |
| 1276 | ti,dividers = <2>, <1>; | |
| 1277 | ti,bit-shift = <8>; | |
| 1278 | ti,max-div = <2>; | |
| 1279 | }; | |
| 1280 | ||
| 1281 | optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { | |
| 1282 | compatible = "ti,gate-clock"; | |
| 1283 | clocks = <&apll_pcie_ck>; | |
| 1284 | #clock-cells = <0>; | |
| 1285 | reg = <0x13b0>; | |
| 1286 | ti,bit-shift = <9>; | |
| 1287 | }; | |
| 1288 | ||
| 1289 | optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { | |
| 1290 | compatible = "ti,gate-clock"; | |
| 1291 | clocks = <&apll_pcie_ck>; | |
| 1292 | #clock-cells = <0>; | |
| 1293 | reg = <0x13b8>; | |
| 1294 | ti,bit-shift = <9>; | |
| 1295 | }; | |
| 1296 | ||
| 1297 | optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { | |
| 1298 | compatible = "ti,gate-clock"; | |
| 1299 | clocks = <&optfclk_pciephy_div>; | |
| 1300 | #clock-cells = <0>; | |
| 1301 | reg = <0x13b0>; | |
| 1302 | ti,bit-shift = <10>; | |
| 1303 | }; | |
| 1304 | ||
| 1305 | optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { | |
| 1306 | compatible = "ti,gate-clock"; | |
| 1307 | clocks = <&optfclk_pciephy_div>; | |
| 1308 | #clock-cells = <0>; | |
| 1309 | reg = <0x13b8>; | |
| 1310 | ti,bit-shift = <10>; | |
| 1311 | }; | |
| 1312 | ||
| f8ae3e60 | 1313 | apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { |
| 57cd681b TR |
1314 | #clock-cells = <0>; |
| 1315 | compatible = "fixed-factor-clock"; | |
| 1316 | clocks = <&apll_pcie_ck>; | |
| 1317 | clock-mult = <1>; | |
| 1318 | clock-div = <1>; | |
| 1319 | }; | |
| 1320 | ||
| f8ae3e60 | 1321 | apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { |
| 57cd681b TR |
1322 | #clock-cells = <0>; |
| 1323 | compatible = "fixed-factor-clock"; | |
| 1324 | clocks = <&apll_pcie_ck>; | |
| 1325 | clock-mult = <1>; | |
| 1326 | clock-div = <1>; | |
| 1327 | }; | |
| 1328 | ||
| f8ae3e60 | 1329 | apll_pcie_m2_ck: clock-apll-pcie-m2 { |
| 57cd681b TR |
1330 | #clock-cells = <0>; |
| 1331 | compatible = "fixed-factor-clock"; | |
| 1332 | clocks = <&apll_pcie_ck>; | |
| 1333 | clock-mult = <1>; | |
| 1334 | clock-div = <1>; | |
| 1335 | }; | |
| 1336 | ||
| f8ae3e60 | 1337 | dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { |
| 57cd681b TR |
1338 | #clock-cells = <0>; |
| 1339 | compatible = "ti,mux-clock"; | |
| 1340 | clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; | |
| 1341 | ti,bit-shift = <23>; | |
| 1342 | reg = <0x014c>; | |
| 1343 | }; | |
| 1344 | ||
| f8ae3e60 | 1345 | dpll_per_ck: clock@140 { |
| 57cd681b TR |
1346 | #clock-cells = <0>; |
| 1347 | compatible = "ti,omap4-dpll-clock"; | |
| 1348 | clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; | |
| 1349 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; | |
| 1350 | }; | |
| 1351 | ||
| f8ae3e60 | 1352 | dpll_per_m2_ck: clock-dpll-per-m2-8@150 { |
| 57cd681b TR |
1353 | #clock-cells = <0>; |
| 1354 | compatible = "ti,divider-clock"; | |
| 1355 | clocks = <&dpll_per_ck>; | |
| 1356 | ti,max-div = <31>; | |
| 1357 | ti,autoidle-shift = <8>; | |
| 1358 | reg = <0x0150>; | |
| 1359 | ti,index-starts-at-one; | |
| 1360 | ti,invert-autoidle-bit; | |
| 1361 | }; | |
| 1362 | ||
| f8ae3e60 | 1363 | func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { |
| 57cd681b TR |
1364 | #clock-cells = <0>; |
| 1365 | compatible = "fixed-factor-clock"; | |
| 1366 | clocks = <&dpll_per_m2_ck>; | |
| 1367 | clock-mult = <1>; | |
| 1368 | clock-div = <1>; | |
| 1369 | }; | |
| 1370 | ||
| f8ae3e60 | 1371 | dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { |
| 57cd681b TR |
1372 | #clock-cells = <0>; |
| 1373 | compatible = "ti,mux-clock"; | |
| 1374 | clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; | |
| 1375 | ti,bit-shift = <23>; | |
| 1376 | reg = <0x018c>; | |
| 1377 | }; | |
| 1378 | ||
| f8ae3e60 | 1379 | dpll_usb_ck: clock@180 { |
| 57cd681b TR |
1380 | #clock-cells = <0>; |
| 1381 | compatible = "ti,omap4-dpll-j-type-clock"; | |
| 1382 | clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; | |
| 1383 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; | |
| 1384 | }; | |
| 1385 | ||
| f8ae3e60 | 1386 | dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { |
| 57cd681b TR |
1387 | #clock-cells = <0>; |
| 1388 | compatible = "ti,divider-clock"; | |
| 1389 | clocks = <&dpll_usb_ck>; | |
| 1390 | ti,max-div = <127>; | |
| 1391 | ti,autoidle-shift = <8>; | |
| 1392 | reg = <0x0190>; | |
| 1393 | ti,index-starts-at-one; | |
| 1394 | ti,invert-autoidle-bit; | |
| 1395 | }; | |
| 1396 | ||
| f8ae3e60 | 1397 | dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { |
| 57cd681b TR |
1398 | #clock-cells = <0>; |
| 1399 | compatible = "ti,divider-clock"; | |
| 1400 | clocks = <&dpll_pcie_ref_ck>; | |
| 1401 | ti,max-div = <127>; | |
| 1402 | ti,autoidle-shift = <8>; | |
| 1403 | reg = <0x0210>; | |
| 1404 | ti,index-starts-at-one; | |
| 1405 | ti,invert-autoidle-bit; | |
| 1406 | }; | |
| 1407 | ||
| f8ae3e60 | 1408 | dpll_per_x2_ck: clock-dpll-per-x2 { |
| 57cd681b TR |
1409 | #clock-cells = <0>; |
| 1410 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 1411 | clocks = <&dpll_per_ck>; | |
| 1412 | }; | |
| 1413 | ||
| f8ae3e60 | 1414 | dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { |
| 57cd681b TR |
1415 | #clock-cells = <0>; |
| 1416 | compatible = "ti,divider-clock"; | |
| 1417 | clocks = <&dpll_per_x2_ck>; | |
| 1418 | ti,max-div = <63>; | |
| 1419 | ti,autoidle-shift = <8>; | |
| 1420 | reg = <0x0158>; | |
| 1421 | ti,index-starts-at-one; | |
| 1422 | ti,invert-autoidle-bit; | |
| 1423 | }; | |
| 1424 | ||
| f8ae3e60 | 1425 | dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { |
| 57cd681b TR |
1426 | #clock-cells = <0>; |
| 1427 | compatible = "ti,divider-clock"; | |
| 1428 | clocks = <&dpll_per_x2_ck>; | |
| 1429 | ti,max-div = <63>; | |
| 1430 | ti,autoidle-shift = <8>; | |
| 1431 | reg = <0x015c>; | |
| 1432 | ti,index-starts-at-one; | |
| 1433 | ti,invert-autoidle-bit; | |
| 1434 | }; | |
| 1435 | ||
| f8ae3e60 | 1436 | dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { |
| 57cd681b TR |
1437 | #clock-cells = <0>; |
| 1438 | compatible = "ti,divider-clock"; | |
| 1439 | clocks = <&dpll_per_x2_ck>; | |
| 1440 | ti,max-div = <63>; | |
| 1441 | ti,autoidle-shift = <8>; | |
| 1442 | reg = <0x0160>; | |
| 1443 | ti,index-starts-at-one; | |
| 1444 | ti,invert-autoidle-bit; | |
| 1445 | }; | |
| 1446 | ||
| f8ae3e60 | 1447 | dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { |
| 57cd681b TR |
1448 | #clock-cells = <0>; |
| 1449 | compatible = "ti,divider-clock"; | |
| 1450 | clocks = <&dpll_per_x2_ck>; | |
| 1451 | ti,max-div = <63>; | |
| 1452 | ti,autoidle-shift = <8>; | |
| 1453 | reg = <0x0164>; | |
| 1454 | ti,index-starts-at-one; | |
| 1455 | ti,invert-autoidle-bit; | |
| 1456 | }; | |
| 1457 | ||
| f8ae3e60 | 1458 | dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { |
| 57cd681b TR |
1459 | #clock-cells = <0>; |
| 1460 | compatible = "ti,divider-clock"; | |
| 1461 | clocks = <&dpll_per_x2_ck>; | |
| 1462 | ti,max-div = <31>; | |
| 1463 | ti,autoidle-shift = <8>; | |
| 1464 | reg = <0x0150>; | |
| 1465 | ti,index-starts-at-one; | |
| 1466 | ti,invert-autoidle-bit; | |
| 1467 | }; | |
| 1468 | ||
| f8ae3e60 | 1469 | dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { |
| 57cd681b TR |
1470 | #clock-cells = <0>; |
| 1471 | compatible = "fixed-factor-clock"; | |
| 1472 | clocks = <&dpll_usb_ck>; | |
| 1473 | clock-mult = <1>; | |
| 1474 | clock-div = <1>; | |
| 1475 | }; | |
| 1476 | ||
| f8ae3e60 | 1477 | func_128m_clk: clock-func-128m { |
| 57cd681b TR |
1478 | #clock-cells = <0>; |
| 1479 | compatible = "fixed-factor-clock"; | |
| 1480 | clocks = <&dpll_per_h11x2_ck>; | |
| 1481 | clock-mult = <1>; | |
| 1482 | clock-div = <2>; | |
| 1483 | }; | |
| 1484 | ||
| f8ae3e60 | 1485 | func_12m_fclk: clock-func-12m-fclk { |
| 57cd681b TR |
1486 | #clock-cells = <0>; |
| 1487 | compatible = "fixed-factor-clock"; | |
| 1488 | clocks = <&dpll_per_m2x2_ck>; | |
| 1489 | clock-mult = <1>; | |
| 1490 | clock-div = <16>; | |
| 1491 | }; | |
| 1492 | ||
| f8ae3e60 | 1493 | func_24m_clk: clock-func-24m { |
| 57cd681b TR |
1494 | #clock-cells = <0>; |
| 1495 | compatible = "fixed-factor-clock"; | |
| 1496 | clocks = <&dpll_per_m2_ck>; | |
| 1497 | clock-mult = <1>; | |
| 1498 | clock-div = <4>; | |
| 1499 | }; | |
| 1500 | ||
| f8ae3e60 | 1501 | func_48m_fclk: clock-func-48m-fclk { |
| 57cd681b TR |
1502 | #clock-cells = <0>; |
| 1503 | compatible = "fixed-factor-clock"; | |
| 1504 | clocks = <&dpll_per_m2x2_ck>; | |
| 1505 | clock-mult = <1>; | |
| 1506 | clock-div = <4>; | |
| 1507 | }; | |
| 1508 | ||
| f8ae3e60 | 1509 | func_96m_fclk: clock-func-96m-fclk { |
| 57cd681b TR |
1510 | #clock-cells = <0>; |
| 1511 | compatible = "fixed-factor-clock"; | |
| 1512 | clocks = <&dpll_per_m2x2_ck>; | |
| 1513 | clock-mult = <1>; | |
| 1514 | clock-div = <2>; | |
| 1515 | }; | |
| 1516 | ||
| f8ae3e60 | 1517 | l3init_60m_fclk: clock-l3init-60m@104 { |
| 57cd681b TR |
1518 | #clock-cells = <0>; |
| 1519 | compatible = "ti,divider-clock"; | |
| 1520 | clocks = <&dpll_usb_m2_ck>; | |
| 1521 | reg = <0x0104>; | |
| 1522 | ti,dividers = <1>, <8>; | |
| 1523 | }; | |
| 1524 | ||
| f8ae3e60 | 1525 | clkout2_clk: clock-clkout2-8@6b0 { |
| 57cd681b TR |
1526 | #clock-cells = <0>; |
| 1527 | compatible = "ti,gate-clock"; | |
| 1528 | clocks = <&clkoutmux2_clk_mux>; | |
| 1529 | ti,bit-shift = <8>; | |
| 1530 | reg = <0x06b0>; | |
| 1531 | }; | |
| 1532 | ||
| f8ae3e60 | 1533 | l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { |
| 57cd681b TR |
1534 | #clock-cells = <0>; |
| 1535 | compatible = "ti,gate-clock"; | |
| 1536 | clocks = <&dpll_usb_clkdcoldo>; | |
| 1537 | ti,bit-shift = <8>; | |
| 1538 | reg = <0x06c0>; | |
| 1539 | }; | |
| 1540 | ||
| 7aa1a408 | 1541 | dss_32khz_clk: dss_32khz_clk@1120 { |
| 57cd681b TR |
1542 | #clock-cells = <0>; |
| 1543 | compatible = "ti,gate-clock"; | |
| 1544 | clocks = <&sys_32k_ck>; | |
| 1545 | ti,bit-shift = <11>; | |
| 1546 | reg = <0x1120>; | |
| 1547 | }; | |
| 1548 | ||
| 7aa1a408 | 1549 | dss_48mhz_clk: dss_48mhz_clk@1120 { |
| 57cd681b TR |
1550 | #clock-cells = <0>; |
| 1551 | compatible = "ti,gate-clock"; | |
| 1552 | clocks = <&func_48m_fclk>; | |
| 1553 | ti,bit-shift = <9>; | |
| 1554 | reg = <0x1120>; | |
| 1555 | }; | |
| 1556 | ||
| 7aa1a408 | 1557 | dss_dss_clk: dss_dss_clk@1120 { |
| 57cd681b TR |
1558 | #clock-cells = <0>; |
| 1559 | compatible = "ti,gate-clock"; | |
| 1560 | clocks = <&dpll_per_h12x2_ck>; | |
| 1561 | ti,bit-shift = <8>; | |
| 1562 | reg = <0x1120>; | |
| 1563 | ti,set-rate-parent; | |
| 1564 | }; | |
| 1565 | ||
| 7aa1a408 | 1566 | dss_hdmi_clk: dss_hdmi_clk@1120 { |
| 57cd681b TR |
1567 | #clock-cells = <0>; |
| 1568 | compatible = "ti,gate-clock"; | |
| 1569 | clocks = <&hdmi_dpll_clk_mux>; | |
| 1570 | ti,bit-shift = <10>; | |
| 1571 | reg = <0x1120>; | |
| 1572 | }; | |
| 1573 | ||
| 7aa1a408 | 1574 | dss_video1_clk: dss_video1_clk@1120 { |
| 57cd681b TR |
1575 | #clock-cells = <0>; |
| 1576 | compatible = "ti,gate-clock"; | |
| 1577 | clocks = <&video1_dpll_clk_mux>; | |
| 1578 | ti,bit-shift = <12>; | |
| 1579 | reg = <0x1120>; | |
| 1580 | }; | |
| 1581 | ||
| 7aa1a408 | 1582 | dss_video2_clk: dss_video2_clk@1120 { |
| 57cd681b TR |
1583 | #clock-cells = <0>; |
| 1584 | compatible = "ti,gate-clock"; | |
| 1585 | clocks = <&video2_dpll_clk_mux>; | |
| 1586 | ti,bit-shift = <13>; | |
| 1587 | reg = <0x1120>; | |
| 1588 | }; | |
| 1589 | ||
| 7aa1a408 | 1590 | gpio2_dbclk: gpio2_dbclk@1760 { |
| 57cd681b TR |
1591 | #clock-cells = <0>; |
| 1592 | compatible = "ti,gate-clock"; | |
| 1593 | clocks = <&sys_32k_ck>; | |
| 1594 | ti,bit-shift = <8>; | |
| 1595 | reg = <0x1760>; | |
| 1596 | }; | |
| 1597 | ||
| 7aa1a408 | 1598 | gpio3_dbclk: gpio3_dbclk@1768 { |
| 57cd681b TR |
1599 | #clock-cells = <0>; |
| 1600 | compatible = "ti,gate-clock"; | |
| 1601 | clocks = <&sys_32k_ck>; | |
| 1602 | ti,bit-shift = <8>; | |
| 1603 | reg = <0x1768>; | |
| 1604 | }; | |
| 1605 | ||
| 7aa1a408 | 1606 | gpio4_dbclk: gpio4_dbclk@1770 { |
| 57cd681b TR |
1607 | #clock-cells = <0>; |
| 1608 | compatible = "ti,gate-clock"; | |
| 1609 | clocks = <&sys_32k_ck>; | |
| 1610 | ti,bit-shift = <8>; | |
| 1611 | reg = <0x1770>; | |
| 1612 | }; | |
| 1613 | ||
| 7aa1a408 | 1614 | gpio5_dbclk: gpio5_dbclk@1778 { |
| 57cd681b TR |
1615 | #clock-cells = <0>; |
| 1616 | compatible = "ti,gate-clock"; | |
| 1617 | clocks = <&sys_32k_ck>; | |
| 1618 | ti,bit-shift = <8>; | |
| 1619 | reg = <0x1778>; | |
| 1620 | }; | |
| 1621 | ||
| 7aa1a408 | 1622 | gpio6_dbclk: gpio6_dbclk@1780 { |
| 57cd681b TR |
1623 | #clock-cells = <0>; |
| 1624 | compatible = "ti,gate-clock"; | |
| 1625 | clocks = <&sys_32k_ck>; | |
| 1626 | ti,bit-shift = <8>; | |
| 1627 | reg = <0x1780>; | |
| 1628 | }; | |
| 1629 | ||
| 7aa1a408 | 1630 | gpio7_dbclk: gpio7_dbclk@1810 { |
| 57cd681b TR |
1631 | #clock-cells = <0>; |
| 1632 | compatible = "ti,gate-clock"; | |
| 1633 | clocks = <&sys_32k_ck>; | |
| 1634 | ti,bit-shift = <8>; | |
| 1635 | reg = <0x1810>; | |
| 1636 | }; | |
| 1637 | ||
| 7aa1a408 | 1638 | gpio8_dbclk: gpio8_dbclk@1818 { |
| 57cd681b TR |
1639 | #clock-cells = <0>; |
| 1640 | compatible = "ti,gate-clock"; | |
| 1641 | clocks = <&sys_32k_ck>; | |
| 1642 | ti,bit-shift = <8>; | |
| 1643 | reg = <0x1818>; | |
| 1644 | }; | |
| 1645 | ||
| 7aa1a408 | 1646 | mmc1_clk32k: mmc1_clk32k@1328 { |
| 57cd681b TR |
1647 | #clock-cells = <0>; |
| 1648 | compatible = "ti,gate-clock"; | |
| 1649 | clocks = <&sys_32k_ck>; | |
| 1650 | ti,bit-shift = <8>; | |
| 1651 | reg = <0x1328>; | |
| 1652 | }; | |
| 1653 | ||
| 7aa1a408 | 1654 | mmc2_clk32k: mmc2_clk32k@1330 { |
| 57cd681b TR |
1655 | #clock-cells = <0>; |
| 1656 | compatible = "ti,gate-clock"; | |
| 1657 | clocks = <&sys_32k_ck>; | |
| 1658 | ti,bit-shift = <8>; | |
| 1659 | reg = <0x1330>; | |
| 1660 | }; | |
| 1661 | ||
| 7aa1a408 | 1662 | mmc3_clk32k: mmc3_clk32k@1820 { |
| 57cd681b TR |
1663 | #clock-cells = <0>; |
| 1664 | compatible = "ti,gate-clock"; | |
| 1665 | clocks = <&sys_32k_ck>; | |
| 1666 | ti,bit-shift = <8>; | |
| 1667 | reg = <0x1820>; | |
| 1668 | }; | |
| 1669 | ||
| 7aa1a408 | 1670 | mmc4_clk32k: mmc4_clk32k@1828 { |
| 57cd681b TR |
1671 | #clock-cells = <0>; |
| 1672 | compatible = "ti,gate-clock"; | |
| 1673 | clocks = <&sys_32k_ck>; | |
| 1674 | ti,bit-shift = <8>; | |
| 1675 | reg = <0x1828>; | |
| 1676 | }; | |
| 1677 | ||
| 7aa1a408 | 1678 | sata_ref_clk: sata_ref_clk@1388 { |
| 57cd681b TR |
1679 | #clock-cells = <0>; |
| 1680 | compatible = "ti,gate-clock"; | |
| 1681 | clocks = <&sys_clkin1>; | |
| 1682 | ti,bit-shift = <8>; | |
| 1683 | reg = <0x1388>; | |
| 1684 | }; | |
| 1685 | ||
| 7aa1a408 | 1686 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 { |
| 57cd681b TR |
1687 | #clock-cells = <0>; |
| 1688 | compatible = "ti,gate-clock"; | |
| 1689 | clocks = <&l3init_960m_gfclk>; | |
| 1690 | ti,bit-shift = <8>; | |
| 1691 | reg = <0x13f0>; | |
| 1692 | }; | |
| 1693 | ||
| 7aa1a408 | 1694 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 { |
| 57cd681b TR |
1695 | #clock-cells = <0>; |
| 1696 | compatible = "ti,gate-clock"; | |
| 1697 | clocks = <&l3init_960m_gfclk>; | |
| 1698 | ti,bit-shift = <8>; | |
| 1699 | reg = <0x1340>; | |
| 1700 | }; | |
| 1701 | ||
| f8ae3e60 | 1702 | usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { |
| 57cd681b TR |
1703 | #clock-cells = <0>; |
| 1704 | compatible = "ti,gate-clock"; | |
| 1705 | clocks = <&sys_32k_ck>; | |
| 1706 | ti,bit-shift = <8>; | |
| 1707 | reg = <0x0640>; | |
| 1708 | }; | |
| 1709 | ||
| f8ae3e60 | 1710 | usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { |
| 57cd681b TR |
1711 | #clock-cells = <0>; |
| 1712 | compatible = "ti,gate-clock"; | |
| 1713 | clocks = <&sys_32k_ck>; | |
| 1714 | ti,bit-shift = <8>; | |
| 1715 | reg = <0x0688>; | |
| 1716 | }; | |
| 1717 | ||
| f8ae3e60 | 1718 | usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { |
| 57cd681b TR |
1719 | #clock-cells = <0>; |
| 1720 | compatible = "ti,gate-clock"; | |
| 1721 | clocks = <&sys_32k_ck>; | |
| 1722 | ti,bit-shift = <8>; | |
| 1723 | reg = <0x0698>; | |
| 1724 | }; | |
| 1725 | ||
| 7aa1a408 | 1726 | atl_dpll_clk_mux: atl_dpll_clk_mux@c00 { |
| 57cd681b TR |
1727 | #clock-cells = <0>; |
| 1728 | compatible = "ti,mux-clock"; | |
| 1729 | clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; | |
| 1730 | ti,bit-shift = <24>; | |
| 1731 | reg = <0x0c00>; | |
| 1732 | }; | |
| 1733 | ||
| 7aa1a408 | 1734 | atl_gfclk_mux: atl_gfclk_mux@c00 { |
| 57cd681b TR |
1735 | #clock-cells = <0>; |
| 1736 | compatible = "ti,mux-clock"; | |
| 1737 | clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; | |
| 1738 | ti,bit-shift = <26>; | |
| 1739 | reg = <0x0c00>; | |
| 1740 | }; | |
| 1741 | ||
| 7aa1a408 | 1742 | rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { |
| 57cd681b | 1743 | #clock-cells = <0>; |
| 7aa1a408 LV |
1744 | compatible = "ti,mux-clock"; |
| 1745 | clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; | |
| 57cd681b TR |
1746 | ti,bit-shift = <24>; |
| 1747 | reg = <0x13d0>; | |
| 57cd681b TR |
1748 | }; |
| 1749 | ||
| 7aa1a408 | 1750 | gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { |
| 57cd681b TR |
1751 | #clock-cells = <0>; |
| 1752 | compatible = "ti,mux-clock"; | |
| 1753 | clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; | |
| 1754 | ti,bit-shift = <25>; | |
| 1755 | reg = <0x13d0>; | |
| 1756 | }; | |
| 1757 | ||
| f8ae3e60 | 1758 | gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { |
| 57cd681b TR |
1759 | #clock-cells = <0>; |
| 1760 | compatible = "ti,mux-clock"; | |
| 1761 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; | |
| 1762 | ti,bit-shift = <24>; | |
| 1763 | reg = <0x1220>; | |
| 4ddaa6ce LV |
1764 | assigned-clocks = <&gpu_core_gclk_mux>; |
| 1765 | assigned-clock-parents = <&dpll_gpu_m2_ck>; | |
| 57cd681b TR |
1766 | }; |
| 1767 | ||
| f8ae3e60 | 1768 | gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { |
| 57cd681b TR |
1769 | #clock-cells = <0>; |
| 1770 | compatible = "ti,mux-clock"; | |
| 1771 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; | |
| 1772 | ti,bit-shift = <26>; | |
| 1773 | reg = <0x1220>; | |
| 4ddaa6ce LV |
1774 | assigned-clocks = <&gpu_hyd_gclk_mux>; |
| 1775 | assigned-clock-parents = <&dpll_gpu_m2_ck>; | |
| 57cd681b TR |
1776 | }; |
| 1777 | ||
| f8ae3e60 | 1778 | l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { |
| 57cd681b TR |
1779 | #clock-cells = <0>; |
| 1780 | compatible = "ti,divider-clock"; | |
| 1781 | clocks = <&wkupaon_iclk_mux>; | |
| 1782 | ti,bit-shift = <24>; | |
| 1783 | reg = <0x0e50>; | |
| 1784 | ti,dividers = <8>, <16>, <32>; | |
| 1785 | }; | |
| 1786 | ||
| 7aa1a408 | 1787 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { |
| 57cd681b TR |
1788 | #clock-cells = <0>; |
| 1789 | compatible = "ti,mux-clock"; | |
| 1790 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1791 | ti,bit-shift = <28>; | |
| 1792 | reg = <0x1860>; | |
| 1793 | }; | |
| 1794 | ||
| 7aa1a408 | 1795 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 { |
| 57cd681b TR |
1796 | #clock-cells = <0>; |
| 1797 | compatible = "ti,mux-clock"; | |
| 1798 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1799 | ti,bit-shift = <24>; | |
| 1800 | reg = <0x1860>; | |
| 1801 | }; | |
| 1802 | ||
| 7aa1a408 | 1803 | mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { |
| 57cd681b TR |
1804 | #clock-cells = <0>; |
| 1805 | compatible = "ti,mux-clock"; | |
| 1806 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1807 | ti,bit-shift = <22>; | |
| 1808 | reg = <0x1860>; | |
| 1809 | }; | |
| 1810 | ||
| 7aa1a408 | 1811 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { |
| 57cd681b TR |
1812 | #clock-cells = <0>; |
| 1813 | compatible = "ti,mux-clock"; | |
| 1814 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1815 | ti,bit-shift = <24>; | |
| 1816 | reg = <0x1868>; | |
| 1817 | }; | |
| 1818 | ||
| 7aa1a408 | 1819 | mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { |
| 57cd681b TR |
1820 | #clock-cells = <0>; |
| 1821 | compatible = "ti,mux-clock"; | |
| 1822 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1823 | ti,bit-shift = <22>; | |
| 1824 | reg = <0x1868>; | |
| 1825 | }; | |
| 1826 | ||
| 7aa1a408 | 1827 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { |
| 57cd681b TR |
1828 | #clock-cells = <0>; |
| 1829 | compatible = "ti,mux-clock"; | |
| 1830 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1831 | ti,bit-shift = <24>; | |
| 1832 | reg = <0x1898>; | |
| 1833 | }; | |
| 1834 | ||
| 7aa1a408 | 1835 | mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { |
| 57cd681b TR |
1836 | #clock-cells = <0>; |
| 1837 | compatible = "ti,mux-clock"; | |
| 1838 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1839 | ti,bit-shift = <22>; | |
| 1840 | reg = <0x1898>; | |
| 1841 | }; | |
| 1842 | ||
| 7aa1a408 | 1843 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { |
| 57cd681b TR |
1844 | #clock-cells = <0>; |
| 1845 | compatible = "ti,mux-clock"; | |
| 1846 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1847 | ti,bit-shift = <24>; | |
| 1848 | reg = <0x1878>; | |
| 1849 | }; | |
| 1850 | ||
| 7aa1a408 | 1851 | mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { |
| 57cd681b TR |
1852 | #clock-cells = <0>; |
| 1853 | compatible = "ti,mux-clock"; | |
| 1854 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1855 | ti,bit-shift = <22>; | |
| 1856 | reg = <0x1878>; | |
| 1857 | }; | |
| 1858 | ||
| 7aa1a408 | 1859 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { |
| 57cd681b TR |
1860 | #clock-cells = <0>; |
| 1861 | compatible = "ti,mux-clock"; | |
| 1862 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1863 | ti,bit-shift = <24>; | |
| 1864 | reg = <0x1904>; | |
| 1865 | }; | |
| 1866 | ||
| 7aa1a408 | 1867 | mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { |
| 57cd681b TR |
1868 | #clock-cells = <0>; |
| 1869 | compatible = "ti,mux-clock"; | |
| 1870 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1871 | ti,bit-shift = <22>; | |
| 1872 | reg = <0x1904>; | |
| 1873 | }; | |
| 1874 | ||
| 7aa1a408 | 1875 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { |
| 57cd681b TR |
1876 | #clock-cells = <0>; |
| 1877 | compatible = "ti,mux-clock"; | |
| 1878 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1879 | ti,bit-shift = <24>; | |
| 1880 | reg = <0x1908>; | |
| 1881 | }; | |
| 1882 | ||
| 7aa1a408 | 1883 | mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 { |
| 57cd681b TR |
1884 | #clock-cells = <0>; |
| 1885 | compatible = "ti,mux-clock"; | |
| 1886 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1887 | ti,bit-shift = <22>; | |
| 1888 | reg = <0x1908>; | |
| 1889 | }; | |
| 1890 | ||
| 7aa1a408 | 1891 | mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { |
| 57cd681b TR |
1892 | #clock-cells = <0>; |
| 1893 | compatible = "ti,mux-clock"; | |
| 1894 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | |
| 1895 | ti,bit-shift = <22>; | |
| 1896 | reg = <0x1890>; | |
| 1897 | }; | |
| 1898 | ||
| 7aa1a408 | 1899 | mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { |
| 57cd681b TR |
1900 | #clock-cells = <0>; |
| 1901 | compatible = "ti,mux-clock"; | |
| 1902 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
| 1903 | ti,bit-shift = <24>; | |
| 1904 | reg = <0x1890>; | |
| 1905 | }; | |
| 1906 | ||
| 7aa1a408 | 1907 | mmc1_fclk_mux: mmc1_fclk_mux@1328 { |
| 57cd681b TR |
1908 | #clock-cells = <0>; |
| 1909 | compatible = "ti,mux-clock"; | |
| 1910 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1911 | ti,bit-shift = <24>; | |
| 1912 | reg = <0x1328>; | |
| 1913 | }; | |
| 1914 | ||
| 7aa1a408 | 1915 | mmc1_fclk_div: mmc1_fclk_div@1328 { |
| 57cd681b TR |
1916 | #clock-cells = <0>; |
| 1917 | compatible = "ti,divider-clock"; | |
| 1918 | clocks = <&mmc1_fclk_mux>; | |
| 1919 | ti,bit-shift = <25>; | |
| 1920 | ti,max-div = <4>; | |
| 1921 | reg = <0x1328>; | |
| 1922 | ti,index-power-of-two; | |
| 1923 | }; | |
| 1924 | ||
| 7aa1a408 | 1925 | mmc2_fclk_mux: mmc2_fclk_mux@1330 { |
| 57cd681b TR |
1926 | #clock-cells = <0>; |
| 1927 | compatible = "ti,mux-clock"; | |
| 1928 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1929 | ti,bit-shift = <24>; | |
| 1930 | reg = <0x1330>; | |
| 1931 | }; | |
| 1932 | ||
| 7aa1a408 | 1933 | mmc2_fclk_div: mmc2_fclk_div@1330 { |
| 57cd681b TR |
1934 | #clock-cells = <0>; |
| 1935 | compatible = "ti,divider-clock"; | |
| 1936 | clocks = <&mmc2_fclk_mux>; | |
| 1937 | ti,bit-shift = <25>; | |
| 1938 | ti,max-div = <4>; | |
| 1939 | reg = <0x1330>; | |
| 1940 | ti,index-power-of-two; | |
| 1941 | }; | |
| 1942 | ||
| 7aa1a408 | 1943 | mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { |
| 57cd681b TR |
1944 | #clock-cells = <0>; |
| 1945 | compatible = "ti,mux-clock"; | |
| 1946 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 1947 | ti,bit-shift = <24>; | |
| 1948 | reg = <0x1820>; | |
| 1949 | }; | |
| 1950 | ||
| 7aa1a408 | 1951 | mmc3_gfclk_div: mmc3_gfclk_div@1820 { |
| 57cd681b TR |
1952 | #clock-cells = <0>; |
| 1953 | compatible = "ti,divider-clock"; | |
| 1954 | clocks = <&mmc3_gfclk_mux>; | |
| 1955 | ti,bit-shift = <25>; | |
| 1956 | ti,max-div = <4>; | |
| 1957 | reg = <0x1820>; | |
| 1958 | ti,index-power-of-two; | |
| 1959 | }; | |
| 1960 | ||
| 7aa1a408 | 1961 | mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { |
| 57cd681b TR |
1962 | #clock-cells = <0>; |
| 1963 | compatible = "ti,mux-clock"; | |
| 1964 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 1965 | ti,bit-shift = <24>; | |
| 1966 | reg = <0x1828>; | |
| 1967 | }; | |
| 1968 | ||
| 7aa1a408 | 1969 | mmc4_gfclk_div: mmc4_gfclk_div@1828 { |
| 57cd681b TR |
1970 | #clock-cells = <0>; |
| 1971 | compatible = "ti,divider-clock"; | |
| 1972 | clocks = <&mmc4_gfclk_mux>; | |
| 1973 | ti,bit-shift = <25>; | |
| 1974 | ti,max-div = <4>; | |
| 1975 | reg = <0x1828>; | |
| 1976 | ti,index-power-of-two; | |
| 1977 | }; | |
| 1978 | ||
| 7aa1a408 | 1979 | qspi_gfclk_mux: qspi_gfclk_mux@1838 { |
| 57cd681b TR |
1980 | #clock-cells = <0>; |
| 1981 | compatible = "ti,mux-clock"; | |
| 1982 | clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; | |
| 1983 | ti,bit-shift = <24>; | |
| 1984 | reg = <0x1838>; | |
| 1985 | }; | |
| 1986 | ||
| 7aa1a408 | 1987 | qspi_gfclk_div: qspi_gfclk_div@1838 { |
| 57cd681b TR |
1988 | #clock-cells = <0>; |
| 1989 | compatible = "ti,divider-clock"; | |
| 1990 | clocks = <&qspi_gfclk_mux>; | |
| 1991 | ti,bit-shift = <25>; | |
| 1992 | ti,max-div = <4>; | |
| 1993 | reg = <0x1838>; | |
| 1994 | ti,index-power-of-two; | |
| 1995 | }; | |
| 1996 | ||
| 7aa1a408 | 1997 | timer10_gfclk_mux: timer10_gfclk_mux@1728 { |
| 57cd681b TR |
1998 | #clock-cells = <0>; |
| 1999 | compatible = "ti,mux-clock"; | |
| 2000 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2001 | ti,bit-shift = <24>; | |
| 2002 | reg = <0x1728>; | |
| 2003 | }; | |
| 2004 | ||
| 7aa1a408 | 2005 | timer11_gfclk_mux: timer11_gfclk_mux@1730 { |
| 57cd681b TR |
2006 | #clock-cells = <0>; |
| 2007 | compatible = "ti,mux-clock"; | |
| 2008 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2009 | ti,bit-shift = <24>; | |
| 2010 | reg = <0x1730>; | |
| 2011 | }; | |
| 2012 | ||
| 7aa1a408 | 2013 | timer13_gfclk_mux: timer13_gfclk_mux@17c8 { |
| 57cd681b TR |
2014 | #clock-cells = <0>; |
| 2015 | compatible = "ti,mux-clock"; | |
| 2016 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2017 | ti,bit-shift = <24>; | |
| 2018 | reg = <0x17c8>; | |
| 2019 | }; | |
| 2020 | ||
| 7aa1a408 | 2021 | timer14_gfclk_mux: timer14_gfclk_mux@17d0 { |
| 57cd681b TR |
2022 | #clock-cells = <0>; |
| 2023 | compatible = "ti,mux-clock"; | |
| 2024 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2025 | ti,bit-shift = <24>; | |
| 2026 | reg = <0x17d0>; | |
| 2027 | }; | |
| 2028 | ||
| 7aa1a408 | 2029 | timer15_gfclk_mux: timer15_gfclk_mux@17d8 { |
| 57cd681b TR |
2030 | #clock-cells = <0>; |
| 2031 | compatible = "ti,mux-clock"; | |
| 2032 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2033 | ti,bit-shift = <24>; | |
| 2034 | reg = <0x17d8>; | |
| 2035 | }; | |
| 2036 | ||
| 7aa1a408 | 2037 | timer16_gfclk_mux: timer16_gfclk_mux@1830 { |
| 57cd681b TR |
2038 | #clock-cells = <0>; |
| 2039 | compatible = "ti,mux-clock"; | |
| 2040 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2041 | ti,bit-shift = <24>; | |
| 2042 | reg = <0x1830>; | |
| 2043 | }; | |
| 2044 | ||
| 7aa1a408 | 2045 | timer2_gfclk_mux: timer2_gfclk_mux@1738 { |
| 57cd681b TR |
2046 | #clock-cells = <0>; |
| 2047 | compatible = "ti,mux-clock"; | |
| 2048 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2049 | ti,bit-shift = <24>; | |
| 2050 | reg = <0x1738>; | |
| 2051 | }; | |
| 2052 | ||
| 7aa1a408 | 2053 | timer3_gfclk_mux: timer3_gfclk_mux@1740 { |
| 57cd681b TR |
2054 | #clock-cells = <0>; |
| 2055 | compatible = "ti,mux-clock"; | |
| 2056 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2057 | ti,bit-shift = <24>; | |
| 2058 | reg = <0x1740>; | |
| 2059 | }; | |
| 2060 | ||
| 7aa1a408 | 2061 | timer4_gfclk_mux: timer4_gfclk_mux@1748 { |
| 57cd681b TR |
2062 | #clock-cells = <0>; |
| 2063 | compatible = "ti,mux-clock"; | |
| 2064 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2065 | ti,bit-shift = <24>; | |
| 2066 | reg = <0x1748>; | |
| 2067 | }; | |
| 2068 | ||
| 7aa1a408 | 2069 | timer9_gfclk_mux: timer9_gfclk_mux@1750 { |
| 57cd681b TR |
2070 | #clock-cells = <0>; |
| 2071 | compatible = "ti,mux-clock"; | |
| 2072 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
| 2073 | ti,bit-shift = <24>; | |
| 2074 | reg = <0x1750>; | |
| 2075 | }; | |
| 2076 | ||
| 7aa1a408 | 2077 | uart1_gfclk_mux: uart1_gfclk_mux@1840 { |
| 57cd681b TR |
2078 | #clock-cells = <0>; |
| 2079 | compatible = "ti,mux-clock"; | |
| 2080 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2081 | ti,bit-shift = <24>; | |
| 2082 | reg = <0x1840>; | |
| 2083 | }; | |
| 2084 | ||
| 7aa1a408 | 2085 | uart2_gfclk_mux: uart2_gfclk_mux@1848 { |
| 57cd681b TR |
2086 | #clock-cells = <0>; |
| 2087 | compatible = "ti,mux-clock"; | |
| 2088 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2089 | ti,bit-shift = <24>; | |
| 2090 | reg = <0x1848>; | |
| 2091 | }; | |
| 2092 | ||
| 7aa1a408 | 2093 | uart3_gfclk_mux: uart3_gfclk_mux@1850 { |
| 57cd681b TR |
2094 | #clock-cells = <0>; |
| 2095 | compatible = "ti,mux-clock"; | |
| 2096 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2097 | ti,bit-shift = <24>; | |
| 2098 | reg = <0x1850>; | |
| 2099 | }; | |
| 2100 | ||
| 7aa1a408 | 2101 | uart4_gfclk_mux: uart4_gfclk_mux@1858 { |
| 57cd681b TR |
2102 | #clock-cells = <0>; |
| 2103 | compatible = "ti,mux-clock"; | |
| 2104 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2105 | ti,bit-shift = <24>; | |
| 2106 | reg = <0x1858>; | |
| 2107 | }; | |
| 2108 | ||
| 7aa1a408 | 2109 | uart5_gfclk_mux: uart5_gfclk_mux@1870 { |
| 57cd681b TR |
2110 | #clock-cells = <0>; |
| 2111 | compatible = "ti,mux-clock"; | |
| 2112 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2113 | ti,bit-shift = <24>; | |
| 2114 | reg = <0x1870>; | |
| 2115 | }; | |
| 2116 | ||
| 7aa1a408 | 2117 | uart7_gfclk_mux: uart7_gfclk_mux@18d0 { |
| 57cd681b TR |
2118 | #clock-cells = <0>; |
| 2119 | compatible = "ti,mux-clock"; | |
| 2120 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2121 | ti,bit-shift = <24>; | |
| 2122 | reg = <0x18d0>; | |
| 2123 | }; | |
| 2124 | ||
| 7aa1a408 | 2125 | uart8_gfclk_mux: uart8_gfclk_mux@18e0 { |
| 57cd681b TR |
2126 | #clock-cells = <0>; |
| 2127 | compatible = "ti,mux-clock"; | |
| 2128 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2129 | ti,bit-shift = <24>; | |
| 2130 | reg = <0x18e0>; | |
| 2131 | }; | |
| 2132 | ||
| 7aa1a408 | 2133 | uart9_gfclk_mux: uart9_gfclk_mux@18e8 { |
| 57cd681b TR |
2134 | #clock-cells = <0>; |
| 2135 | compatible = "ti,mux-clock"; | |
| 2136 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
| 2137 | ti,bit-shift = <24>; | |
| 2138 | reg = <0x18e8>; | |
| 2139 | }; | |
| 2140 | ||
| f8ae3e60 | 2141 | vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { |
| 57cd681b TR |
2142 | #clock-cells = <0>; |
| 2143 | compatible = "ti,mux-clock"; | |
| 2144 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
| 2145 | ti,bit-shift = <24>; | |
| 2146 | reg = <0x1020>; | |
| 2147 | }; | |
| 2148 | ||
| f8ae3e60 | 2149 | vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { |
| 57cd681b TR |
2150 | #clock-cells = <0>; |
| 2151 | compatible = "ti,mux-clock"; | |
| 2152 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
| 2153 | ti,bit-shift = <24>; | |
| 2154 | reg = <0x1028>; | |
| 2155 | }; | |
| 2156 | ||
| 7aa1a408 | 2157 | vip3_gclk_mux: vip3_gclk_mux@1030 { |
| 57cd681b TR |
2158 | #clock-cells = <0>; |
| 2159 | compatible = "ti,mux-clock"; | |
| 2160 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
| 2161 | ti,bit-shift = <24>; | |
| 2162 | reg = <0x1030>; | |
| 2163 | }; | |
| 2164 | }; | |
| 2165 | ||
| 2166 | &cm_core_clockdomains { | |
| 2167 | coreaon_clkdm: coreaon_clkdm { | |
| 2168 | compatible = "ti,clockdomain"; | |
| 2169 | clocks = <&dpll_usb_ck>; | |
| 2170 | }; | |
| 2171 | }; | |
| 2172 | ||
| 2173 | &scm_conf_clocks { | |
| 7aa1a408 | 2174 | dss_deshdcp_clk: dss_deshdcp_clk@558 { |
| 57cd681b TR |
2175 | #clock-cells = <0>; |
| 2176 | compatible = "ti,gate-clock"; | |
| 2177 | clocks = <&l3_iclk_div>; | |
| 2178 | ti,bit-shift = <0>; | |
| 2179 | reg = <0x558>; | |
| 2180 | }; | |
| 7aa1a408 LV |
2181 | |
| 2182 | ehrpwm0_tbclk: ehrpwm0_tbclk@558 { | |
| 2183 | #clock-cells = <0>; | |
| 2184 | compatible = "ti,gate-clock"; | |
| 2185 | clocks = <&l4_root_clk_div>; | |
| 2186 | ti,bit-shift = <20>; | |
| 2187 | reg = <0x0558>; | |
| 2188 | }; | |
| 2189 | ||
| 2190 | ehrpwm1_tbclk: ehrpwm1_tbclk@558 { | |
| 2191 | #clock-cells = <0>; | |
| 2192 | compatible = "ti,gate-clock"; | |
| 2193 | clocks = <&l4_root_clk_div>; | |
| 2194 | ti,bit-shift = <21>; | |
| 2195 | reg = <0x0558>; | |
| 2196 | }; | |
| 2197 | ||
| 2198 | ehrpwm2_tbclk: ehrpwm2_tbclk@558 { | |
| 2199 | #clock-cells = <0>; | |
| 2200 | compatible = "ti,gate-clock"; | |
| 2201 | clocks = <&l4_root_clk_div>; | |
| 2202 | ti,bit-shift = <22>; | |
| 2203 | reg = <0x0558>; | |
| 2204 | }; | |
| 2205 | ||
| 2206 | sys_32k_ck: sys_32k_ck { | |
| 2207 | #clock-cells = <0>; | |
| 2208 | compatible = "ti,mux-clock"; | |
| 2209 | clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; | |
| 2210 | ti,bit-shift = <8>; | |
| 2211 | reg = <0x6c4>; | |
| 2212 | }; | |
| 57cd681b | 2213 | }; |