[u-boot.git] / drivers / pci / pcie_layerscape_fixup.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017-2020 NXP
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Layerscape PCIe driver
 */

#include <common.h>
#include <init.h>
#include <pci.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/io.h>
#include <errno.h>
#ifdef CONFIG_OF_BOARD_SETUP
#include <linux/libfdt.h>
#include <fdt_support.h>
#ifdef CONFIG_ARM
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"

#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
 * Return next available LUT index.
 */
static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
{
	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
		return pcie->next_lut_index++;
	else
		return -ENOSPC;  /* LUT is full */
}

static void lut_writel(struct ls_pcie *pcie, unsigned int value,
		       unsigned int offset)
{
	if (pcie->big_endian)
		out_be32(pcie->lut + offset, value);
	else
		out_le32(pcie->lut + offset, value);
}

/*
 * Program a single LUT entry
 */
static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
				    u32 streamid)
{
	/* leave mask as all zeroes, want to match all bits */
	lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
	lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}

/*
 * An msi-map is a property to be added to the pci controller
 * node.  It is a table, where each entry consists of 4 fields
 * e.g.:
 *
 *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
 *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
 */
static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
					  u32 devid, u32 streamid)
{
	u32 *prop;
	u32 phandle;
	int nodeoffset;
	uint svr;
	char *compat = NULL;

	/* find pci controller node */
	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
						   pcie->dbi_res.start);
	if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
		    svr == SVR_LS2081A || svr == SVR_LS2041A)
			compat = "fsl,ls2088a-pcie";
		else
			compat = CONFIG_FSL_PCIE_COMPAT;
		if (compat)
			nodeoffset = fdt_node_offset_by_compat_reg(blob,
					compat, pcie->dbi_res.start);
#endif
		if (nodeoffset < 0)
			return;
	}

	/* get phandle to MSI controller */
	prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
	if (prop == NULL) {
		debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
		      __func__, pcie->idx);
		return;
	}
	phandle = fdt32_to_cpu(*prop);

	/* set one msi-map row */
	fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
	fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
	fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
	fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
}

/*
 * An iommu-map is a property to be added to the pci controller
 * node.  It is a table, where each entry consists of 4 fields
 * e.g.:
 *
 *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
 *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
 */
static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
					    u32 devid, u32 streamid)
{
	u32 *prop;
	u32 iommu_map[4];
	int nodeoffset;
	int lenp;
	uint svr;
	char *compat = NULL;

	/* find pci controller node */
	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
						   pcie->dbi_res.start);
	if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
		    svr == SVR_LS2081A || svr == SVR_LS2041A)
			compat = "fsl,ls2088a-pcie";
		else
			compat = CONFIG_FSL_PCIE_COMPAT;

		if (compat)
			nodeoffset = fdt_node_offset_by_compat_reg(blob,
						compat, pcie->dbi_res.start);
#endif
		if (nodeoffset < 0)
			return;
	}

	/* get phandle to iommu controller */
	prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
	if (prop == NULL) {
		debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
		      __func__, pcie->idx);
		return;
	}

	/* set iommu-map row */
	iommu_map[0] = cpu_to_fdt32(devid);
	iommu_map[1] = *++prop;
	iommu_map[2] = cpu_to_fdt32(streamid);
	iommu_map[3] = cpu_to_fdt32(1);

	if (devid == 0) {
		fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
				    iommu_map, 16);
	} else {
		fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
	}
}

static void fdt_fixup_pcie_ls(void *blob)
{
	struct udevice *dev, *bus;
	struct ls_pcie *pcie;
	int streamid;
	int index;
	pci_dev_t bdf;

	/* Scan all known buses */
	for (pci_find_first_device(&dev);
	     dev;
	     pci_find_next_device(&dev)) {
		for (bus = dev; device_is_on_pci_bus(bus);)
			bus = bus->parent;
		pcie = dev_get_priv(bus);

		streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
		if (streamid < 0) {
			debug("ERROR: no stream ids free\n");
			continue;
		} else {
			pcie->stream_id_cur++;
		}

		index = ls_pcie_next_lut_index(pcie);
		if (index < 0) {
			debug("ERROR: no LUT indexes free\n");
			continue;
		}

		/* the DT fixup must be relative to the hose first_busno */
		bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
		/* map PCI b.d.f to streamID in LUT */
		ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
					streamid);
		/* update msi-map in device tree */
		fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
					      streamid);
		/* update iommu-map in device tree */
		fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
						streamid);
	}
	pcie_board_fix_fdt(blob);
}
#endif

static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
{
	int off;
	uint svr;
	char *compat = NULL;

	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
					    pcie->dbi_res.start);
	if (off < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
		    svr == SVR_LS2081A || svr == SVR_LS2041A)
			compat = "fsl,ls2088a-pcie";
		else
			compat = CONFIG_FSL_PCIE_COMPAT;
		if (compat)
			off = fdt_node_offset_by_compat_reg(blob,
					compat, pcie->dbi_res.start);
#endif
		if (off < 0)
			return;
	}

	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
	else
		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}

static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
{
	int off;

	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
					    pcie->dbi_res.start);
	if (off < 0)
		return;

	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
	else
		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}

static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
{
	ft_pcie_ep_fix(blob, pcie);
	ft_pcie_rc_fix(blob, pcie);
}

/* Fixup Kernel DT for PCIe */
void ft_pci_setup_ls(void *blob, bd_t *bd)
{
	struct ls_pcie *pcie;

	list_for_each_entry(pcie, &ls_pcie_list, list)
		ft_pcie_ls_setup(blob, pcie);

#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
	fdt_fixup_pcie_ls(blob);
#endif
}

#else /* !CONFIG_OF_BOARD_SETUP */
void ft_pci_setup_ls(void *blob, bd_t *bd)
{
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a7294aba	2	/*
1185b229	3	* Copyright 2017-2020 NXP
a7294aba HZ	4	* Copyright 2014-2015 Freescale Semiconductor, Inc.
a7294aba HZ	5	* Layerscape PCIe driver
a7294aba HZ	6	*/
	7
	8	#include <common.h>
691d719d	9	#include <init.h>
a7294aba HZ	10	#include <pci.h>
	11	#include <asm/arch/fsl_serdes.h>
	12	#include <asm/io.h>
	13	#include <errno.h>
	14	#ifdef CONFIG_OF_BOARD_SETUP
b08c8c48	15	#include <linux/libfdt.h>
a7294aba	16	#include <fdt_support.h>
6e2941d7 SG	17	#ifdef CONFIG_ARM
	18	#include <asm/arch/clock.h>
	19	#endif
a7294aba	20	#include "pcie_layerscape.h"
1185b229	21	#include "pcie_layerscape_fixup_common.h"
a7294aba	22
47d17362	23	#if defined(CONFIG_FSL_LSCH3) \|\| defined(CONFIG_FSL_LSCH2)
a7294aba HZ	24	/*
	25	* Return next available LUT index.
	26	*/
	27	static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
	28	{
	29	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
	30	return pcie->next_lut_index++;
	31	else
	32	return -ENOSPC; /* LUT is full */
	33	}
	34
80afc63f ML	35	static void lut_writel(struct ls_pcie *pcie, unsigned int value,
	36	unsigned int offset)
	37	{
	38	if (pcie->big_endian)
	39	out_be32(pcie->lut + offset, value);
	40	else
	41	out_le32(pcie->lut + offset, value);
	42	}
	43
	44	/*
	45	* Program a single LUT entry
	46	*/
	47	static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
	48	u32 streamid)
	49	{
	50	/* leave mask as all zeroes, want to match all bits */
	51	lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
	52	lut_writel(pcie, streamid \| PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
	53	}
	54
	55	/*
	56	* An msi-map is a property to be added to the pci controller
	57	* node. It is a table, where each entry consists of 4 fields
	58	* e.g.:
	59	*
	60	* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
	61	* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
	62	*/
485304af WK	63	static void fdt_pcie_set_msi_map_entry_ls(void blob, struct ls_pcie pcie,
485304af WK	64	u32 devid, u32 streamid)
80afc63f ML	65	{
	66	u32 *prop;
	67	u32 phandle;
	68	int nodeoffset;
0aaa1a90 HZ	69	uint svr;
0aaa1a90 HZ	70	char *compat = NULL;
80afc63f ML	71
	72	/* find pci controller node */
	73	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
	74	pcie->dbi_res.start);
	75	if (nodeoffset < 0) {
19538f30	76	#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
0aaa1a90 HZ	77	svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
0aaa1a90 HZ	78	if (svr == SVR_LS2088A \|\| svr == SVR_LS2084A \|\|
e809e747 PJ	79	svr == SVR_LS2048A \|\| svr == SVR_LS2044A \|\|
e809e747 PJ	80	svr == SVR_LS2081A \|\| svr == SVR_LS2041A)
0aaa1a90 HZ	81	compat = "fsl,ls2088a-pcie";
	82	else
	83	compat = CONFIG_FSL_PCIE_COMPAT;
	84	if (compat)
	85	nodeoffset = fdt_node_offset_by_compat_reg(blob,
	86	compat, pcie->dbi_res.start);
	87	#endif
80afc63f ML	88	if (nodeoffset < 0)
80afc63f ML	89	return;
80afc63f ML	90	}
	91
	92	/* get phandle to MSI controller */
	93	prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
	94	if (prop == NULL) {
	95	debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
	96	__func__, pcie->idx);
	97	return;
	98	}
	99	phandle = fdt32_to_cpu(*prop);
	100
	101	/* set one msi-map row */
	102	fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
	103	fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
	104	fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
	105	fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
	106	}
	107
78be6222 BB	108	/*
	109	* An iommu-map is a property to be added to the pci controller
	110	* node. It is a table, where each entry consists of 4 fields
	111	* e.g.:
	112	*
	113	* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
	114	* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
	115	*/
485304af WK	116	static void fdt_pcie_set_iommu_map_entry_ls(void blob, struct ls_pcie pcie,
485304af WK	117	u32 devid, u32 streamid)
78be6222 BB	118	{
	119	u32 *prop;
	120	u32 iommu_map[4];
	121	int nodeoffset;
	122	int lenp;
4b97a824 BB	123	uint svr;
4b97a824 BB	124	char *compat = NULL;
78be6222 BB	125
	126	/* find pci controller node */
	127	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
	128	pcie->dbi_res.start);
	129	if (nodeoffset < 0) {
	130	#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
4b97a824 BB	131	svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
	132	if (svr == SVR_LS2088A \|\| svr == SVR_LS2084A \|\|
	133	svr == SVR_LS2048A \|\| svr == SVR_LS2044A \|\|
	134	svr == SVR_LS2081A \|\| svr == SVR_LS2041A)
	135	compat = "fsl,ls2088a-pcie";
	136	else
	137	compat = CONFIG_FSL_PCIE_COMPAT;
	138
	139	if (compat)
	140	nodeoffset = fdt_node_offset_by_compat_reg(blob,
	141	compat, pcie->dbi_res.start);
	142	#endif
78be6222 BB	143	if (nodeoffset < 0)
78be6222 BB	144	return;
78be6222 BB	145	}
	146
	147	/* get phandle to iommu controller */
	148	prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
	149	if (prop == NULL) {
	150	debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
	151	__func__, pcie->idx);
	152	return;
	153	}
	154
	155	/* set iommu-map row */
	156	iommu_map[0] = cpu_to_fdt32(devid);
	157	iommu_map[1] = *++prop;
	158	iommu_map[2] = cpu_to_fdt32(streamid);
	159	iommu_map[3] = cpu_to_fdt32(1);
	160
	161	if (devid == 0) {
	162	fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
	163	iommu_map, 16);
	164	} else {
	165	fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
	166	}
	167	}
	168
485304af	169	static void fdt_fixup_pcie_ls(void *blob)
80afc63f ML	170	{
	171	struct udevice dev, bus;
	172	struct ls_pcie *pcie;
	173	int streamid;
	174	int index;
	175	pci_dev_t bdf;
	176
	177	/* Scan all known buses */
	178	for (pci_find_first_device(&dev);
	179	dev;
	180	pci_find_next_device(&dev)) {
	181	for (bus = dev; device_is_on_pci_bus(bus);)
	182	bus = bus->parent;
	183	pcie = dev_get_priv(bus);
	184
d20eb7a6	185	streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
80afc63f ML	186	if (streamid < 0) {
	187	debug("ERROR: no stream ids free\n");
	188	continue;
d20eb7a6 WK	189	} else {
d20eb7a6 WK	190	pcie->stream_id_cur++;
80afc63f ML	191	}
	192
	193	index = ls_pcie_next_lut_index(pcie);
	194	if (index < 0) {
	195	debug("ERROR: no LUT indexes free\n");
	196	continue;
	197	}
	198
	199	/* the DT fixup must be relative to the hose first_busno */
	200	bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
	201	/* map PCI b.d.f to streamID in LUT */
	202	ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
	203	streamid);
	204	/* update msi-map in device tree */
485304af WK	205	fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
485304af WK	206	streamid);
78be6222	207	/* update iommu-map in device tree */
485304af WK	208	fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
485304af WK	209	streamid);
80afc63f	210	}
9c2969e9	211	pcie_board_fix_fdt(blob);
80afc63f ML	212	}
	213	#endif
	214
59a557f3	215	static void ft_pcie_rc_fix(void blob, struct ls_pcie pcie)
80afc63f ML	216	{
80afc63f ML	217	int off;
0aaa1a90 HZ	218	uint svr;
0aaa1a90 HZ	219	char *compat = NULL;
80afc63f ML	220
	221	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
	222	pcie->dbi_res.start);
	223	if (off < 0) {
19538f30	224	#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
0aaa1a90 HZ	225	svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
0aaa1a90 HZ	226	if (svr == SVR_LS2088A \|\| svr == SVR_LS2084A \|\|
e809e747 PJ	227	svr == SVR_LS2048A \|\| svr == SVR_LS2044A \|\|
e809e747 PJ	228	svr == SVR_LS2081A \|\| svr == SVR_LS2041A)
0aaa1a90 HZ	229	compat = "fsl,ls2088a-pcie";
	230	else
	231	compat = CONFIG_FSL_PCIE_COMPAT;
	232	if (compat)
	233	off = fdt_node_offset_by_compat_reg(blob,
	234	compat, pcie->dbi_res.start);
	235	#endif
80afc63f ML	236	if (off < 0)
80afc63f ML	237	return;
80afc63f ML	238	}
80afc63f ML	239
59a557f3 XB	240	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
	241	fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
	242	else
	243	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
	244	}
	245
	246	static void ft_pcie_ep_fix(void blob, struct ls_pcie pcie)
	247	{
	248	int off;
	249
63618e71	250	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
59a557f3 XB	251	pcie->dbi_res.start);
	252	if (off < 0)
	253	return;
	254
	255	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
80afc63f ML	256	fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
	257	else
	258	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
	259	}
	260
59a557f3 XB	261	static void ft_pcie_ls_setup(void blob, struct ls_pcie pcie)
	262	{
	263	ft_pcie_ep_fix(blob, pcie);
	264	ft_pcie_rc_fix(blob, pcie);
	265	}
	266
80afc63f	267	/* Fixup Kernel DT for PCIe */
1185b229	268	void ft_pci_setup_ls(void blob, bd_t bd)
80afc63f ML	269	{
	270	struct ls_pcie *pcie;
	271
	272	list_for_each_entry(pcie, &ls_pcie_list, list)
	273	ft_pcie_ls_setup(blob, pcie);
	274
47d17362	275	#if defined(CONFIG_FSL_LSCH3) \|\| defined(CONFIG_FSL_LSCH2)
485304af	276	fdt_fixup_pcie_ls(blob);
80afc63f ML	277	#endif
80afc63f ML	278	}
80afc63f	279
a7294aba	280	#else /* !CONFIG_OF_BOARD_SETUP */
1185b229	281	void ft_pci_setup_ls(void blob, bd_t bd)
a7294aba HZ	282	{
	283	}
	284	#endif