[u-boot.git] / drivers / mmc / exynos_dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>

#define	DWMMC_MAX_CH_NUM		4
#define	DWMMC_MAX_FREQ			52000000
#define	DWMMC_MIN_FREQ			400000
#define	DWMMC_MMC0_CLKSEL_VAL		0x03030001
#define	DWMMC_MMC2_CLKSEL_VAL		0x03020001

/*
 * Function used as callback function to initialise the
 * CLKSEL register for every mmc channel.
 */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}

unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
{
	unsigned long sclk;
	int8_t clk_div;

	/*
	 * Since SDCLKIN is divided inside controller by the DIVRATIO
	 * value set in the CLKSEL register, we need to use the same output
	 * clock value to calculate the CLKDIV value.
	 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	 */
	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
			& DWMCI_DIVRATIO_MASK) + 1;
	sclk = get_mmc_clk(host->dev_index);

	/*
	 * Assume to know divider value.
	 * When clock unit is broken, need to set "host->div"
	 */
	return sclk / clk_div / (host->div + 1);
}

static void exynos_dwmci_board_init(struct dwmci_host *host)
{
	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
		dwmci_writel(host, EMMCP_SEND0, 0);
		dwmci_writel(host, EMMCP_CTRL0,
			     MPSCTRL_SECURE_READ_BIT |
			     MPSCTRL_SECURE_WRITE_BIT |
			     MPSCTRL_NON_SECURE_READ_BIT |
			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
	}

	/* Set to clksel_val at initial time */
	if (host->clksel_val)
		exynos_dwmci_clksel(host);
}

static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
	unsigned int div;
	unsigned long freq, sclk;

	if (host->bus_hz)
		freq = host->bus_hz;
	else
		freq = DWMMC_MAX_FREQ;

	/* request mmc clock vlaue of 52MHz.  */
	sclk = get_mmc_clk(index);
	div = DIV_ROUND_UP(sclk, freq);
	/* set the clock divisor for mmc */
	set_mmc_clk(index, div);

	host->name = "EXYNOS DWMMC";
#ifdef CONFIG_EXYNOS5420
	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
	host->board_init = exynos_dwmci_board_init;

	if (!host->clksel_val) {
		if (index == 0)
			host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
		else if (index == 2)
			host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	}

	host->caps = MMC_MODE_DDR_52MHz;
	host->clksel = exynos_dwmci_clksel;
	host->dev_index = index;
	host->get_mmc_clk = exynos_dwmci_get_clk;
	/* Add the mmc channel to be registered with mmc core */
	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
		printf("DWMMC%d registration failed\n", index);
		return -1;
	}
	return 0;
}

/*
 * This function adds the mmc channel to be registered with mmc core.
 * index -	mmc channel number.
 * regbase -	register base address of mmc channel specified in 'index'.
 * bus_width -	operating bus width of mmc channel specified in 'index'.
 * clksel -	value to be written into CLKSEL register in case of FDT.
 *		NULL in case od non-FDT.
 */
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
	struct dwmci_host *host = NULL;

	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		error("dwmci_host malloc fail!\n");
		return -ENOMEM;
	}

	host->ioaddr = (void *)regbase;
	host->buswidth = bus_width;

	if (clksel)
		host->clksel_val = clksel;

	return exynos_dwmci_core_init(host, index);
}

#ifdef CONFIG_OF_CONTROL
static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];

static int do_dwmci_init(struct dwmci_host *host)
{
	int index, flag, err;

	index = host->dev_index;

	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	err = exynos_pinmux_config(host->dev_id, flag);
	if (err) {
		printf("DWMMC%d not configure\n", index);
		return err;
	}

	return exynos_dwmci_core_init(host, index);
}

static int exynos_dwmci_get_config(const void *blob, int node,
					struct dwmci_host *host)
{
	int err = 0;
	u32 base, clksel_val, timing[3];

	/* Extract device id for each mmc channel */
	host->dev_id = pinmux_decode_periph_id(blob, node);

	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	if (host->dev_index == host->dev_id)
		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;


	/* Get the bus width from the device node */
	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	if (host->buswidth <= 0) {
		printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
		return -EINVAL;
	}

	/* Set the base address from the device node */
	base = fdtdec_get_addr(blob, node, "reg");
	if (!base) {
		printf("DWMMC%d: Can't get base address\n", host->dev_index);
		return -EINVAL;
	}
	host->ioaddr = (void *)base;

	/* Extract the timing info from the node */
	err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	if (err) {
		printf("DWMMC%d: Can't get sdr-timings for devider\n",
				host->dev_index);
		return -EINVAL;
	}

	clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
			DWMCI_SET_DRV_CLK(timing[1]) |
			DWMCI_SET_DIV_RATIO(timing[2]));
	if (clksel_val)
		host->clksel_val = clksel_val;

	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	host->div = fdtdec_get_int(blob, node, "div", 0);

	return 0;
}

static int exynos_dwmci_process_node(const void *blob,
					int node_list[], int count)
{
	struct dwmci_host *host;
	int i, node, err;

	for (i = 0; i < count; i++) {
		node = node_list[i];
		if (node <= 0)
			continue;
		host = &dwmci_host[i];
		err = exynos_dwmci_get_config(blob, node, host);
		if (err) {
			printf("%s: failed to decode dev %d\n", __func__, i);
			return err;
		}

		do_dwmci_init(host);
	}
	return 0;
}

int exynos_dwmmc_init(const void *blob)
{
	int compat_id;
	int node_list[DWMMC_MAX_CH_NUM];
	int err = 0, count;

	compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;

	count = fdtdec_find_aliases_for_id(blob, "mmc",
				compat_id, node_list, DWMMC_MAX_CH_NUM);
	err = exynos_dwmci_process_node(blob, node_list, count);

	return err;
}
#endif
Commit	Line	Data
d0ebbb8d JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d0ebbb8d JC	6	*/
	7
	8	#include <common.h>
d0ebbb8d	9	#include <dwmmc.h>
a082a2dd A	10	#include <fdtdec.h>
	11	#include <libfdt.h>
	12	#include <malloc.h>
d0ebbb8d JC	13	#include <asm/arch/dwmmc.h>
d0ebbb8d JC	14	#include <asm/arch/clk.h>
a082a2dd	15	#include <asm/arch/pinmux.h>
959198f7 JC	16	#include <asm/gpio.h>
959198f7 JC	17	#include <asm-generic/errno.h>
d0ebbb8d	18
a082a2dd A	19	#define DWMMC_MAX_CH_NUM 4
	20	#define DWMMC_MAX_FREQ 52000000
	21	#define DWMMC_MIN_FREQ 400000
	22	#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
	23	#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
d0ebbb8d	24
a082a2dd A	25	/*
	26	* Function used as callback function to initialise the
	27	* CLKSEL register for every mmc channel.
	28	*/
d0ebbb8d JC	29	static void exynos_dwmci_clksel(struct dwmci_host *host)
d0ebbb8d JC	30	{
a082a2dd A	31	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
a082a2dd A	32	}
d0ebbb8d	33
d3e016cc	34	unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
a082a2dd	35	{
d3e016cc RS	36	unsigned long sclk;
	37	int8_t clk_div;
	38
	39	/*
	40	* Since SDCLKIN is divided inside controller by the DIVRATIO
	41	* value set in the CLKSEL register, we need to use the same output
	42	* clock value to calculate the CLKDIV value.
	43	* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	44	*/
	45	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
	46	& DWMCI_DIVRATIO_MASK) + 1;
	47	sclk = get_mmc_clk(host->dev_index);
	48
959198f7 JC	49	/*
	50	* Assume to know divider value.
	51	* When clock unit is broken, need to set "host->div"
	52	*/
	53	return sclk / clk_div / (host->div + 1);
d0ebbb8d JC	54	}
d0ebbb8d JC	55
18ab6755 JC	56	static void exynos_dwmci_board_init(struct dwmci_host *host)
	57	{
	58	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
	59	dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
	60	dwmci_writel(host, EMMCP_SEND0, 0);
	61	dwmci_writel(host, EMMCP_CTRL0,
	62	MPSCTRL_SECURE_READ_BIT \|
	63	MPSCTRL_SECURE_WRITE_BIT \|
	64	MPSCTRL_NON_SECURE_READ_BIT \|
	65	MPSCTRL_NON_SECURE_WRITE_BIT \| MPSCTRL_VALID);
	66	}
3a33bb18 JC	67
	68	/* Set to clksel_val at initial time */
	69	if (host->clksel_val)
	70	exynos_dwmci_clksel(host);
18ab6755 JC	71	}
18ab6755 JC	72
959198f7	73	static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
d0ebbb8d	74	{
a082a2dd A	75	unsigned int div;
a082a2dd A	76	unsigned long freq, sclk;
959198f7 JC	77
	78	if (host->bus_hz)
	79	freq = host->bus_hz;
	80	else
	81	freq = DWMMC_MAX_FREQ;
	82
a082a2dd	83	/* request mmc clock vlaue of 52MHz. */
a082a2dd A	84	sclk = get_mmc_clk(index);
	85	div = DIV_ROUND_UP(sclk, freq);
	86	/* set the clock divisor for mmc */
	87	set_mmc_clk(index, div);
d0ebbb8d	88
a082a2dd	89	host->name = "EXYNOS DWMMC";
6f0b7caa RS	90	#ifdef CONFIG_EXYNOS5420
	91	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
	92	#endif
18ab6755	93	host->board_init = exynos_dwmci_board_init;
a082a2dd	94
959198f7 JC	95	if (!host->clksel_val) {
959198f7 JC	96	if (index == 0)
a082a2dd	97	host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
959198f7	98	else if (index == 2)
a082a2dd A	99	host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	100	}
	101
e09bd853	102	host->caps = MMC_MODE_DDR_52MHz;
d0ebbb8d JC	103	host->clksel = exynos_dwmci_clksel;
d0ebbb8d JC	104	host->dev_index = index;
b44fe83a	105	host->get_mmc_clk = exynos_dwmci_get_clk;
a082a2dd A	106	/* Add the mmc channel to be registered with mmc core */
a082a2dd A	107	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
dfcb683a	108	printf("DWMMC%d registration failed\n", index);
a082a2dd A	109	return -1;
	110	}
	111	return 0;
	112	}
	113
959198f7 JC	114	/*
	115	* This function adds the mmc channel to be registered with mmc core.
	116	* index - mmc channel number.
	117	* regbase - register base address of mmc channel specified in 'index'.
	118	* bus_width - operating bus width of mmc channel specified in 'index'.
	119	* clksel - value to be written into CLKSEL register in case of FDT.
	120	* NULL in case od non-FDT.
	121	*/
	122	int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
	123	{
	124	struct dwmci_host *host = NULL;
	125
	126	host = malloc(sizeof(struct dwmci_host));
	127	if (!host) {
	128	error("dwmci_host malloc fail!\n");
	129	return -ENOMEM;
	130	}
	131
	132	host->ioaddr = (void *)regbase;
	133	host->buswidth = bus_width;
	134
	135	if (clksel)
	136	host->clksel_val = clksel;
	137
	138	return exynos_dwmci_core_init(host, index);
	139	}
	140
a082a2dd	141	#ifdef CONFIG_OF_CONTROL
959198f7 JC	142	static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
	143
	144	static int do_dwmci_init(struct dwmci_host *host)
a082a2dd	145	{
959198f7	146	int index, flag, err;
a082a2dd	147
959198f7	148	index = host->dev_index;
a082a2dd	149
959198f7 JC	150	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	151	err = exynos_pinmux_config(host->dev_id, flag);
	152	if (err) {
dfcb683a	153	printf("DWMMC%d not configure\n", index);
959198f7 JC	154	return err;
959198f7 JC	155	}
a082a2dd	156
959198f7 JC	157	return exynos_dwmci_core_init(host, index);
959198f7 JC	158	}
d0ebbb8d	159
959198f7 JC	160	static int exynos_dwmci_get_config(const void *blob, int node,
	161	struct dwmci_host *host)
	162	{
	163	int err = 0;
	164	u32 base, clksel_val, timing[3];
d0ebbb8d	165
959198f7 JC	166	/* Extract device id for each mmc channel */
959198f7 JC	167	host->dev_id = pinmux_decode_periph_id(blob, node);
a082a2dd	168
dfcb683a JC	169	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	170	if (host->dev_index == host->dev_id)
	171	host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
	172
	173
959198f7 JC	174	/* Get the bus width from the device node */
	175	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	176	if (host->buswidth <= 0) {
dfcb683a	177	printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
959198f7 JC	178	return -EINVAL;
959198f7 JC	179	}
a082a2dd	180
959198f7 JC	181	/* Set the base address from the device node */
	182	base = fdtdec_get_addr(blob, node, "reg");
	183	if (!base) {
dfcb683a	184	printf("DWMMC%d: Can't get base address\n", host->dev_index);
959198f7 JC	185	return -EINVAL;
	186	}
	187	host->ioaddr = (void *)base;
	188
	189	/* Extract the timing info from the node */
	190	err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	191	if (err) {
dfcb683a JC	192	printf("DWMMC%d: Can't get sdr-timings for devider\n",
dfcb683a JC	193	host->dev_index);
959198f7 JC	194	return -EINVAL;
	195	}
	196
	197	clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) \|
	198	DWMCI_SET_DRV_CLK(timing[1]) \|
	199	DWMCI_SET_DIV_RATIO(timing[2]));
	200	if (clksel_val)
	201	host->clksel_val = clksel_val;
	202
	203	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	204	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	205	host->div = fdtdec_get_int(blob, node, "div", 0);
	206
	207	return 0;
	208	}
	209
	210	static int exynos_dwmci_process_node(const void *blob,
	211	int node_list[], int count)
	212	{
	213	struct dwmci_host *host;
	214	int i, node, err;
	215
	216	for (i = 0; i < count; i++) {
	217	node = node_list[i];
	218	if (node <= 0)
	219	continue;
	220	host = &dwmci_host[i];
	221	err = exynos_dwmci_get_config(blob, node, host);
a082a2dd	222	if (err) {
dfcb683a	223	printf("%s: failed to decode dev %d\n", __func__, i);
959198f7	224	return err;
a082a2dd A	225	}
a082a2dd A	226
959198f7	227	do_dwmci_init(host);
a082a2dd	228	}
d0ebbb8d JC	229	return 0;
d0ebbb8d JC	230	}
959198f7 JC	231
	232	int exynos_dwmmc_init(const void *blob)
	233	{
	234	int compat_id;
	235	int node_list[DWMMC_MAX_CH_NUM];
	236	int err = 0, count;
	237
	238	compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
	239
	240	count = fdtdec_find_aliases_for_id(blob, "mmc",
	241	compat_id, node_list, DWMMC_MAX_CH_NUM);
	242	err = exynos_dwmci_process_node(blob, node_list, count);
	243
	244	return err;
	245	}
a082a2dd	246	#endif