]> Git Repo - u-boot.git/blame - arch/arm/cpu/arm946es/cpu.c
common: Move enable/disable_interrupts out of common.h
[u-boot.git] / arch / arm / cpu / arm946es / cpu.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
74f4304e
WD
2/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <[email protected]>
6 *
7 * (C) Copyright 2002
792a09eb 8 * Gary Jennejohn, DENX Software Engineering, <[email protected]>
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9 */
10
11/*
12 * CPU specific code
13 */
14
15#include <common.h>
16#include <command.h>
9edefc27 17#include <cpu_func.h>
36bf446b 18#include <irq_func.h>
677e62f4 19#include <asm/system.h>
cd6cc344 20#include <asm/io.h>
74f4304e 21
b3acb6cd 22static void cache_flush(void);
74f4304e 23
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24int cleanup_before_linux (void)
25{
26 /*
27 * this function is called just before we call linux
28 * it prepares the processor for linux
29 *
30 * we turn off caches etc ...
31 */
32
9d3915b2 33 disable_interrupts();
74f4304e 34
fe7eb5d8
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35 /* ARM926E-S needs the protection unit enabled for the icache to have
36 * been enabled - left for possible later use
74f4304e 37 * should turn off the protection unit as well....
fe7eb5d8 38 */
74f4304e 39 /* turn off I/D-cache */
b3acb6cd
JCPV
40 icache_disable();
41 dcache_disable();
74f4304e 42 /* flush I/D-cache */
b3acb6cd
JCPV
43 cache_flush();
44
45 return 0;
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46}
47
b3acb6cd
JCPV
48/* flush I/D-cache */
49static void cache_flush (void)
74f4304e 50{
b3acb6cd 51 unsigned long i = 0;
74f4304e 52
b3acb6cd
JCPV
53 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
54 asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
74f4304e 55}
cd6cc344 56
e702146e 57#ifndef CONFIG_ARCH_INTEGRATOR
cd6cc344
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58
59__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
60{
61 writew(0x0, 0xfffece10);
62 writew(0x8, 0xfffece10);
63 for (;;)
64 ;
65}
66
e702146e 67#endif /* #ifdef CONFIG_ARCH_INTEGRATOR */
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