[u-boot.git] / board / xilinx / versal / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
 * Michal Simek <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <fdtdec.h>
#include <init.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include "../common/board.h"

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC;
#endif

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA_VERSALPL)
	fpga_init();
	fpga_add(fpga_xilinx, &versalpl);
#endif

	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
		xilinx_read_eeprom();

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	debug("iou_switch ctrl div0 %x\n",
	      readl(&crlapb_base->iou_switch_ctrl));

	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
	       &crlapb_base->iou_switch_ctrl);

	/* Global timer init - Program time stamp reference clk */
	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	debug("ref ctrl 0x%x\n",
	      readl(&crlapb_base->timestamp_ref_ctrl));

	/* Clear reset of timestamp reg */
	writel(0, &crlapb_base->rst_timestamp);

	/*
	 * Program freq register in System counter and
	 * enable system counter.
	 */
	writel(COUNTER_FREQUENCY,
	       &iou_scntr_secure->base_frequency_id_register);

	debug("counter val 0x%x\n",
	      readl(&iou_scntr_secure->base_frequency_id_register));

	writel(IOU_SCNTRS_CONTROL_EN,
	       &iou_scntr_secure->counter_control_register);

	debug("scntrs control 0x%x\n",
	      readl(&iou_scntr_secure->counter_control_register));
	debug("timer 0x%llx\n", get_ticks());
	debug("timer 0x%llx\n", get_ticks());

	return 0;
}

static u8 versal_get_bootmode(void)
{
	u8 bootmode;
	u32 reg = 0;

	reg = readl(&crp_base->boot_mode_usr);

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	return bootmode;
}

int board_late_init(void)
{
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
		return 0;

	bootmode = versal_get_bootmode();

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "dfu_usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "jtag pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
		puts("QSPI_MODE_24\n");
		mode = "xspi0";
		break;
	case QSPI_MODE_32BIT:
		puts("QSPI_MODE_32\n");
		mode = "xspi0";
		break;
	case OSPI_MODE:
		puts("OSPI_MODE\n");
		mode = "xspi0";
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from EMMC but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1040000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));

		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));

		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	return board_late_init_xilinx();
}

int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base_lowest() != 0)
		return -EINVAL;

	return 0;
}

void reset_cpu(void)
{
}
Commit	Line	Data
ec48b6c9 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 - 2018 Xilinx, Inc.
	4	* Michal Simek <[email protected]>
	5	*/
	6
	7	#include <common.h>
9a3b4ceb	8	#include <cpu_func.h>
09140113	9	#include <env.h>
ec48b6c9	10	#include <fdtdec.h>
5255932f	11	#include <init.h>
f7ae49fc	12	#include <log.h>
ec48b6c9	13	#include <malloc.h>
1045315d	14	#include <time.h>
90526e9f	15	#include <asm/cache.h>
401d1c4f	16	#include <asm/global_data.h>
ec48b6c9 MS	17	#include <asm/io.h>
ec48b6c9 MS	18	#include <asm/arch/hardware.h>
aef149e9	19	#include <asm/arch/sys_proto.h>
bfd092f9 SDPP	20	#include <dm/device.h>
bfd092f9 SDPP	21	#include <dm/uclass.h>
26e054c9	22	#include <versalpl.h>
80fdef12	23	#include "../common/board.h"
ec48b6c9 MS	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
26e054c9 SDPP	27	#if defined(CONFIG_FPGA_VERSALPL)
	28	static xilinx_desc versalpl = XILINX_VERSAL_DESC;
	29	#endif
	30
ec48b6c9 MS	31	int board_init(void)
	32	{
	33	printf("EL Level:\tEL%d\n", current_el());
	34
26e054c9 SDPP	35	#if defined(CONFIG_FPGA_VERSALPL)
	36	fpga_init();
	37	fpga_add(fpga_xilinx, &versalpl);
	38	#endif
	39
d61728c8 MS	40	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
	41	xilinx_read_eeprom();
	42
ec48b6c9 MS	43	return 0;
	44	}
	45
	46	int board_early_init_r(void)
	47	{
fb771793 MS	48	u32 val;
	49
	50	if (current_el() != 3)
	51	return 0;
	52
47a766f9 MS	53	debug("iou_switch ctrl div0 %x\n",
	54	readl(&crlapb_base->iou_switch_ctrl));
	55
fb771793	56	writel(IOU_SWITCH_CTRL_CLKACT_BIT \|
47a766f9	57	(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
fb771793 MS	58	&crlapb_base->iou_switch_ctrl);
	59
	60	/* Global timer init - Program time stamp reference clk */
	61	val = readl(&crlapb_base->timestamp_ref_ctrl);
	62	val \|= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	63	writel(val, &crlapb_base->timestamp_ref_ctrl);
	64
	65	debug("ref ctrl 0x%x\n",
	66	readl(&crlapb_base->timestamp_ref_ctrl));
	67
	68	/* Clear reset of timestamp reg */
	69	writel(0, &crlapb_base->rst_timestamp);
	70
	71	/*
	72	* Program freq register in System counter and
	73	* enable system counter.
	74	*/
	75	writel(COUNTER_FREQUENCY,
	76	&iou_scntr_secure->base_frequency_id_register);
	77
	78	debug("counter val 0x%x\n",
	79	readl(&iou_scntr_secure->base_frequency_id_register));
	80
	81	writel(IOU_SCNTRS_CONTROL_EN,
	82	&iou_scntr_secure->counter_control_register);
	83
	84	debug("scntrs control 0x%x\n",
	85	readl(&iou_scntr_secure->counter_control_register));
	86	debug("timer 0x%llx\n", get_ticks());
	87	debug("timer 0x%llx\n", get_ticks());
ec48b6c9 MS	88
	89	return 0;
	90	}
	91
51f6c52e	92	static u8 versal_get_bootmode(void)
bfd092f9	93	{
51f6c52e	94	u8 bootmode;
bfd092f9	95	u32 reg = 0;
51f6c52e MS	96
	97	reg = readl(&crp_base->boot_mode_usr);
	98
	99	if (reg >> BOOT_MODE_ALT_SHIFT)
	100	reg >>= BOOT_MODE_ALT_SHIFT;
	101
	102	bootmode = reg & BOOT_MODES_MASK;
	103
	104	return bootmode;
	105	}
	106
	107	int board_late_init(void)
	108	{
bfd092f9 SDPP	109	u8 bootmode;
	110	struct udevice *dev;
	111	int bootseq = -1;
	112	int bootseq_len = 0;
	113	int env_targets_len = 0;
	114	const char *mode;
	115	char *new_targets;
	116	char *env_targets;
	117
	118	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	119	debug("Saved variables - Skipping\n");
	120	return 0;
	121	}
	122
62b96262 MS	123	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
	124	return 0;
	125
51f6c52e	126	bootmode = versal_get_bootmode();
bfd092f9 SDPP	127
	128	puts("Bootmode: ");
	129	switch (bootmode) {
f0c16cd6 KR	130	case USB_MODE:
	131	puts("USB_MODE\n");
	132	mode = "dfu_usb";
	133	break;
bfd092f9 SDPP	134	case JTAG_MODE:
bfd092f9 SDPP	135	puts("JTAG_MODE\n");
3d865acb	136	mode = "jtag pxe dhcp";
bfd092f9 SDPP	137	break;
	138	case QSPI_MODE_24BIT:
	139	puts("QSPI_MODE_24\n");
	140	mode = "xspi0";
	141	break;
	142	case QSPI_MODE_32BIT:
	143	puts("QSPI_MODE_32\n");
	144	mode = "xspi0";
	145	break;
	146	case OSPI_MODE:
	147	puts("OSPI_MODE\n");
	148	mode = "xspi0";
	149	break;
	150	case EMMC_MODE:
	151	puts("EMMC_MODE\n");
7c5b7bb1 KR	152	if (uclass_get_device_by_name(UCLASS_MMC,
	153	"sdhci@f1050000", &dev)) {
	154	puts("Boot from EMMC but without SD1 enabled!\n");
	155	return -1;
	156	}
8b85dfc6	157	debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
7c5b7bb1	158	mode = "mmc";
8b85dfc6	159	bootseq = dev_seq(dev);
bfd092f9 SDPP	160	break;
	161	case SD_MODE:
	162	puts("SD_MODE\n");
	163	if (uclass_get_device_by_name(UCLASS_MMC,
	164	"sdhci@f1040000", &dev)) {
	165	puts("Boot from SD0 but without SD0 enabled!\n");
	166	return -1;
	167	}
8b85dfc6	168	debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
bfd092f9 SDPP	169
bfd092f9 SDPP	170	mode = "mmc";
8b85dfc6	171	bootseq = dev_seq(dev);
bfd092f9 SDPP	172	break;
	173	case SD1_LSHFT_MODE:
	174	puts("LVL_SHFT_");
	175	/* fall through */
	176	case SD_MODE1:
	177	puts("SD_MODE1\n");
	178	if (uclass_get_device_by_name(UCLASS_MMC,
	179	"sdhci@f1050000", &dev)) {
	180	puts("Boot from SD1 but without SD1 enabled!\n");
	181	return -1;
	182	}
8b85dfc6	183	debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
bfd092f9 SDPP	184
bfd092f9 SDPP	185	mode = "mmc";
8b85dfc6	186	bootseq = dev_seq(dev);
bfd092f9 SDPP	187	break;
	188	default:
	189	mode = "";
	190	printf("Invalid Boot Mode:0x%x\n", bootmode);
	191	break;
	192	}
	193
	194	if (bootseq >= 0) {
	195	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	196	debug("Bootseq len: %x\n", bootseq_len);
	197	}
	198
	199	/*
	200	* One terminating char + one byte for space between mode
	201	* and default boot_targets
	202	*/
	203	env_targets = env_get("boot_targets");
	204	if (env_targets)
	205	env_targets_len = strlen(env_targets);
	206
	207	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
	208	bootseq_len);
	209	if (!new_targets)
	210	return -ENOMEM;
	211
	212	if (bootseq >= 0)
	213	sprintf(new_targets, "%s%x %s", mode, bootseq,
	214	env_targets ? env_targets : "");
	215	else
	216	sprintf(new_targets, "%s %s", mode,
	217	env_targets ? env_targets : "");
	218
	219	env_set("boot_targets", new_targets);
	220
80fdef12	221	return board_late_init_xilinx();
bfd092f9 SDPP	222	}
bfd092f9 SDPP	223
ec48b6c9 MS	224	int dram_init_banksize(void)
ec48b6c9 MS	225	{
aef149e9 MS	226	int ret;
	227
	228	ret = fdtdec_setup_memory_banksize();
	229	if (ret)
	230	return ret;
	231
	232	mem_map_fill();
ec48b6c9 MS	233
	234	return 0;
	235	}
	236
	237	int dram_init(void)
	238	{
22b6bb6c	239	if (fdtdec_setup_mem_size_base_lowest() != 0)
ec48b6c9 MS	240	return -EINVAL;
	241
	242	return 0;
	243	}
	244
35b65dd8	245	void reset_cpu(void)
ec48b6c9 MS	246	{
ec48b6c9 MS	247	}