[u-boot.git] / board / renesas / silk / silk.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/silk/silk.c
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 */

#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	BIT(25)
#define MMC0_MSTP315	BIT(15)

#define SD1CKCR		0xE6150078
#define SD_97500KHZ	0x7

int board_early_init_f(void)
{
	/* TMU */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/* Set SD1 to the 97.5MHz */
	writel(SD_97500KHZ, SD1CKCR);

	return 0;
}

#define ETHERNET_PHY_RESET	56	/* GPIO 1 24 */

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Force ethernet PHY out of reset */
	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	mdelay(20);
	gpio_direction_output(ETHERNET_PHY_RESET, 1);
	udelay(1);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

/* porter has KSZ8041RNLI */
#define PHY_CONTROL1		0x1E
#define PHY_LED_MODE		0xC000
#define PHY_LED_MODE_ACK	0x4000
int board_phy_config(struct phy_device *phydev)
{
	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	ret &= ~PHY_LED_MODE;
	ret |= PHY_LED_MODE_ACK;
	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);

	return 0;
}

void reset_cpu(void)
{
	struct udevice *dev;
	const u8 pmic_bus = 1;
	const u8 pmic_addr = 0x5a;
	u8 data;
	int ret;

	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	if (ret)
		hang();

	ret = dm_i2c_read(dev, 0x13, &data, 1);
	if (ret)
		hang();

	data |= BIT(1);

	ret = dm_i2c_write(dev, 0x13, &data, 1);
	if (ret)
		hang();
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	const u32 load_magic = 0xb33fc0de;

	/* Block environment access if loaded using JTAG */
	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	    (op != ENVOP_INIT))
		return ENVL_UNKNOWN;

	if (prio)
		return ENVL_UNKNOWN;

	return ENVL_SPI_FLASH;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
3b7f0e10 VB	2	/*
	3	* board/renesas/silk/silk.c
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Copyright (C) 2015 Cogent Embedded, Inc.
3b7f0e10 VB	7	*/
	8
	9	#include <common.h>
9a3b4ceb	10	#include <cpu_func.h>
7b51b576	11	#include <env.h>
db41d65a	12	#include <hang.h>
691d719d	13	#include <init.h>
3b7f0e10	14	#include <malloc.h>
3cfab108	15	#include <dm.h>
401d1c4f	16	#include <asm/global_data.h>
3cfab108	17	#include <dm/platform_data/serial_sh.h>
f3998fdc	18	#include <env_internal.h>
3b7f0e10 VB	19	#include <asm/processor.h>
	20	#include <asm/mach-types.h>
	21	#include <asm/io.h>
cd93d625	22	#include <linux/bitops.h>
c05ed00a	23	#include <linux/delay.h>
1221ce45	24	#include <linux/errno.h>
3b7f0e10 VB	25	#include <asm/arch/sys_proto.h>
	26	#include <asm/gpio.h>
	27	#include <asm/arch/rmobile.h>
	28	#include <asm/arch/rcar-mstp.h>
	29	#include <asm/arch/mmc.h>
275ec28e	30	#include <asm/arch/sh_sdhi.h>
3b7f0e10 VB	31	#include <netdev.h>
	32	#include <miiphy.h>
	33	#include <i2c.h>
	34	#include <div64.h>
	35	#include "qos.h"
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
3b7f0e10 VB	39	void s_init(void)
	40	{
	41	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	42	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	43
	44	/* Watchdog init */
	45	writel(0xA5A5A500, &rwdt->rwtcsra);
	46	writel(0xA5A5A500, &swdt->swtcsra);
	47
	48	/* QoS */
	49	qos_init();
3b7f0e10 VB	50	}
3b7f0e10 VB	51
f7aa3cd4 MV	52	#define TMU0_MSTP125 BIT(25)
f7aa3cd4 MV	53	#define MMC0_MSTP315 BIT(15)
275ec28e VB	54
275ec28e VB	55	#define SD1CKCR 0xE6150078
f7aa3cd4	56	#define SD_97500KHZ 0x7
3b7f0e10 VB	57
	58	int board_early_init_f(void)
	59	{
	60	/* TMU */
	61	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	62
f7aa3cd4 MV	63	/* Set SD1 to the 97.5MHz */
f7aa3cd4 MV	64	writel(SD_97500KHZ, SD1CKCR);
3b7f0e10	65
3b7f0e10 VB	66	return 0;
	67	}
	68
f7aa3cd4 MV	69	#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
f7aa3cd4 MV	70
3b7f0e10 VB	71	int board_init(void)
	72	{
	73	/* adress of boot parameters */
	74	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	75
f7aa3cd4 MV	76	/* Force ethernet PHY out of reset */
	77	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	78	gpio_direction_output(ETHERNET_PHY_RESET, 0);
3b7f0e10	79	mdelay(20);
f7aa3cd4	80	gpio_direction_output(ETHERNET_PHY_RESET, 1);
3b7f0e10 VB	81	udelay(1);
	82
	83	return 0;
	84	}
	85
f7aa3cd4	86	int dram_init(void)
3b7f0e10	87	{
12308b12	88	if (fdtdec_setup_mem_size_base() != 0)
f7aa3cd4	89	return -EINVAL;
3b7f0e10	90
3b7f0e10	91	return 0;
3b7f0e10 VB	92	}
3b7f0e10 VB	93
f7aa3cd4	94	int dram_init_banksize(void)
3b7f0e10	95	{
f7aa3cd4 MV	96	fdtdec_setup_memory_banksize();
	97
	98	return 0;
3b7f0e10 VB	99	}
3b7f0e10 VB	100
f7aa3cd4 MV	101	/* porter has KSZ8041RNLI */
f7aa3cd4 MV	102	#define PHY_CONTROL1 0x1E
4bbd4642	103	#define PHY_LED_MODE 0xC000
f7aa3cd4 MV	104	#define PHY_LED_MODE_ACK 0x4000
f7aa3cd4 MV	105	int board_phy_config(struct phy_device *phydev)
3b7f0e10	106	{
f7aa3cd4 MV	107	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	108	ret &= ~PHY_LED_MODE;
	109	ret \|= PHY_LED_MODE_ACK;
	110	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
3b7f0e10 VB	111
	112	return 0;
	113	}
	114
35b65dd8	115	void reset_cpu(void)
3b7f0e10	116	{
f7aa3cd4 MV	117	struct udevice *dev;
f7aa3cd4 MV	118	const u8 pmic_bus = 1;
fe537802	119	const u8 pmic_addr = 0x5a;
f7aa3cd4 MV	120	u8 data;
	121	int ret;
	122
	123	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	124	if (ret)
	125	hang();
	126
	127	ret = dm_i2c_read(dev, 0x13, &data, 1);
	128	if (ret)
	129	hang();
3b7f0e10	130
f7aa3cd4 MV	131	data \|= BIT(1);
	132
	133	ret = dm_i2c_write(dev, 0x13, &data, 1);
	134	if (ret)
	135	hang();
3b7f0e10	136	}
3cfab108	137
f7aa3cd4 MV	138	enum env_location env_get_location(enum env_operation op, int prio)
	139	{
	140	const u32 load_magic = 0xb33fc0de;
3cfab108	141
f7aa3cd4 MV	142	/* Block environment access if loaded using JTAG */
	143	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	144	(op != ENVOP_INIT))
	145	return ENVL_UNKNOWN;
	146
	147	if (prio)
	148	return ENVL_UNKNOWN;
	149
	150	return ENVL_SPI_FLASH;
	151	}