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ba932bc8 CB |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright (C) 2017 Renesas Electronics | |
4 | * Copyright (C) Chris Brandt | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
9a3b4ceb | 8 | #include <cpu_func.h> |
691d719d | 9 | #include <init.h> |
401d1c4f | 10 | #include <asm/global_data.h> |
ba932bc8 CB |
11 | #include <asm/io.h> |
12 | #include <asm/arch/sys_proto.h> | |
13 | ||
14 | #define RZA1_WDT_BASE 0xfcfe0000 | |
15 | #define WTCSR 0x00 | |
16 | #define WTCNT 0x02 | |
17 | #define WRCSR 0x04 | |
18 | ||
19 | DECLARE_GLOBAL_DATA_PTR; | |
20 | ||
21 | int board_init(void) | |
22 | { | |
23 | gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); | |
24 | ||
25 | return 0; | |
26 | } | |
27 | ||
28 | int dram_init(void) | |
29 | { | |
30 | if (fdtdec_setup_mem_size_base() != 0) | |
31 | return -EINVAL; | |
32 | ||
33 | return 0; | |
34 | } | |
35 | ||
36 | int dram_init_banksize(void) | |
37 | { | |
38 | fdtdec_setup_memory_banksize(); | |
39 | ||
40 | return 0; | |
41 | } | |
42 | ||
35b65dd8 | 43 | void reset_cpu(void) |
ba932bc8 CB |
44 | { |
45 | /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ | |
46 | readb(RZA1_WDT_BASE + WRCSR); | |
47 | ||
48 | writew(0xa500, RZA1_WDT_BASE + WRCSR); | |
49 | writew(0x5a5f, RZA1_WDT_BASE + WRCSR); | |
50 | writew(0x5a00, RZA1_WDT_BASE + WTCNT); | |
51 | writew(0xa578, RZA1_WDT_BASE + WTCSR); | |
52 | ||
53 | for (;;) | |
54 | asm volatile("wfi"); | |
55 | } |