[u-boot.git] / drivers / net / fsl_mcdmafec.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <command.h>
#include <config.h>
#include <net.h>
#include <miiphy.h>

#undef	ET_DEBUG
#undef	MII_DEBUG

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH		1520
#define PKT_MAXBUF_SIZE		1518
#define PKT_MINBUF_SIZE		64
#define PKT_MAXBLR_SIZE		1536
#define LAST_PKTBUFSRX		PKTBUFSRX - 1
#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)
#define FIFO_ERRSTAT		(FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)

/* RxBD bits definitions */
#define BD_ENET_RX_ERR	(BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
			 BD_ENET_RX_OV | BD_ENET_RX_TR)

#include <asm/immap.h>
#include <asm/fsl_mcdmafec.h>

#include "MCD_dma.h"

DECLARE_GLOBAL_DATA_PTR;

struct fec_info_dma fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
	{
	 0,			/* index */
	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phyname init */
	 0,			/* RX BD */
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_dma *)-1,	/* next */
	 FEC0_RX_TASK,		/* rxTask */
	 FEC0_TX_TASK,		/* txTask */
	 FEC0_RX_PRIORITY,	/* rxPri */
	 FEC0_TX_PRIORITY,	/* txPri */
	 FEC0_RX_INIT,		/* rxInit */
	 FEC0_TX_INIT,		/* txInit */
	 0,			/* usedTbdIndex */
	 0,			/* cleanTbdNum */
	 },
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
	{
	 1,			/* index */
	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phy name init */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
#else
	 0,			/* RX BD */
#endif
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_dma *)-1,	/* next */
	 FEC1_RX_TASK,		/* rxTask */
	 FEC1_TX_TASK,		/* txTask */
	 FEC1_RX_PRIORITY,	/* rxPri */
	 FEC1_TX_PRIORITY,	/* txPri */
	 FEC1_RX_INIT,		/* rxInit */
	 FEC1_TX_INIT,		/* txInit */
	 0,			/* usedTbdIndex */
	 0,			/* cleanTbdNum */
	 }
#endif
};

static int fec_send(struct eth_device *dev, void *packet, int length);
static int fec_recv(struct eth_device *dev);
static int fec_init(struct eth_device *dev, bd_t * bd);
static void fec_halt(struct eth_device *dev);

#ifdef ET_DEBUG
static void dbg_fec_regs(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);

	printf("=====\n");
	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	printf("r hash       %x - %x\n", (int)&fecp->rhr, fecp->rhr);
	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	printf("r_fdata      %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
	printf("r_fstat      %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
	printf("r_fctrl      %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
	printf("r_flrfp      %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
	printf("r_flwfp      %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
	printf("r_frfar      %x - %x\n", (int)&fecp->rfar, fecp->rfar);
	printf("r_frfrp      %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
	printf("r_frfwp      %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
	printf("t_fdata      %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
	printf("t_fstat      %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
	printf("t_fctrl      %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
	printf("t_flrfp      %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
	printf("t_flwfp      %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
	printf("t_ftfar      %x - %x\n", (int)&fecp->tfar, fecp->tfar);
	printf("t_ftfrp      %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
	printf("t_ftfwp      %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
	printf("frst         %x - %x\n", (int)&fecp->frst, fecp->frst);
	printf("ctcwr        %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
}
#endif

static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
				 int dup_spd)
{
	if ((dup_spd >> 16) == FULL) {
		/* Set maximum frame length */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
		    FEC_RCR_PROM | 0x100;
		fecp->tcr = FEC_TCR_FDEN;
	} else {
		/* Half duplex mode */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
		fecp->tcr &= ~FEC_TCR_FDEN;
	}

	if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef MII_DEBUG
		printf("100Mbps\n");
#endif
		bd->bi_ethspeed = 100;
	} else {
#ifdef MII_DEBUG
		printf("10Mbps\n");
#endif
		bd->bi_ethspeed = 10;
	}
}

static int fec_send(struct eth_device *dev, void *packet, int length)
{
	struct fec_info_dma *info = dev->priv;
	cbd_t *pTbd, *pUsedTbd;
	u16 phyStatus;

	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);

	/* process all the consumed TBDs */
	while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
		pUsedTbd = &info->txbd[info->usedTbdIdx];
		if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
#ifdef ET_DEBUG
			printf("Cannot clean TBD %d, in use\n",
			       info->cleanTbdNum);
#endif
			return 0;
		}

		/* clean this buffer descriptor */
		if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
			pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
		else
			pUsedTbd->cbd_sc = 0;

		/* update some indeces for a correct handling of the TBD ring */
		info->cleanTbdNum++;
		info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
	}

	/* Check for valid length of data. */
	if ((length > 1500) || (length <= 0)) {
		return -1;
	}

	/* Check the number of vacant TxBDs. */
	if (info->cleanTbdNum < 1) {
		printf("No available TxBDs ...\n");
		return -1;
	}

	/* Get the first TxBD to send the mac header */
	pTbd = &info->txbd[info->txIdx];
	pTbd->cbd_datlen = length;
	pTbd->cbd_bufaddr = (u32) packet;
	pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
	info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;

	/* Enable DMA transmit task */
	MCD_continDma(info->txTask);

	info->cleanTbdNum -= 1;

	/* wait until frame is sent . */
	while (pTbd->cbd_sc & BD_ENET_TX_READY) {
		udelay(10);
	}

	return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
}

static int fec_recv(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);

	cbd_t *prbd = &info->rxbd[info->rxIdx];
	u32 ievent;
	int frame_length, len = 0;

	/* Check if any critical events have happened */
	ievent = fecp->eir;
	if (ievent != 0) {
		fecp->eir = ievent;

		if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
			printf("fec_recv: error\n");
			fec_halt(dev);
			fec_init(dev, NULL);
			return 0;
		}

		if (ievent & FEC_EIR_HBERR) {
			/* Heartbeat error */
			fecp->tcr |= FEC_TCR_GTS;
		}

		if (ievent & FEC_EIR_GRA) {
			/* Graceful stop complete */
			if (fecp->tcr & FEC_TCR_GTS) {
				printf("fec_recv: tcr_gts\n");
				fec_halt(dev);
				fecp->tcr &= ~FEC_TCR_GTS;
				fec_init(dev, NULL);
			}
		}
	}

	if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
		if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
		    !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
		    ((prbd->cbd_datlen - 4) > 14)) {

			/* Get buffer address and size */
			frame_length = prbd->cbd_datlen - 4;

			/* Fill the buffer and pass it to upper layers */
			net_process_received_packet((uchar *)prbd->cbd_bufaddr,
						    frame_length);
			len = frame_length;
		}

		/* Reset buffer descriptor as empty */
		if ((info->rxIdx) == (PKTBUFSRX - 1))
			prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
		else
			prbd->cbd_sc = BD_ENET_RX_EMPTY;

		prbd->cbd_datlen = PKTSIZE_ALIGN;

		/* Now, we have an empty RxBD, restart the DMA receive task */
		MCD_continDma(info->rxTask);

		/* Increment BD count */
		info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
	}

	return len;
}

static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
{
	u8 currByte;		/* byte for which to compute the CRC */
	int byte;		/* loop - counter */
	int bit;		/* loop - counter */
	u32 crc = 0xffffffff;	/* initial value */

	for (byte = 0; byte < 6; byte++) {
		currByte = mac[byte];
		for (bit = 0; bit < 8; bit++) {
			if ((currByte & 0x01) ^ (crc & 0x01)) {
				crc >>= 1;
				crc = crc ^ 0xedb88320;
			} else {
				crc >>= 1;
			}
			currByte >>= 1;
		}
	}

	crc = crc >> 26;

	/* Set individual hash table register */
	if (crc >= 32) {
		fecp->ialr = (1 << (crc - 32));
		fecp->iaur = 0;
	} else {
		fecp->ialr = 0;
		fecp->iaur = (1 << crc);
	}

	/* Set physical address */
	fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
	fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;

	/* Clear multicast address hash table */
	fecp->gaur = 0;
	fecp->galr = 0;
}

static int fec_init(struct eth_device *dev, bd_t * bd)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
	int i;
	uchar enetaddr[6];

#ifdef ET_DEBUG
	printf("fec_init: iobase 0x%08x ...\n", info->iobase);
#endif

	fecpin_setclear(dev, 1);

	fec_halt(dev);

#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
	defined (CONFIG_SYS_DISCOVER_PHY)

	mii_init();

	set_fec_duplex_speed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif				/* CONFIG_CMD_MII || CONFIG_MII */

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set station address   */
	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
		eth_env_get_enetaddr("ethaddr", enetaddr);
	else
		eth_env_get_enetaddr("eth1addr", enetaddr);
	fec_set_hwaddr(fecp, enetaddr);

	/* Set Opcode/Pause Duration Register */
	fecp->opd = 0x00010020;

	/* Setup Buffers and Buffer Desriptors */
	info->rxIdx = 0;
	info->txIdx = 0;

	/* Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:     Empty, Wrap */
	for (i = 0; i < PKTBUFSRX; i++) {
		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
		info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
	}
	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:    Last, Tx CRC */
	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
		info->txbd[i].cbd_sc = 0;
		info->txbd[i].cbd_datlen = 0;
		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	}
	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;

	info->usedTbdIdx = 0;
	info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;

	/* Set Rx FIFO alarm and granularity value */
	fecp->rfcr = 0x0c000000;
	fecp->rfar = 0x0000030c;

	/* Set Tx FIFO granularity value */
	fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
	fecp->tfar = 0x00000080;

	fecp->tfwr = 0x2;
	fecp->ctcwr = 0x03000000;

	/* Enable DMA receive task */
	MCD_startDma(info->rxTask,	/* Dma channel */
		     (s8 *) info->rxbd,	/*Source Address */
		     0,		/* Source increment */
		     (s8 *) (&fecp->rfdr),	/* dest */
		     4,		/* dest increment */
		     0,		/* DMA size */
		     4,		/* xfer size */
		     info->rxInit,	/* initiator */
		     info->rxPri,	/* priority */
		     (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
	    );

	/* Enable DMA tx task with no ready buffer descriptors */
	MCD_startDma(info->txTask,	/* Dma channel */
		     (s8 *) info->txbd,	/*Source Address */
		     0,		/* Source increment */
		     (s8 *) (&fecp->tfdr),	/* dest */
		     4,		/* dest incr */
		     0,		/* DMA size */
		     4,		/* xfer size */
		     info->txInit,	/* initiator */
		     info->txPri,	/* priority */
		     (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
	    );

	/* Now enable the transmit and receive processing */
	fecp->ecr |= FEC_ECR_ETHER_EN;

	return 1;
}

static void fec_halt(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
	int counter = 0xffff;

	/* issue graceful stop command to the FEC transmitter if necessary */
	fecp->tcr |= FEC_TCR_GTS;

	/* wait for graceful stop to register */
	while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;

	/* Disable DMA tasks */
	MCD_killDma(info->txTask);
	MCD_killDma(info->rxTask);

	/* Disable the Ethernet Controller */
	fecp->ecr &= ~FEC_ECR_ETHER_EN;

	/* Clear FIFO status registers */
	fecp->rfsr &= FIFO_ERRSTAT;
	fecp->tfsr &= FIFO_ERRSTAT;

	fecp->frst = 0x01000000;

	/* Issue a reset command to the FEC chip */
	fecp->ecr |= FEC_ECR_RESET;

	/* wait at least 20 clock cycles */
	udelay(10000);

#ifdef ET_DEBUG
	printf("Ethernet task stopped\n");
#endif
}

int mcdmafec_initialize(bd_t * bis)
{
	struct eth_device *dev;
	int i;
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
	u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
#endif

	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {

		dev =
		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
						  sizeof *dev);
		if (dev == NULL)
			hang();

		memset(dev, 0, sizeof(*dev));

		sprintf(dev->name, "FEC%d", fec_info[i].index);

		dev->priv = &fec_info[i];
		dev->init = fec_init;
		dev->halt = fec_halt;
		dev->send = fec_send;
		dev->recv = fec_recv;

		/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
		tmp = (u32)fec_info[i].rxbd;
		fec_info[i].txbd =
		    (cbd_t *)((u32)fec_info[i].txbd + tmp +
		    (PKTBUFSRX * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbd;
		fec_info[i].txbuf =
		    (char *)((u32)fec_info[i].txbuf + tmp +
		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbuf;
#else
		fec_info[i].rxbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (PKTBUFSRX * sizeof(cbd_t)));
		fec_info[i].txbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		fec_info[i].txbuf =
		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif

#ifdef ET_DEBUG
		printf("rxbd %x txbd %x\n",
		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif

		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);

		eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
		int retval;
		struct mii_dev *mdiodev = mdio_alloc();
		if (!mdiodev)
			return -ENOMEM;
		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
		mdiodev->read = mcffec_miiphy_read;
		mdiodev->write = mcffec_miiphy_write;

		retval = mdio_register(mdiodev);
		if (retval < 0)
			return retval;
#endif

		if (i > 0)
			fec_info[i - 1].next = &fec_info[i];
	}
	fec_info[i - 1].next = &fec_info[0];

	/* default speed */
	bis->bi_ethspeed = 10;

	return 0;
}
Commit	Line	Data
777d1abd TL	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* (C) Copyright 2007 Freescale Semiconductor, Inc.
	6	* TsiChung Liew ([email protected])
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
777d1abd TL	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <command.h>
	14	#include <config.h>
	15	#include <net.h>
	16	#include <miiphy.h>
	17
777d1abd TL	18	#undef ET_DEBUG
	19	#undef MII_DEBUG
	20
	21	/* Ethernet Transmit and Receive Buffers */
	22	#define DBUF_LENGTH 1520
	23	#define PKT_MAXBUF_SIZE 1518
	24	#define PKT_MINBUF_SIZE 64
	25	#define PKT_MAXBLR_SIZE 1536
	26	#define LAST_PKTBUFSRX PKTBUFSRX - 1
	27	#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY)
	28	#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY \| BD_ENET_TX_LAST)
	29	#define FIFO_ERRSTAT (FIFO_STAT_RXW \| FIFO_STAT_UF \| FIFO_STAT_OF)
	30
	31	/* RxBD bits definitions */
	32	#define BD_ENET_RX_ERR (BD_ENET_RX_LG \| BD_ENET_RX_NO \| BD_ENET_RX_CR \| \
	33	BD_ENET_RX_OV \| BD_ENET_RX_TR)
	34
777d1abd TL	35	#include <asm/immap.h>
	36	#include <asm/fsl_mcdmafec.h>
	37
	38	#include "MCD_dma.h"
	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	struct fec_info_dma fec_info[] = {
6d0f6bcf	43	#ifdef CONFIG_SYS_FEC0_IOBASE
777d1abd TL	44	{
777d1abd TL	45	0, /* index */
6d0f6bcf JCPV	46	CONFIG_SYS_FEC0_IOBASE, /* io base */
	47	CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
	48	CONFIG_SYS_FEC0_MIIBASE, /* mii base */
777d1abd TL	49	-1, /* phy_addr */
	50	0, /* duplex and speed */
	51	0, /* phy name */
	52	0, /* phyname init */
	53	0, /* RX BD */
	54	0, /* TX BD */
	55	0, /* rx Index */
	56	0, /* tx Index */
	57	0, /* tx buffer */
	58	0, /* initialized flag */
	59	(struct fec_info_dma )-1, / next */
	60	FEC0_RX_TASK, /* rxTask */
	61	FEC0_TX_TASK, /* txTask */
	62	FEC0_RX_PRIORITY, /* rxPri */
	63	FEC0_TX_PRIORITY, /* txPri */
	64	FEC0_RX_INIT, /* rxInit */
	65	FEC0_TX_INIT, /* txInit */
	66	0, /* usedTbdIndex */
	67	0, /* cleanTbdNum */
	68	},
	69	#endif
6d0f6bcf	70	#ifdef CONFIG_SYS_FEC1_IOBASE
777d1abd TL	71	{
777d1abd TL	72	1, /* index */
6d0f6bcf JCPV	73	CONFIG_SYS_FEC1_IOBASE, /* io base */
	74	CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
	75	CONFIG_SYS_FEC1_MIIBASE, /* mii base */
777d1abd TL	76	-1, /* phy_addr */
	77	0, /* duplex and speed */
	78	0, /* phy name */
	79	0, /* phy name init */
6d0f6bcf	80	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
429be27c	81	(cbd_t )DBUF_LENGTH, / RX BD */
f32f7fe7	82	#else
777d1abd	83	0, /* RX BD */
f32f7fe7	84	#endif
777d1abd TL	85	0, /* TX BD */
	86	0, /* rx Index */
	87	0, /* tx Index */
	88	0, /* tx buffer */
	89	0, /* initialized flag */
	90	(struct fec_info_dma )-1, / next */
	91	FEC1_RX_TASK, /* rxTask */
	92	FEC1_TX_TASK, /* txTask */
	93	FEC1_RX_PRIORITY, /* rxPri */
	94	FEC1_TX_PRIORITY, /* txPri */
	95	FEC1_RX_INIT, /* rxInit */
	96	FEC1_TX_INIT, /* txInit */
	97	0, /* usedTbdIndex */
	98	0, /* cleanTbdNum */
	99	}
	100	#endif
	101	};
	102
10cbe3b6	103	static int fec_send(struct eth_device dev, void packet, int length);
777d1abd TL	104	static int fec_recv(struct eth_device *dev);
	105	static int fec_init(struct eth_device dev, bd_t bd);
	106	static void fec_halt(struct eth_device *dev);
	107
	108	#ifdef ET_DEBUG
	109	static void dbg_fec_regs(struct eth_device *dev)
	110	{
	111	struct fec_info_dma *info = dev->priv;
	112	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	113
	114	printf("=====\n");
	115	printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
	116	printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	117	printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	118	printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	119	printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	120	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	121	printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	122	printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
	123	printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	124	printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
	125	printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
	126	printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
	127	printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	128	printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	129	printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	130	printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
	131	printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	132	printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
	133	printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
	134	printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
	135	printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
	136	printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
	137	printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
	138	printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
	139	printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
	140	printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
	141	printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
	142	printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
	143	printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
	144	printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
	145	printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
	146	printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
	147	printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
	148	printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
	149	printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
	150	}
	151	#endif
	152
f32f7fe7 TL	153	static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
f32f7fe7 TL	154	int dup_spd)
777d1abd TL	155	{
	156	if ((dup_spd >> 16) == FULL) {
	157	/* Set maximum frame length */
	158	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \| FEC_RCR_MII_MODE \|
	159	FEC_RCR_PROM \| 0x100;
	160	fecp->tcr = FEC_TCR_FDEN;
	161	} else {
	162	/* Half duplex mode */
	163	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \|
	164	FEC_RCR_MII_MODE \| FEC_RCR_DRT;
	165	fecp->tcr &= ~FEC_TCR_FDEN;
	166	}
	167
	168	if ((dup_spd & 0xFFFF) == _100BASET) {
	169	#ifdef MII_DEBUG
	170	printf("100Mbps\n");
	171	#endif
	172	bd->bi_ethspeed = 100;
	173	} else {
	174	#ifdef MII_DEBUG
	175	printf("10Mbps\n");
	176	#endif
	177	bd->bi_ethspeed = 10;
	178	}
	179	}
	180
10cbe3b6	181	static int fec_send(struct eth_device dev, void packet, int length)
777d1abd TL	182	{
	183	struct fec_info_dma *info = dev->priv;
	184	cbd_t pTbd, pUsedTbd;
	185	u16 phyStatus;
	186
8ef583a0	187	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
777d1abd TL	188
777d1abd TL	189	/* process all the consumed TBDs */
6d0f6bcf	190	while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
777d1abd TL	191	pUsedTbd = &info->txbd[info->usedTbdIdx];
	192	if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
	193	#ifdef ET_DEBUG
	194	printf("Cannot clean TBD %d, in use\n",
	195	info->cleanTbdNum);
	196	#endif
	197	return 0;
	198	}
	199
	200	/* clean this buffer descriptor */
6d0f6bcf	201	if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
777d1abd TL	202	pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
	203	else
	204	pUsedTbd->cbd_sc = 0;
	205
	206	/* update some indeces for a correct handling of the TBD ring */
	207	info->cleanTbdNum++;
6d0f6bcf	208	info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	209	}
	210
	211	/* Check for valid length of data. */
	212	if ((length > 1500) \|\| (length <= 0)) {
	213	return -1;
	214	}
	215
	216	/* Check the number of vacant TxBDs. */
	217	if (info->cleanTbdNum < 1) {
	218	printf("No available TxBDs ...\n");
	219	return -1;
	220	}
	221
	222	/* Get the first TxBD to send the mac header */
	223	pTbd = &info->txbd[info->txIdx];
	224	pTbd->cbd_datlen = length;
	225	pTbd->cbd_bufaddr = (u32) packet;
	226	pTbd->cbd_sc \|= BD_ENET_TX_LAST \| BD_ENET_TX_TC \| BD_ENET_TX_READY;
6d0f6bcf	227	info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	228
	229	/* Enable DMA transmit task */
	230	MCD_continDma(info->txTask);
	231
	232	info->cleanTbdNum -= 1;
	233
	234	/* wait until frame is sent . */
	235	while (pTbd->cbd_sc & BD_ENET_TX_READY) {
	236	udelay(10);
	237	}
	238
	239	return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	240	}
	241
	242	static int fec_recv(struct eth_device *dev)
	243	{
	244	struct fec_info_dma *info = dev->priv;
	245	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	246
1fd92db8	247	cbd_t *prbd = &info->rxbd[info->rxIdx];
777d1abd TL	248	u32 ievent;
	249	int frame_length, len = 0;
	250
	251	/* Check if any critical events have happened */
	252	ievent = fecp->eir;
	253	if (ievent != 0) {
	254	fecp->eir = ievent;
	255
	256	if (ievent & (FEC_EIR_BABT \| FEC_EIR_TXERR \| FEC_EIR_RXERR)) {
	257	printf("fec_recv: error\n");
	258	fec_halt(dev);
	259	fec_init(dev, NULL);
	260	return 0;
	261	}
	262
	263	if (ievent & FEC_EIR_HBERR) {
	264	/* Heartbeat error */
	265	fecp->tcr \|= FEC_TCR_GTS;
	266	}
	267
	268	if (ievent & FEC_EIR_GRA) {
	269	/* Graceful stop complete */
	270	if (fecp->tcr & FEC_TCR_GTS) {
	271	printf("fec_recv: tcr_gts\n");
	272	fec_halt(dev);
	273	fecp->tcr &= ~FEC_TCR_GTS;
	274	fec_init(dev, NULL);
	275	}
	276	}
	277	}
	278
1fd92db8 JH	279	if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
	280	if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
	281	!(prbd->cbd_sc & BD_ENET_RX_ERR) &&
	282	((prbd->cbd_datlen - 4) > 14)) {
777d1abd TL	283
777d1abd TL	284	/* Get buffer address and size */
1fd92db8	285	frame_length = prbd->cbd_datlen - 4;
777d1abd TL	286
777d1abd TL	287	/* Fill the buffer and pass it to upper layers */
1fd92db8 JH	288	net_process_received_packet((uchar *)prbd->cbd_bufaddr,
1fd92db8 JH	289	frame_length);
777d1abd TL	290	len = frame_length;
	291	}
	292
	293	/* Reset buffer descriptor as empty */
	294	if ((info->rxIdx) == (PKTBUFSRX - 1))
1fd92db8	295	prbd->cbd_sc = (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY);
777d1abd	296	else
1fd92db8	297	prbd->cbd_sc = BD_ENET_RX_EMPTY;
777d1abd	298
1fd92db8	299	prbd->cbd_datlen = PKTSIZE_ALIGN;
777d1abd TL	300
	301	/* Now, we have an empty RxBD, restart the DMA receive task */
	302	MCD_continDma(info->rxTask);
	303
	304	/* Increment BD count */
	305	info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
	306	}
	307
	308	return len;
	309	}
	310
	311	static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
	312	{
	313	u8 currByte; /* byte for which to compute the CRC */
	314	int byte; /* loop - counter */
	315	int bit; /* loop - counter */
	316	u32 crc = 0xffffffff; /* initial value */
	317
	318	for (byte = 0; byte < 6; byte++) {
	319	currByte = mac[byte];
	320	for (bit = 0; bit < 8; bit++) {
	321	if ((currByte & 0x01) ^ (crc & 0x01)) {
	322	crc >>= 1;
	323	crc = crc ^ 0xedb88320;
	324	} else {
	325	crc >>= 1;
	326	}
	327	currByte >>= 1;
	328	}
	329	}
	330
	331	crc = crc >> 26;
	332
	333	/* Set individual hash table register */
	334	if (crc >= 32) {
	335	fecp->ialr = (1 << (crc - 32));
	336	fecp->iaur = 0;
	337	} else {
	338	fecp->ialr = 0;
	339	fecp->iaur = (1 << crc);
	340	}
	341
	342	/* Set physical address */
	343	fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
	344	fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
	345
	346	/* Clear multicast address hash table */
	347	fecp->gaur = 0;
	348	fecp->galr = 0;
	349	}
	350
	351	static int fec_init(struct eth_device dev, bd_t bd)
	352	{
	353	struct fec_info_dma *info = dev->priv;
	354	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	355	int i;
d3f87148	356	uchar enetaddr[6];
777d1abd TL	357
	358	#ifdef ET_DEBUG
	359	printf("fec_init: iobase 0x%08x ...\n", info->iobase);
	360	#endif
	361
	362	fecpin_setclear(dev, 1);
	363
	364	fec_halt(dev);
	365
	366	#if defined(CONFIG_CMD_MII) \|\| defined (CONFIG_MII) \|\| \
6d0f6bcf	367	defined (CONFIG_SYS_DISCOVER_PHY)
777d1abd TL	368
	369	mii_init();
	370
	371	set_fec_duplex_speed(fecp, bd, info->dup_spd);
	372	#else
6d0f6bcf	373	#ifndef CONFIG_SYS_DISCOVER_PHY
777d1abd	374	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) \| FECSPEED);
6d0f6bcf	375	#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
777d1abd TL	376	#endif /* CONFIG_CMD_MII \|\| CONFIG_MII */
	377
	378	/* We use strictly polling mode only */
	379	fecp->eimr = 0;
	380
	381	/* Clear any pending interrupt */
	382	fecp->eir = 0xffffffff;
	383
	384	/* Set station address */
d3f87148	385	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
35affd7a	386	eth_env_get_enetaddr("ethaddr", enetaddr);
d3f87148	387	else
35affd7a	388	eth_env_get_enetaddr("eth1addr", enetaddr);
d3f87148	389	fec_set_hwaddr(fecp, enetaddr);
777d1abd TL	390
	391	/* Set Opcode/Pause Duration Register */
	392	fecp->opd = 0x00010020;
	393
	394	/* Setup Buffers and Buffer Desriptors */
	395	info->rxIdx = 0;
	396	info->txIdx = 0;
	397
	398	/* Setup Receiver Buffer Descriptors (13.14.24.18)
	399	* Settings: Empty, Wrap */
	400	for (i = 0; i < PKTBUFSRX; i++) {
	401	info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	402	info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
1fd92db8	403	info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
777d1abd TL	404	}
	405	info->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	406
	407	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	408	* Settings: Last, Tx CRC */
6d0f6bcf	409	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
777d1abd TL	410	info->txbd[i].cbd_sc = 0;
	411	info->txbd[i].cbd_datlen = 0;
	412	info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	413	}
6d0f6bcf	414	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc \|= BD_ENET_TX_WRAP;
777d1abd TL	415
777d1abd TL	416	info->usedTbdIdx = 0;
6d0f6bcf	417	info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	418
	419	/* Set Rx FIFO alarm and granularity value */
	420	fecp->rfcr = 0x0c000000;
	421	fecp->rfar = 0x0000030c;
	422
	423	/* Set Tx FIFO granularity value */
	424	fecp->tfcr = FIFO_CTRL_FRAME \| FIFO_CTRL_GR(6) \| 0x00040000;
	425	fecp->tfar = 0x00000080;
	426
	427	fecp->tfwr = 0x2;
	428	fecp->ctcwr = 0x03000000;
	429
	430	/* Enable DMA receive task */
	431	MCD_startDma(info->rxTask, /* Dma channel */
	432	(s8 ) info->rxbd, /Source Address */
	433	0, /* Source increment */
	434	(s8 ) (&fecp->rfdr), / dest */
	435	4, /* dest increment */
	436	0, /* DMA size */
	437	4, /* xfer size */
	438	info->rxInit, /* initiator */
	439	info->rxPri, /* priority */
	440	(MCD_FECRX_DMA \| MCD_TT_FLAGS_DEF), /* Flags */
	441	(MCD_NO_CSUM \| MCD_NO_BYTE_SWAP) /* Function description */
	442	);
	443
	444	/* Enable DMA tx task with no ready buffer descriptors */
	445	MCD_startDma(info->txTask, /* Dma channel */
	446	(s8 ) info->txbd, /Source Address */
	447	0, /* Source increment */
	448	(s8 ) (&fecp->tfdr), / dest */
	449	4, /* dest incr */
	450	0, /* DMA size */
	451	4, /* xfer size */
	452	info->txInit, /* initiator */
	453	info->txPri, /* priority */
	454	(MCD_FECTX_DMA \| MCD_TT_FLAGS_DEF), /* Flags */
	455	(MCD_NO_CSUM \| MCD_NO_BYTE_SWAP) /* Function description */
	456	);
	457
	458	/* Now enable the transmit and receive processing */
	459	fecp->ecr \|= FEC_ECR_ETHER_EN;
	460
	461	return 1;
	462	}
	463
	464	static void fec_halt(struct eth_device *dev)
	465	{
	466	struct fec_info_dma *info = dev->priv;
	467	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	468	int counter = 0xffff;
	469
	470	/* issue graceful stop command to the FEC transmitter if necessary */
	471	fecp->tcr \|= FEC_TCR_GTS;
	472
	473	/* wait for graceful stop to register */
	474	while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
	475
	476	/* Disable DMA tasks */
	477	MCD_killDma(info->txTask);
51855e89	478	MCD_killDma(info->rxTask);
777d1abd TL	479
	480	/* Disable the Ethernet Controller */
	481	fecp->ecr &= ~FEC_ECR_ETHER_EN;
	482
	483	/* Clear FIFO status registers */
	484	fecp->rfsr &= FIFO_ERRSTAT;
	485	fecp->tfsr &= FIFO_ERRSTAT;
	486
	487	fecp->frst = 0x01000000;
	488
	489	/* Issue a reset command to the FEC chip */
	490	fecp->ecr \|= FEC_ECR_RESET;
	491
	492	/* wait at least 20 clock cycles */
	493	udelay(10000);
	494
	495	#ifdef ET_DEBUG
	496	printf("Ethernet task stopped\n");
	497	#endif
	498	}
	499
	500	int mcdmafec_initialize(bd_t * bis)
	501	{
	502	struct eth_device *dev;
	503	int i;
6d0f6bcf JCPV	504	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
6d0f6bcf JCPV	505	u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
f32f7fe7	506	#endif
777d1abd	507
a62cd29c	508	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
777d1abd TL	509
777d1abd TL	510	dev =
6d0f6bcf	511	(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
777d1abd TL	512	sizeof *dev);
	513	if (dev == NULL)
	514	hang();
	515
	516	memset(dev, 0, sizeof(*dev));
	517
	518	sprintf(dev->name, "FEC%d", fec_info[i].index);
	519
	520	dev->priv = &fec_info[i];
	521	dev->init = fec_init;
	522	dev->halt = fec_halt;
	523	dev->send = fec_send;
	524	dev->recv = fec_recv;
	525
	526	/* setup Receive and Transmit buffer descriptor */
6d0f6bcf	527	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
429be27c TL	528	fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
429be27c TL	529	tmp = (u32)fec_info[i].rxbd;
f32f7fe7	530	fec_info[i].txbd =
429be27c TL	531	(cbd_t *)((u32)fec_info[i].txbd + tmp +
	532	(PKTBUFSRX * sizeof(cbd_t)));
	533	tmp = (u32)fec_info[i].txbd;
f32f7fe7	534	fec_info[i].txbuf =
429be27c	535	(char *)((u32)fec_info[i].txbuf + tmp +
6d0f6bcf	536	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
429be27c	537	tmp = (u32)fec_info[i].txbuf;
f32f7fe7	538	#else
777d1abd	539	fec_info[i].rxbd =
6d0f6bcf	540	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
777d1abd TL	541	(PKTBUFSRX * sizeof(cbd_t)));
777d1abd TL	542	fec_info[i].txbd =
6d0f6bcf JCPV	543	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
6d0f6bcf JCPV	544	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
777d1abd	545	fec_info[i].txbuf =
6d0f6bcf	546	(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
f32f7fe7	547	#endif
777d1abd TL	548
	549	#ifdef ET_DEBUG
	550	printf("rxbd %x txbd %x\n",
	551	(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
	552	#endif
	553
6d0f6bcf	554	fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
777d1abd TL	555
	556	eth_register(dev);
	557
	558	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	559	int retval;
	560	struct mii_dev *mdiodev = mdio_alloc();
	561	if (!mdiodev)
	562	return -ENOMEM;
	563	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	564	mdiodev->read = mcffec_miiphy_read;
	565	mdiodev->write = mcffec_miiphy_write;
	566
	567	retval = mdio_register(mdiodev);
	568	if (retval < 0)
	569	return retval;
777d1abd TL	570	#endif
	571
	572	if (i > 0)
	573	fec_info[i - 1].next = &fec_info[i];
	574	}
	575	fec_info[i - 1].next = &fec_info[0];
	576
	577	/* default speed */
	578	bis->bi_ethspeed = 10;
	579
b31da88b	580	return 0;
777d1abd	581	}