projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a9068479 HZ |
1 | /* |
| 2 | * Keystone2: DDR3 initialization | |
| 3 | * | |
| d9a76e77 | 4 | * (C) Copyright 2014-2015 |
| a9068479 HZ |
5 | * Texas Instruments Incorporated, <www.ti.com> |
| 6 | * | |
| 7 | * SPDX-License-Identifier: GPL-2.0+ | |
| 8 | */ | |
| 9 | ||
| 10 | #include <common.h> | |
| 11 | #include "ddr3_cfg.h" | |
| 12 | #include <asm/arch/ddr3.h> | |
| 13 | ||
| a9068479 | 14 | static struct pll_init_data ddr3_400 = DDR3_PLL_400; |
| d9a76e77 | 15 | static struct pll_init_data ddr3_333 = DDR3_PLL_333; |
| a9068479 | 16 | |
| 66c98a0c | 17 | u32 ddr3_init(void) |
| a9068479 | 18 | { |
| d9a76e77 | 19 | struct ddr3_spd_cb spd_cb; |
| a9068479 | 20 | |
| d9a76e77 VA |
21 | if (ddr3_get_dimm_params_from_spd(&spd_cb)) { |
| 22 | printf("Sorry, I don't know how to configure DDR3A.\n" | |
| 23 | "Bye :(\n"); | |
| 24 | for (;;) | |
| 25 | ; | |
| 26 | } | |
| a9068479 | 27 | |
| d9a76e77 | 28 | printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); |
| a9068479 | 29 | |
| d9a76e77 VA |
30 | printf("DDR3 speed %d\n", spd_cb.ddrspdclock); |
| 31 | if (spd_cb.ddrspdclock == 1600) | |
| 32 | init_pll(&ddr3_400); | |
| 33 | else | |
| 34 | init_pll(&ddr3_333); | |
| a9068479 HZ |
35 | |
| 36 | /* Reset DDR3 PHY after PLL enabled */ | |
| 37 | ddr3_reset_ddrphy(); | |
| 38 | ||
| d9a76e77 VA |
39 | spd_cb.phy_cfg.zq0cr1 |= 0x10000; |
| 40 | spd_cb.phy_cfg.zq1cr1 |= 0x10000; | |
| 41 | spd_cb.phy_cfg.zq2cr1 |= 0x10000; | |
| 42 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); | |
| 43 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); | |
| 44 | ||
| 45 | printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte); | |
| a9068479 | 46 | |
| d9a76e77 | 47 | return (u32)spd_cb.ddr_size_gbyte; |
| a9068479 | 48 | } |