[u-boot.git] / common / cmd_pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <[email protected]>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Wolfgang Grandegger, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * PCI routines
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

/*
 * Follows routines for the output of infos about devices on PCI bus.
 */

void pci_header_show(pci_dev_t dev);
void pci_header_show_brief(pci_dev_t dev);

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *				Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
 *				the output will be more or less exhaustive.
 *
 * Inputs:	bus_no		the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(int BusNum, int ShortPCIListing)
{
	int Device;
	int Function;
	unsigned char HeaderType;
	unsigned short VendorID;
	pci_dev_t dev;

	printf("Scanning PCI devices on bus %d\n", BusNum);

	if (ShortPCIListing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}

	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
		HeaderType = 0;
		VendorID = 0;
		for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
			/*
			 * If this is not a multi-function device, we skip the rest.
			 */
			if (Function && !(HeaderType & 0x80))
				break;

			dev = PCI_BDF(BusNum, Device, Function);

			pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
			if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
				continue;

			if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

			if (ShortPCIListing)
			{
				printf("%02x.%02x.%02x   ", BusNum, Device, Function);
				pci_header_show_brief(dev);
			}
			else
			{
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       BusNum, Device, Function);
				pci_header_show(dev);
			}
	    }
    }
}


/*
 * Subroutine:  pci_header_show_brief
 *
 * Description: Reads and prints the header of the
 *		specified PCI device in short form.
 *
 * Inputs:	dev      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show_brief(pci_dev_t dev)
{
	u16 vendor, device;
	u8 class, subclass;

	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);

	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
	       vendor, device,
	       pci_class_str(class), subclass);
}

/*
 * Subroutine:  PCI_Header_Show
 *
 * Description: Reads the header of the specified PCI device.
 *
 * Inputs:		BusDevFunc      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show(pci_dev_t dev)
{
	u8 _byte, header_type;
	u16 _word;
	u32 _dword;

#define PRINT(msg, type, reg) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type)

#define PRINT2(msg, type, reg, func) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type, func(_##type))

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	PRINT ("  vendor ID =                   0x%.4x\n", word, PCI_VENDOR_ID);
	PRINT ("  device ID =                   0x%.4x\n", word, PCI_DEVICE_ID);
	PRINT ("  command register =            0x%.4x\n", word, PCI_COMMAND);
	PRINT ("  status register =             0x%.4x\n", word, PCI_STATUS);
	PRINT ("  revision ID =                 0x%.2x\n", byte, PCI_REVISION_ID);
	PRINT2("  class code =                  0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
								pci_class_str);
	PRINT ("  sub class code =              0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	PRINT ("  programming interface =       0x%.2x\n", byte, PCI_CLASS_PROG);
	PRINT ("  cache line =                  0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	PRINT ("  latency time =                0x%.2x\n", byte, PCI_LATENCY_TIMER);
	PRINT ("  header type =                 0x%.2x\n", byte, PCI_HEADER_TYPE);
	PRINT ("  BIST =                        0x%.2x\n", byte, PCI_BIST);
	PRINT ("  base address 0 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_0);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  base address 2 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		PRINT ("  base address 3 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		PRINT ("  base address 4 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		PRINT ("  base address 5 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		PRINT ("  cardBus CIS pointer =         0x%.8x\n", dword, PCI_CARDBUS_CIS);
		PRINT ("  sub system vendor ID =        0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		PRINT ("  sub system ID =               0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  min Grant =                   0x%.2x\n", byte, PCI_MIN_GNT);
		PRINT ("  max Latency =                 0x%.2x\n", byte, PCI_MAX_LAT);
		break;

	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */

		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_PRIMARY_BUS);
		PRINT ("  secondary bus number =        0x%.2x\n", byte, PCI_SECONDARY_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
		PRINT ("  secondary latency timer =     0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
		PRINT ("  IO base =                     0x%.2x\n", byte, PCI_IO_BASE);
		PRINT ("  IO limit =                    0x%.2x\n", byte, PCI_IO_LIMIT);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_SEC_STATUS);
		PRINT ("  memory base =                 0x%.4x\n", word, PCI_MEMORY_BASE);
		PRINT ("  memory limit =                0x%.4x\n", word, PCI_MEMORY_LIMIT);
		PRINT ("  prefetch memory base =        0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
		PRINT ("  prefetch memory limit =       0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
		PRINT ("  prefetch memory base upper =  0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
		PRINT ("  prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
		PRINT ("  IO base upper 16 bits =       0x%.4x\n", word, PCI_IO_BASE_UPPER16);
		PRINT ("  IO limit upper 16 bits =      0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS1);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_BRIDGE_CONTROL);
		break;

	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */

		PRINT ("  capabilities =                0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_CB_SEC_STATUS);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
		PRINT ("  CardBus number =              0x%.2x\n", byte, PCI_CB_CARD_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
		PRINT ("  CardBus latency timer =       0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
		PRINT ("  CardBus memory base 0 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
		PRINT ("  CardBus memory limit 0 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
		PRINT ("  CardBus memory base 1 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		PRINT ("  CardBus memory limit 1 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		PRINT ("  CardBus IO base 0 =           0x%.4x\n", word, PCI_CB_IO_BASE_0);
		PRINT ("  CardBus IO base high 0 =      0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		PRINT ("  CardBus IO limit 0 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		PRINT ("  CardBus IO limit high 0 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		PRINT ("  CardBus IO base 1 =           0x%.4x\n", word, PCI_CB_IO_BASE_1);
		PRINT ("  CardBus IO base high 1 =      0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		PRINT ("  CardBus IO limit 1 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		PRINT ("  CardBus IO limit high 1 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		PRINT ("  subvendor ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		PRINT ("  subdevice ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		PRINT ("  PC Card 16bit base address =  0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		break;

	default:
		printf("unknown header\n");
		break;
    }

#undef PRINT
#undef PRINT2
}

/* Convert the "bus.device.function" identifier into a number.
 */
static pci_dev_t get_pci_dev(char* name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = simple_strtoul(cnum, NULL, 16);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int rc = 0;

	if (length == 0)
		length = 0x40 / size; /* Standard PCI configuration space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * size;
	do {
		uint	val4;
		ushort  val2;
		u_char	val1;

		printf("%08lx:", addr);
		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
		for (i=0; i<linebytes; i+= size) {
			if (size == 4) {
				pci_read_config_dword(bdf, addr, &val4);
				printf(" %08x", val4);
			} else if (size == 2) {
				pci_read_config_word(bdf, addr, &val2);
				printf(" %04x", val2);
			} else {
				pci_read_config_byte(bdf, addr, &val1);
				printf(" %02x", val1);
			}
			addr += size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
	if (size == 4) {
		pci_write_config_dword(bdf, addr, value);
	}
	else if (size == 2) {
		ushort val = value & 0xffff;
		pci_write_config_word(bdf, addr, val);
	}
	else {
		u_char val = value & 0xff;
		pci_write_config_byte(bdf, addr, val);
	}
	return 0;
}

static int
pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	uint	val4;
	ushort  val2;
	u_char	val1;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		if (size == 4) {
			pci_read_config_dword(bdf, addr, &val4);
			printf(" %08x", val4);
		}
		else if (size == 2) {
			pci_read_config_word(bdf, addr, &val2);
			printf(" %04x", val2);
		}
		else {
			pci_read_config_byte(bdf, addr, &val1);
			printf(" %02x", val1);
		}

		nbytes = readline (" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
#ifdef CONFIG_BOOT_RETRY_TIME
			reset_cmd_timeout(); /* good enough to not time out */
#endif
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = simple_strtoul(console_buffer, &endp, 16);
			nbytes = endp - console_buffer;
			if (nbytes) {
#ifdef CONFIG_BOOT_RETRY_TIME
				/* good enough to not time out
				 */
				reset_cmd_timeout();
#endif
				pci_cfg_write (bdf, addr, size, i);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong addr = 0, value = 0, size = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		size = cmd_get_data_size(argv[1], 4);
		if (argc > 3)
			addr = simple_strtoul(argv[3], NULL, 16);
		if (argc > 4)
			value = simple_strtoul(argv[4], NULL, 16);
	case 'h':		/* header */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		break;
#endif
	default:		/* scan bus */
		value = 1; /* short listing */
		bdf = 0;   /* bus number  */
		if (argc > 1) {
			if (argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				bdf = simple_strtoul(argv[1], NULL, 16);
		}
		pciinfo(bdf, value);
		return 0;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(bdf);
		return 0;
	case 'd':		/* display */
		return pci_cfg_display(bdf, addr, size, value);
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		pci_init();
		return 0;
#endif
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 0);
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 1);
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		return pci_cfg_write(bdf, addr, size, value);
	}

	return 1;
 usage:
	return CMD_RET_USAGE;
}

/***************************************************/

#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
#ifdef CONFIG_CMD_PCI_ENUM
	"pci enum\n"
	"    - re-enumerate PCI buses\n"
#endif
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address";
#endif

U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"list and access PCI Configuration Space", pci_help_text
);
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <[email protected]>
	4	*
	5	* (C) Copyright 2002
	6	* Wolfgang Denk, DENX Software Engineering, [email protected].
	7	* Wolfgang Grandegger, DENX Software Engineering, [email protected].
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	10	*/
	11
	12	/*
	13	* PCI routines
	14	*/
	15
	16	#include <common.h>
c609719b	17	#include <command.h>
c609719b WD	18	#include <asm/processor.h>
c609719b WD	19	#include <asm/io.h>
c609719b WD	20	#include <pci.h>
c609719b WD	21
c609719b WD	22	/*
	23	* Follows routines for the output of infos about devices on PCI bus.
	24	*/
	25
	26	void pci_header_show(pci_dev_t dev);
	27	void pci_header_show_brief(pci_dev_t dev);
	28
	29	/*
	30	* Subroutine: pciinfo
	31	*
	32	* Description: Show information about devices on PCI bus.
6d0f6bcf	33	* Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
c609719b WD	34	* the output will be more or less exhaustive.
	35	*
	36	* Inputs: bus_no the number of the bus to be scanned.
	37	*
	38	* Return: None
	39	*
	40	*/
	41	void pciinfo(int BusNum, int ShortPCIListing)
	42	{
	43	int Device;
	44	int Function;
	45	unsigned char HeaderType;
	46	unsigned short VendorID;
	47	pci_dev_t dev;
	48
	49	printf("Scanning PCI devices on bus %d\n", BusNum);
	50
	51	if (ShortPCIListing) {
	52	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	53	printf("_____________________________________________________________\n");
	54	}
	55
	56	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
	57	HeaderType = 0;
	58	VendorID = 0;
	59	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
	60	/*
	61	* If this is not a multi-function device, we skip the rest.
	62	*/
	63	if (Function && !(HeaderType & 0x80))
	64	break;
	65
	66	dev = PCI_BDF(BusNum, Device, Function);
	67
	68	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
	69	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
	70	continue;
	71
c7de829c	72	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
c609719b WD	73
	74	if (ShortPCIListing)
	75	{
	76	printf("%02x.%02x.%02x ", BusNum, Device, Function);
	77	pci_header_show_brief(dev);
	78	}
	79	else
	80	{
	81	printf("\nFound PCI device %02x.%02x.%02x:\n",
	82	BusNum, Device, Function);
	83	pci_header_show(dev);
	84	}
	85	}
	86	}
	87	}
	88
c609719b WD	89
	90	/*
	91	* Subroutine: pci_header_show_brief
	92	*
	93	* Description: Reads and prints the header of the
53677ef1	94	* specified PCI device in short form.
c609719b WD	95	*
	96	* Inputs: dev Bus+Device+Function number
	97	*
	98	* Return: None
	99	*
	100	*/
	101	void pci_header_show_brief(pci_dev_t dev)
	102	{
	103	u16 vendor, device;
	104	u8 class, subclass;
	105
	106	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	107	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	108	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	109	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
	110
5d232d0e	111	printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
c609719b	112	vendor, device,
983eb9d1	113	pci_class_str(class), subclass);
c609719b WD	114	}
	115
	116	/*
	117	* Subroutine: PCI_Header_Show
	118	*
	119	* Description: Reads the header of the specified PCI device.
	120	*
	121	* Inputs: BusDevFunc Bus+Device+Function number
	122	*
	123	* Return: None
	124	*
	125	*/
	126	void pci_header_show(pci_dev_t dev)
	127	{
	128	u8 _byte, header_type;
	129	u16 _word;
	130	u32 _dword;
	131
	132	#define PRINT(msg, type, reg) \
	133	pci_read_config_##type(dev, reg, &_##type); \
	134	printf(msg, _##type)
	135
	136	#define PRINT2(msg, type, reg, func) \
	137	pci_read_config_##type(dev, reg, &_##type); \
	138	printf(msg, _##type, func(_##type))
	139
	140	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	141
	142	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
	143	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
	144	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
	145	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
	146	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
	147	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
983eb9d1	148	pci_class_str);
c609719b WD	149	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	150	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
	151	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	152	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
	153	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
	154	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
	155	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
c609719b	156
7c7a23bd WD	157	switch (header_type & 0x03) {
	158	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
	159	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
	160	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
	161	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
	162	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
	163	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
	164	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
	165	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
	166	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
	167	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
	168	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	169	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	170	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
	171	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
	172	break;
8bde7f77	173
7c7a23bd WD	174	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
	175
	176	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
c609719b WD	177	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
	178	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
	179	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
	180	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
	181	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
	182	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
	183	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
	184	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
	185	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
	186	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
	187	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
	188	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
	189	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
	190	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
	191	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
	192	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
	193	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	194	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	195	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
7c7a23bd WD	196	break;
	197
	198	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
	199
	200	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
	201	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
	202	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
	203	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
	204	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
8bde7f77	205	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
7c7a23bd WD	206	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
	207	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
	208	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
	209	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
	210	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
	211	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
	212	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
	213	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
	214	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
	215	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
	216	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
	217	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
	218	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	219	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	220	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
	221	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
	222	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
	223	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
	224	break;
8bde7f77	225
7c7a23bd WD	226	default:
7c7a23bd WD	227	printf("unknown header\n");
8bde7f77	228	break;
c609719b WD	229	}
	230
	231	#undef PRINT
	232	#undef PRINT2
	233	}
	234
	235	/* Convert the "bus.device.function" identifier into a number.
	236	*/
	237	static pci_dev_t get_pci_dev(char* name)
	238	{
	239	char cnum[12];
	240	int len, i, iold, n;
	241	int bdfs[3] = {0,0,0};
	242
	243	len = strlen(name);
	244	if (len > 8)
	245	return -1;
	246	for (i = 0, iold = 0, n = 0; i < len; i++) {
	247	if (name[i] == '.') {
	248	memcpy(cnum, &name[iold], i - iold);
	249	cnum[i - iold] = '\0';
	250	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
	251	iold = i + 1;
	252	}
	253	}
	254	strcpy(cnum, &name[iold]);
	255	if (n == 0)
	256	n = 1;
	257	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	258	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	259	}
	260
	261	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
	262	{
	263	#define DISP_LINE_LEN 16
	264	ulong i, nbytes, linebytes;
	265	int rc = 0;
	266
	267	if (length == 0)
	268	length = 0x40 / size; /* Standard PCI configuration space */
	269
	270	/* Print the lines.
	271	* once, and all accesses are with the specified bus width.
	272	*/
	273	nbytes = length * size;
	274	do {
	275	uint val4;
	276	ushort val2;
	277	u_char val1;
	278
	279	printf("%08lx:", addr);
	280	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
	281	for (i=0; i<linebytes; i+= size) {
	282	if (size == 4) {
	283	pci_read_config_dword(bdf, addr, &val4);
	284	printf(" %08x", val4);
	285	} else if (size == 2) {
	286	pci_read_config_word(bdf, addr, &val2);
	287	printf(" %04x", val2);
	288	} else {
	289	pci_read_config_byte(bdf, addr, &val1);
	290	printf(" %02x", val1);
	291	}
	292	addr += size;
293	}
294	printf("\n");
295	nbytes -= linebytes;
296	if (ctrlc()) {
297	rc = 1;
298	break;
299	}
300	} while (nbytes > 0);
301
302	return (rc);
303	}
304
305	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
306	{
307	if (size == 4) {
308	pci_write_config_dword(bdf, addr, value);
309	}
310	else if (size == 2) {
311	ushort val = value & 0xffff;
312	pci_write_config_word(bdf, addr, val);
313	}
314	else {
315	u_char val = value & 0xff;
316	pci_write_config_byte(bdf, addr, val);
317	}
318	return 0;
319	}
320
321	static int
322	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
323	{
324	ulong i;
325	int nbytes;
c609719b WD	326	uint val4;
	327	ushort val2;
	328	u_char val1;
	329
	330	/* Print the address, followed by value. Then accept input for
	331	* the next value. A non-converted value exits.
	332	*/
	333	do {
	334	printf("%08lx:", addr);
	335	if (size == 4) {
	336	pci_read_config_dword(bdf, addr, &val4);
	337	printf(" %08x", val4);
	338	}
	339	else if (size == 2) {
	340	pci_read_config_word(bdf, addr, &val2);
	341	printf(" %04x", val2);
	342	}
	343	else {
	344	pci_read_config_byte(bdf, addr, &val1);
	345	printf(" %02x", val1);
	346	}
	347
	348	nbytes = readline (" ? ");
	349	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
	350	/* <CR> pressed as only input, don't modify current
	351	* location and move to next. "-" pressed will go back.
	352	*/
	353	if (incrflag)
	354	addr += nbytes ? -size : size;
	355	nbytes = 1;
	356	#ifdef CONFIG_BOOT_RETRY_TIME
	357	reset_cmd_timeout(); /* good enough to not time out */
	358	#endif
	359	}
	360	#ifdef CONFIG_BOOT_RETRY_TIME
	361	else if (nbytes == -2) {
	362	break; /* timed out, exit the command */
	363	}
	364	#endif
	365	else {
	366	char *endp;
	367	i = simple_strtoul(console_buffer, &endp, 16);
	368	nbytes = endp - console_buffer;
	369	if (nbytes) {
	370	#ifdef CONFIG_BOOT_RETRY_TIME
	371	/* good enough to not time out
	372	*/
	373	reset_cmd_timeout();
	374	#endif
	375	pci_cfg_write (bdf, addr, size, i);
	376	if (incrflag)
	377	addr += size;
	378	}
	379	}
	380	} while (nbytes);
	381
	382	return 0;
	383	}
	384
	385	/* PCI Configuration Space access commands
	386	*
	387	* Syntax:
	388	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
	389	* pci next[.b, .w, .l] bus.device.function [addr]
390	* pci modify[.b, .w, .l] bus.device.function [addr]
391	* pci write[.b, .w, .l] bus.device.function addr value
392	*/
088f1b19	393	static int do_pci(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
c609719b WD	394	{
	395	ulong addr = 0, value = 0, size = 0;
	396	pci_dev_t bdf = 0;
	397	char cmd = 's';
	398
	399	if (argc > 1)
	400	cmd = argv[1][0];
	401
	402	switch (cmd) {
	403	case 'd': /* display */
	404	case 'n': /* next */
	405	case 'm': /* modify */
	406	case 'w': /* write */
	407	/* Check for a size specification. */
	408	size = cmd_get_data_size(argv[1], 4);
	409	if (argc > 3)
	410	addr = simple_strtoul(argv[3], NULL, 16);
	411	if (argc > 4)
	412	value = simple_strtoul(argv[4], NULL, 16);
	413	case 'h': /* header */
	414	if (argc < 3)
	415	goto usage;
	416	if ((bdf = get_pci_dev(argv[2])) == -1)
	417	return 1;
	418	break;
96d61603 JS	419	#ifdef CONFIG_CMD_PCI_ENUM
	420	case 'e':
	421	break;
	422	#endif
c609719b WD	423	default: /* scan bus */
	424	value = 1; /* short listing */
	425	bdf = 0; /* bus number */
	426	if (argc > 1) {
	427	if (argv[argc-1][0] == 'l') {
	428	value = 0;
	429	argc--;
	430	}
	431	if (argc > 1)
	432	bdf = simple_strtoul(argv[1], NULL, 16);
	433	}
	434	pciinfo(bdf, value);
	435	return 0;
	436	}
	437
	438	switch (argv[1][0]) {
	439	case 'h': /* header */
	440	pci_header_show(bdf);
	441	return 0;
	442	case 'd': /* display */
	443	return pci_cfg_display(bdf, addr, size, value);
96d61603 JS	444	#ifdef CONFIG_CMD_PCI_ENUM
	445	case 'e':
	446	pci_init();
	447	return 0;
	448	#endif
c609719b WD	449	case 'n': /* next */
	450	if (argc < 4)
	451	goto usage;
	452	return pci_cfg_modify(bdf, addr, size, value, 0);
	453	case 'm': /* modify */
	454	if (argc < 4)
	455	goto usage;
	456	return pci_cfg_modify(bdf, addr, size, value, 1);
	457	case 'w': /* write */
	458	if (argc < 5)
	459	goto usage;
	460	return pci_cfg_write(bdf, addr, size, value);
	461	}
	462
	463	return 1;
	464	usage:
4c12eeb8	465	return CMD_RET_USAGE;
c609719b WD	466	}
c609719b WD	467
8bde7f77 WD	468	/***************************************************/
8bde7f77 WD	469
088f1b19 KP	470	#ifdef CONFIG_SYS_LONGHELP
088f1b19 KP	471	static char pci_help_text[] =
8bde7f77 WD	472	"[bus] [long]\n"
8bde7f77 WD	473	" - short or long list of PCI devices on bus 'bus'\n"
96d61603 JS	474	#ifdef CONFIG_CMD_PCI_ENUM
	475	"pci enum\n"
	476	" - re-enumerate PCI buses\n"
	477	#endif
8bde7f77 WD	478	"pci header b.d.f\n"
	479	" - show header of PCI device 'bus.device.function'\n"
	480	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	481	" - display PCI configuration space (CFG)\n"
	482	"pci next[.b, .w, .l] b.d.f address\n"
	483	" - modify, read and keep CFG address\n"
	484	"pci modify[.b, .w, .l] b.d.f address\n"
	485	" - modify, auto increment CFG address\n"
	486	"pci write[.b, .w, .l] b.d.f address value\n"
088f1b19 KP	487	" - write to CFG address";
	488	#endif
	489
	490	U_BOOT_CMD(
	491	pci, 5, 1, do_pci,
	492	"list and access PCI Configuration Space", pci_help_text
8bde7f77	493	);