[u-boot.git] / include / phy.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <dm.h>
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#include <phy_interface.h>

#define PHY_FIXED_ID		0xa5a55a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);

	/* Phy specific driver override for reading a MMD register */
	int (*read_mmd)(struct phy_device *phydev, int devad, int reg);

	/* Phy specific driver override for writing a MMD register */
	int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
			 u16 val);

	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
	ofnode node;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	bool is_c45;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
					  int regnum)
{
	/* Write the desired MMD Devad */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);

	/* Write the desired MMD register address */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);

	/* Select the Function : DATA with no post increment */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
		  (devad | MII_MMD_CTRL_NOINCR));
}

static inline int phy_read_mmd(struct phy_device *phydev, int devad,
			       int regnum)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->read_mmd)
		return drv->read_mmd(phydev, devad, regnum);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_read(phydev, devad, regnum);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Read the content of the MMD's selected register */
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}

static inline int phy_write_mmd(struct phy_device *phydev, int devad,
				int regnum, u16 val)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->write_mmd)
		return drv->write_mmd(phydev, devad, regnum, val);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_write(phydev, devad, regnum, val);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Write the data into MMD's selected register */
	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	if (ofnode_valid(phydev->node))
		return phydev->node;
	else
		return dev_ofnode(phydev->dev);
}
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	return ofnode_null();
}
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  	0x13e51002
#define PHY_UID_CS4223  	0x03e57003
#define PHY_UID_TN2020		0x00a19410
#define PHY_UID_IN112525_S03	0x02107440

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5f184715 AF	2	/*
5f184715 AF	3	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
5f184715	5	*
5f184715 AF	6	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	7	*/
	8
	9	#ifndef _PHY_H
	10	#define _PHY_H
	11
eef0b8a9	12	#include <dm.h>
5f184715 AF	13	#include <linux/list.h>
	14	#include <linux/mii.h>
	15	#include <linux/ethtool.h>
	16	#include <linux/mdio.h>
f070b1a2	17	#include <phy_interface.h>
5f184715	18
db40c1aa HS	19	#define PHY_FIXED_ID 0xa5a55a5a
db40c1aa HS	20
5f184715 AF	21	#define PHY_MAX_ADDR 32
5f184715 AF	22
ddcd1f30 SX	23	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	24
4dae610b	25	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	26	SUPPORTED_TP \| \
	27	SUPPORTED_MII)
	28
4dae610b FF	29	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	30	SUPPORTED_10baseT_Full)
	31
	32	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	33	SUPPORTED_100baseT_Full)
	34
	35	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	36	SUPPORTED_1000baseT_Full)
5f184715 AF	37
4dae610b FF	38	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	39	PHY_100BT_FEATURES \| \
	40	PHY_DEFAULT_FEATURES)
	41
	42	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	43	PHY_1000BT_FEATURES)
	44
5f184715 AF	45	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	46	SUPPORTED_10000baseT_Full)
	47
4fb3f0c8	48	#ifndef PHY_ANEG_TIMEOUT
5f184715	49	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	50	#endif
5f184715 AF	51
5f184715 AF	52
5f184715 AF	53	struct phy_device;
	54
	55	#define MDIO_NAME_LEN 32
	56
	57	struct mii_dev {
	58	struct list_head link;
	59	char name[MDIO_NAME_LEN];
	60	void *priv;
	61	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	62	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	63	u16 val);
	64	int (reset)(struct mii_dev bus);
	65	struct phy_device *phymap[PHY_MAX_ADDR];
	66	u32 phy_mask;
	67	};
	68
	69	/* struct phy_driver: a structure which defines PHY behavior
	70	*
	71	* uid will contain a number which represents the PHY. During
	72	* startup, the driver will poll the PHY to find out what its
	73	* UID--as defined by registers 2 and 3--is. The 32-bit result
	74	* gotten from the PHY will be masked to
	75	* discard any bits which may change based on revision numbers
	76	* unimportant to functionality
	77	*
	78	*/
	79	struct phy_driver {
	80	char *name;
	81	unsigned int uid;
	82	unsigned int mask;
	83	unsigned int mmds;
	84
	85	u32 features;
	86
	87	/* Called to do any driver startup necessities */
	88	/* Will be called during phy_connect */
	89	int (probe)(struct phy_device phydev);
	90
	91	/* Called to configure the PHY, and modify the controller
	92	* based on the results. Should be called after phy_connect */
	93	int (config)(struct phy_device phydev);
	94
	95	/* Called when starting up the controller */
	96	int (startup)(struct phy_device phydev);
	97
	98	/* Called when bringing down the controller */
	99	int (shutdown)(struct phy_device phydev);
	100
b71841b9 SB	101	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	102	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	103	u16 val);
4f6746dc CC	104
	105	/* Phy specific driver override for reading a MMD register */
	106	int (read_mmd)(struct phy_device phydev, int devad, int reg);
	107
	108	/* Phy specific driver override for writing a MMD register */
	109	int (write_mmd)(struct phy_device phydev, int devad, int reg,
	110	u16 val);
	111
5f184715 AF	112	struct list_head list;
	113	};
	114
	115	struct phy_device {
	116	/* Information about the PHY type */
	117	/* And management functions */
	118	struct mii_dev *bus;
	119	struct phy_driver *drv;
	120	void *priv;
	121
c74c8e66 SG	122	#ifdef CONFIG_DM_ETH
c74c8e66 SG	123	struct udevice *dev;
eef0b8a9	124	ofnode node;
c74c8e66	125	#else
5f184715	126	struct eth_device *dev;
c74c8e66	127	#endif
5f184715 AF	128
	129	/* forced speed & duplex (no autoneg)
	130	* partner speed & duplex & pause (autoneg)
	131	*/
	132	int speed;
	133	int duplex;
	134
	135	/* The most recently read link state */
	136	int link;
	137	int port;
	138	phy_interface_t interface;
	139
	140	u32 advertising;
	141	u32 supported;
	142	u32 mmds;
	143
	144	int autoneg;
	145	int addr;
	146	int pause;
	147	int asym_pause;
	148	u32 phy_id;
b3eabd82	149	bool is_c45;
5f184715 AF	150	u32 flags;
	151	};
	152
f55a776c SX	153	struct fixed_link {
	154	int phy_id;
	155	int duplex;
	156	int link_speed;
	157	int pause;
	158	int asym_pause;
	159	};
	160
5f184715 AF	161	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	162	{
	163	struct mii_dev *bus = phydev->bus;
	164
	165	return bus->read(bus, phydev->addr, devad, regnum);
	166	}
	167
	168	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	169	u16 val)
	170	{
	171	struct mii_dev *bus = phydev->bus;
	172
	173	return bus->write(bus, phydev->addr, devad, regnum, val);
	174	}
	175
4f6746dc CC	176	static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
	177	int regnum)
	178	{
	179	/* Write the desired MMD Devad */
	180	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
	181
	182	/* Write the desired MMD register address */
	183	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
	184
	185	/* Select the Function : DATA with no post increment */
	186	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
	187	(devad \| MII_MMD_CTRL_NOINCR));
	188	}
	189
	190	static inline int phy_read_mmd(struct phy_device *phydev, int devad,
	191	int regnum)
	192	{
	193	struct phy_driver *drv = phydev->drv;
	194
	195	if (regnum > (u16)~0 \|\| devad > 32)
	196	return -EINVAL;
	197
	198	/* driver-specific access */
	199	if (drv->read_mmd)
	200	return drv->read_mmd(phydev, devad, regnum);
	201
	202	/* direct C45 / C22 access */
	203	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	204	devad == MDIO_DEVAD_NONE \|\| !devad)
	205	return phy_read(phydev, devad, regnum);
	206
	207	/* indirect C22 access */
	208	phy_mmd_start_indirect(phydev, devad, regnum);
	209
	210	/* Read the content of the MMD's selected register */
	211	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
	212	}
	213
	214	static inline int phy_write_mmd(struct phy_device *phydev, int devad,
	215	int regnum, u16 val)
	216	{
	217	struct phy_driver *drv = phydev->drv;
	218
	219	if (regnum > (u16)~0 \|\| devad > 32)
	220	return -EINVAL;
	221
	222	/* driver-specific access */
	223	if (drv->write_mmd)
	224	return drv->write_mmd(phydev, devad, regnum, val);
	225
	226	/* direct C45 / C22 access */
	227	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	228	devad == MDIO_DEVAD_NONE \|\| !devad)
	229	return phy_write(phydev, devad, regnum, val);
	230
	231	/* indirect C22 access */
	232	phy_mmd_start_indirect(phydev, devad, regnum);
	233
	234	/* Write the data into MMD's selected register */
	235	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
	236	}
	237
5f184715 AF	238	#ifdef CONFIG_PHYLIB_10G
	239	extern struct phy_driver gen10g_driver;
	240
	241	/* For now, XGMII is the only 10G interface */
	242	static inline int is_10g_interface(phy_interface_t interface)
	243	{
	244	return interface == PHY_INTERFACE_MODE_XGMII;
	245	}
	246
	247	#endif
	248
	249	int phy_init(void);
	250	int phy_reset(struct phy_device *phydev);
1adb406b TK	251	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	252	phy_interface_t interface);
c74c8e66 SG	253	#ifdef CONFIG_DM_ETH
	254	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
	255	struct phy_device phy_connect(struct mii_dev bus, int addr,
	256	struct udevice *dev,
	257	phy_interface_t interface);
eef0b8a9 GS	258	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	259	{
	260	if (ofnode_valid(phydev->node))
	261	return phydev->node;
	262	else
	263	return dev_ofnode(phydev->dev);
	264	}
c74c8e66	265	#else
1adb406b	266	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
5f184715 AF	267	struct phy_device phy_connect(struct mii_dev bus, int addr,
	268	struct eth_device *dev,
	269	phy_interface_t interface);
eef0b8a9 GS	270	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	271	{
	272	return ofnode_null();
	273	}
c74c8e66	274	#endif
5f184715 AF	275	int phy_startup(struct phy_device *phydev);
	276	int phy_config(struct phy_device *phydev);
	277	int phy_shutdown(struct phy_device *phydev);
	278	int phy_register(struct phy_driver *drv);
b18acb0a	279	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	280	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	281	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	282	int genphy_update_link(struct phy_device *phydev);
e2043f5c	283	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	284	int genphy_config(struct phy_device *phydev);
	285	int genphy_startup(struct phy_device *phydev);
	286	int genphy_shutdown(struct phy_device *phydev);
	287	int gen10g_config(struct phy_device *phydev);
	288	int gen10g_startup(struct phy_device *phydev);
	289	int gen10g_shutdown(struct phy_device *phydev);
	290	int gen10g_discover_mmds(struct phy_device *phydev);
	291
137963d7	292	int phy_b53_init(void);
24ae3961	293	int phy_mv88e61xx_init(void);
f7c38cf8	294	int phy_aquantia_init(void);
9082eeac AF	295	int phy_atheros_init(void);
9082eeac AF	296	int phy_broadcom_init(void);
9b18e519	297	int phy_cortina_init(void);
9082eeac	298	int phy_davicom_init(void);
f485c8a3	299	int phy_et1011c_init(void);
9082eeac AF	300	int phy_lxt_init(void);
9082eeac AF	301	int phy_marvell_init(void);
d397f7c4 AG	302	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	303	int phy_micrel_ksz90x1_init(void);
8995a96d	304	int phy_meson_gxl_init(void);
9082eeac AF	305	int phy_natsemi_init(void);
9082eeac AF	306	int phy_realtek_init(void);
b6abf555	307	int phy_smsc_init(void);
9082eeac	308	int phy_teranetics_init(void);
721aed79	309	int phy_ti_init(void);
9082eeac	310	int phy_vitesse_init(void);
ed6fad3e	311	int phy_xilinx_init(void);
a5fd13ad	312	int phy_mscc_init(void);
db40c1aa	313	int phy_fixed_init(void);
a836626c	314
2fb63964	315	int board_phy_config(struct phy_device *phydev);
5707d5ff	316	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	317
c74c8e66 SG	318	/**
	319	* phy_get_interface_by_name() - Look up a PHY interface name
	320	*
	321	* @str: PHY interface name, e.g. "mii"
	322	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	323	*/
	324	int phy_get_interface_by_name(const char *str);
	325
3ab72fe8 DM	326	/**
	327	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	328	* is RGMII (all variants)
	329	* @phydev: the phy_device struct
	330	*/
	331	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	332	{
	333	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	334	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	335	}
	336
3c221af3 DM	337	/**
	338	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	339	* is SGMII (all variants)
	340	* @phydev: the phy_device struct
	341	*/
	342	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	343	{
	344	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	345	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	346	}
	347
a836626c	348	/* PHY UIDs for various PHYs that are referenced in external code */
1ddcf5ed PJ	349	#define PHY_UID_CS4340 0x13e51002
	350	#define PHY_UID_CS4223 0x03e57003
	351	#define PHY_UID_TN2020 0x00a19410
	352	#define PHY_UID_IN112525_S03 0x02107440
a836626c	353
5f184715	354	#endif