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b765ffb7 SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, [email protected]. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
c25dd8fc | 22 | #include <command.h> |
b765ffb7 | 23 | #include <ppc440.h> |
04e6c38b | 24 | #include <asm/processor.h> |
b765ffb7 | 25 | #include <asm/gpio.h> |
04e6c38b | 26 | #include <asm/io.h> |
b765ffb7 SR |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
6d0f6bcf | 30 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
b765ffb7 | 31 | |
3ad63878 SR |
32 | ulong flash_get_size(ulong base, int banknum); |
33 | int misc_init_r_kbd(void); | |
b765ffb7 SR |
34 | |
35 | int board_early_init_f(void) | |
36 | { | |
37 | u32 sdr0_pfc1, sdr0_pfc2; | |
38 | u32 reg; | |
39 | ||
83b4cfa3 WD |
40 | /* PLB Write pipelining disabled. Denali Core workaround */ |
41 | mtdcr(plb0_acr, 0xDE000000); | |
42 | mtdcr(plb1_acr, 0xDE000000); | |
b765ffb7 SR |
43 | |
44 | /*-------------------------------------------------------------------- | |
45 | * Setup the interrupt controller polarities, triggers, etc. | |
46 | *-------------------------------------------------------------------*/ | |
47 | mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ | |
48 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
49 | mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ | |
aedf5bde SR |
50 | mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ |
51 | mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ | |
b765ffb7 SR |
52 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
53 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
54 | ||
55 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
56 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
57 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
aedf5bde SR |
58 | mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ |
59 | mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ | |
b765ffb7 SR |
60 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
61 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
62 | ||
63 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
64 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
65 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
66 | mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ | |
aedf5bde | 67 | mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ |
b765ffb7 | 68 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
aedf5bde | 69 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
b765ffb7 SR |
70 | |
71 | /* Trace Pins are disabled. SDR0_PFC0 Register */ | |
72 | mtsdr(SDR0_PFC0, 0x0); | |
73 | ||
74 | /* select Ethernet pins */ | |
75 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
76 | /* SMII via ZMII */ | |
77 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
78 | SDR0_PFC1_SELECT_CONFIG_6; | |
79 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
80 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
81 | SDR0_PFC2_SELECT_CONFIG_6; | |
82 | ||
83 | /* enable SPI (SCP) */ | |
84 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; | |
85 | ||
86 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
87 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
88 | ||
89 | mtsdr(SDR0_PFC4, 0x80000000); | |
90 | ||
91 | /* PCI arbiter disabled */ | |
83b4cfa3 | 92 | /* PCI Host Configuration disbaled */ |
b765ffb7 | 93 | mfsdr(sdr_pci0, reg); |
83b4cfa3 | 94 | reg = 0; |
b765ffb7 SR |
95 | mtsdr(sdr_pci0, 0x00000000 | reg); |
96 | ||
6d0f6bcf | 97 | gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); |
b765ffb7 | 98 | |
6d0f6bcf JCPV |
99 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 |
100 | gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); | |
65b20dce YT |
101 | |
102 | reg = 0; /* reuse as counter */ | |
6d0f6bcf JCPV |
103 | out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, |
104 | in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | |
105 | & ~CONFIG_SYS_DSPIC_TEST_MASK); | |
106 | while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { | |
65b20dce YT |
107 | udelay(1000); |
108 | } | |
6d0f6bcf JCPV |
109 | gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); |
110 | if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { | |
65b20dce | 111 | /* set "boot error" flag */ |
6d0f6bcf JCPV |
112 | out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, |
113 | in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | | |
114 | CONFIG_SYS_DSPIC_TEST_MASK); | |
65b20dce YT |
115 | } |
116 | #endif | |
117 | ||
54fd6c93 SR |
118 | /* |
119 | * Reset PHY's: | |
120 | * The PHY's need a 2nd reset pulse, since the MDIO address is latched | |
121 | * upon reset, and with the first reset upon powerup, the addresses are | |
122 | * not latched reliable, since the IRQ line is multiplexed with an | |
123 | * MDIO address. A 2nd reset at this time will make sure, that the | |
124 | * correct address is latched. | |
125 | */ | |
6d0f6bcf JCPV |
126 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); |
127 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); | |
54fd6c93 | 128 | udelay(1000); |
6d0f6bcf JCPV |
129 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); |
130 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); | |
54fd6c93 | 131 | udelay(1000); |
6d0f6bcf JCPV |
132 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); |
133 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); | |
54fd6c93 | 134 | |
b765ffb7 SR |
135 | return 0; |
136 | } | |
137 | ||
138 | /*---------------------------------------------------------------------------+ | |
139 | | misc_init_r. | |
140 | +---------------------------------------------------------------------------*/ | |
141 | int misc_init_r(void) | |
142 | { | |
143 | u32 pbcr; | |
144 | int size_val = 0; | |
145 | u32 reg; | |
146 | unsigned long usb2d0cr = 0; | |
147 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
148 | unsigned long sdr0_pfc1; | |
149 | ||
150 | /* | |
151 | * FLASH stuff... | |
152 | */ | |
153 | ||
154 | /* Re-do sizing to get full correct info */ | |
155 | ||
156 | /* adjust flash start and offset */ | |
157 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
158 | gd->bd->bi_flashoffset = 0; | |
159 | ||
160 | mfebc(pb0cr, pbcr); | |
161 | switch (gd->bd->bi_flashsize) { | |
162 | case 1 << 20: | |
163 | size_val = 0; | |
164 | break; | |
165 | case 2 << 20: | |
166 | size_val = 1; | |
167 | break; | |
168 | case 4 << 20: | |
169 | size_val = 2; | |
170 | break; | |
171 | case 8 << 20: | |
172 | size_val = 3; | |
173 | break; | |
174 | case 16 << 20: | |
175 | size_val = 4; | |
176 | break; | |
177 | case 32 << 20: | |
178 | size_val = 5; | |
179 | break; | |
180 | case 64 << 20: | |
181 | size_val = 6; | |
182 | break; | |
183 | case 128 << 20: | |
184 | size_val = 7; | |
185 | break; | |
186 | } | |
187 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
188 | mtebc(pb0cr, pbcr); | |
189 | ||
190 | /* | |
191 | * Re-check to get correct base address | |
192 | */ | |
193 | flash_get_size(gd->bd->bi_flashstart, 0); | |
194 | ||
195 | /* Monitor protection ON by default */ | |
196 | (void)flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 197 | -CONFIG_SYS_MONITOR_LEN, |
b765ffb7 | 198 | 0xffffffff, |
9f24a808 | 199 | &flash_info[1]); |
b765ffb7 SR |
200 | |
201 | /* Env protection ON by default */ | |
202 | (void)flash_protect(FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
203 | CONFIG_ENV_ADDR_REDUND, |
204 | CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, | |
9f24a808 | 205 | &flash_info[1]); |
b765ffb7 SR |
206 | |
207 | /* | |
208 | * USB suff... | |
209 | */ | |
210 | /* SDR Setting */ | |
211 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
212 | mfsdr(SDR0_USB0, usb2d0cr); | |
213 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
214 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
215 | ||
216 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
217 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
218 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
219 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
220 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
221 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ | |
222 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
223 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ | |
224 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
225 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ | |
226 | ||
227 | /* An 8-bit/60MHz interface is the only possible alternative | |
228 | when connecting the Device to the PHY */ | |
229 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
230 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
231 | ||
232 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
233 | mtsdr(SDR0_USB0, usb2d0cr); | |
234 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
235 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
236 | ||
237 | /* | |
238 | * Clear resets | |
239 | */ | |
240 | udelay (1000); | |
241 | mtsdr(SDR0_SRST1, 0x00000000); | |
242 | udelay (1000); | |
243 | mtsdr(SDR0_SRST0, 0x00000000); | |
244 | ||
245 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
246 | ||
247 | /* | |
248 | * Clear PLB4A0_ACR[WRP] | |
249 | * This fix will make the MAL burst disabling patch for the Linux | |
250 | * EMAC driver obsolete. | |
251 | */ | |
252 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; | |
253 | mtdcr(plb4_acr, reg); | |
254 | ||
3ad63878 SR |
255 | /* |
256 | * Init matrix keyboard | |
257 | */ | |
258 | misc_init_r_kbd(); | |
259 | ||
b765ffb7 SR |
260 | return 0; |
261 | } | |
262 | ||
263 | int checkboard(void) | |
264 | { | |
265 | char *s = getenv("serial#"); | |
266 | ||
267 | printf("Board: lwmon5"); | |
268 | ||
269 | if (s != NULL) { | |
270 | puts(", serial# "); | |
271 | puts(s); | |
272 | } | |
273 | putc('\n'); | |
274 | ||
275 | return (0); | |
276 | } | |
277 | ||
b765ffb7 SR |
278 | /************************************************************************* |
279 | * pci_pre_init | |
280 | * | |
281 | * This routine is called just prior to registering the hose and gives | |
282 | * the board the opportunity to check things. Returning a value of zero | |
283 | * indicates that things are bad & PCI initialization should be aborted. | |
284 | * | |
285 | * Different boards may wish to customize the pci controller structure | |
286 | * (add regions, override default access routines, etc) or perform | |
287 | * certain pre-initialization actions. | |
288 | * | |
289 | ************************************************************************/ | |
466fff1a | 290 | #if defined(CONFIG_PCI) |
b765ffb7 SR |
291 | int pci_pre_init(struct pci_controller *hose) |
292 | { | |
293 | unsigned long addr; | |
294 | ||
295 | /*-------------------------------------------------------------------------+ | |
296 | | Set priority for all PLB3 devices to 0. | |
297 | | Set PLB3 arbiter to fair mode. | |
298 | +-------------------------------------------------------------------------*/ | |
299 | mfsdr(sdr_amp1, addr); | |
300 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
301 | addr = mfdcr(plb3_acr); | |
302 | mtdcr(plb3_acr, addr | 0x80000000); | |
303 | ||
304 | /*-------------------------------------------------------------------------+ | |
305 | | Set priority for all PLB4 devices to 0. | |
306 | +-------------------------------------------------------------------------*/ | |
307 | mfsdr(sdr_amp0, addr); | |
308 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
309 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
310 | mtdcr(plb4_acr, addr); | |
311 | ||
312 | /*-------------------------------------------------------------------------+ | |
313 | | Set Nebula PLB4 arbiter to fair mode. | |
314 | +-------------------------------------------------------------------------*/ | |
315 | /* Segment0 */ | |
316 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
317 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
318 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
319 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
320 | mtdcr(plb0_acr, addr); | |
321 | ||
322 | /* Segment1 */ | |
323 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
324 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
325 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
326 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
327 | mtdcr(plb1_acr, addr); | |
328 | ||
329 | return 1; | |
330 | } | |
466fff1a | 331 | #endif /* defined(CONFIG_PCI) */ |
b765ffb7 SR |
332 | |
333 | /************************************************************************* | |
334 | * pci_target_init | |
335 | * | |
336 | * The bootstrap configuration provides default settings for the pci | |
337 | * inbound map (PIM). But the bootstrap config choices are limited and | |
338 | * may not be sufficient for a given board. | |
339 | * | |
340 | ************************************************************************/ | |
6d0f6bcf | 341 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
b765ffb7 SR |
342 | void pci_target_init(struct pci_controller *hose) |
343 | { | |
344 | /*--------------------------------------------------------------------------+ | |
345 | * Set up Direct MMIO registers | |
346 | *--------------------------------------------------------------------------*/ | |
347 | /*--------------------------------------------------------------------------+ | |
348 | | PowerPC440EPX PCI Master configuration. | |
349 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
350 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
351 | | Use byte reversed out routines to handle endianess. | |
352 | | Make this region non-prefetchable. | |
353 | +--------------------------------------------------------------------------*/ | |
354 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
6d0f6bcf JCPV |
355 | out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ |
356 | out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
b765ffb7 SR |
357 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
358 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
359 | ||
360 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
6d0f6bcf JCPV |
361 | out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ |
362 | out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
b765ffb7 SR |
363 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
364 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
365 | ||
366 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
367 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
368 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
369 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
370 | ||
371 | /*--------------------------------------------------------------------------+ | |
372 | * Set up Configuration registers | |
373 | *--------------------------------------------------------------------------*/ | |
374 | ||
375 | /* Program the board's subsystem id/vendor id */ | |
376 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
6d0f6bcf JCPV |
377 | CONFIG_SYS_PCI_SUBSYS_VENDORID); |
378 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); | |
b765ffb7 SR |
379 | |
380 | /* Configure command register as bus master */ | |
381 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
382 | ||
383 | /* 240nS PCI clock */ | |
384 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
385 | ||
386 | /* No error reporting */ | |
387 | pci_write_config_word(0, PCI_ERREN, 0); | |
388 | ||
389 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
390 | ||
391 | } | |
6d0f6bcf | 392 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
b765ffb7 SR |
393 | |
394 | /************************************************************************* | |
395 | * pci_master_init | |
396 | * | |
397 | ************************************************************************/ | |
6d0f6bcf | 398 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
b765ffb7 SR |
399 | void pci_master_init(struct pci_controller *hose) |
400 | { | |
401 | unsigned short temp_short; | |
402 | ||
403 | /*--------------------------------------------------------------------------+ | |
404 | | Write the PowerPC440 EP PCI Configuration regs. | |
405 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
406 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
407 | +--------------------------------------------------------------------------*/ | |
408 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
409 | pci_write_config_word(0, PCI_COMMAND, | |
410 | temp_short | PCI_COMMAND_MASTER | | |
411 | PCI_COMMAND_MEMORY); | |
412 | } | |
6d0f6bcf | 413 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ |
b765ffb7 SR |
414 | |
415 | /************************************************************************* | |
416 | * is_pci_host | |
417 | * | |
418 | * This routine is called to determine if a pci scan should be | |
419 | * performed. With various hardware environments (especially cPCI and | |
420 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
421 | * bit in the strap register, or generic host/adapter assumptions. | |
422 | * | |
423 | * Rather than hard-code a bad assumption in the general 440 code, the | |
424 | * 440 pci code requires the board to decide at runtime. | |
425 | * | |
426 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
427 | * | |
428 | * | |
429 | ************************************************************************/ | |
430 | #if defined(CONFIG_PCI) | |
431 | int is_pci_host(struct pci_controller *hose) | |
432 | { | |
433 | /* Cactus is always configured as host. */ | |
434 | return (1); | |
435 | } | |
436 | #endif /* defined(CONFIG_PCI) */ | |
437 | ||
438 | void hw_watchdog_reset(void) | |
439 | { | |
440 | int val; | |
d32a874b YT |
441 | #if defined(CONFIG_WD_MAX_RATE) |
442 | unsigned long long ct = get_ticks(); | |
443 | ||
444 | /* | |
445 | * Don't allow watch-dog triggering more frequently than | |
446 | * the predefined value CONFIG_WD_MAX_RATE [ticks]. | |
447 | */ | |
448 | if (ct >= gd->wdt_last) { | |
449 | if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE) | |
450 | return; | |
451 | } else { | |
452 | /* Time base counter had been reset */ | |
453 | if (((unsigned long long)(-1) - gd->wdt_last + ct) < | |
454 | CONFIG_WD_MAX_RATE) | |
455 | return; | |
456 | } | |
457 | gd->wdt_last = get_ticks(); | |
458 | #endif | |
b765ffb7 SR |
459 | |
460 | /* | |
461 | * Toggle watchdog output | |
462 | */ | |
6d0f6bcf JCPV |
463 | val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; |
464 | gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); | |
b765ffb7 | 465 | } |
c25dd8fc SR |
466 | |
467 | int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
468 | { | |
469 | if (argc < 2) { | |
62c3ae7c | 470 | cmd_usage(cmdtp); |
c25dd8fc SR |
471 | return 1; |
472 | } | |
473 | ||
474 | if ((strcmp(argv[1], "on") == 0)) { | |
6d0f6bcf | 475 | gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); |
c25dd8fc | 476 | } else if ((strcmp(argv[1], "off") == 0)) { |
6d0f6bcf | 477 | gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); |
c25dd8fc | 478 | } else { |
62c3ae7c | 479 | cmd_usage(cmdtp); |
c25dd8fc SR |
480 | return 1; |
481 | } | |
482 | ||
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | U_BOOT_CMD( | |
488 | eepromwp, 2, 0, do_eeprom_wp, | |
2fb2604d | 489 | "eeprom write protect off/on", |
c25dd8fc SR |
490 | "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n" |
491 | ); | |
d610a607 AG |
492 | |
493 | #if defined(CONFIG_VIDEO) | |
494 | #include <video_fb.h> | |
495 | #include <mb862xx.h> | |
496 | ||
497 | extern GraphicDevice mb862xx; | |
498 | ||
499 | static const gdc_regs init_regs [] = | |
500 | { | |
501 | {0x0100, 0x00000f00}, | |
502 | {0x0020, 0x801401df}, | |
503 | {0x0024, 0x00000000}, | |
504 | {0x0028, 0x00000000}, | |
505 | {0x002c, 0x00000000}, | |
506 | {0x0110, 0x00000000}, | |
507 | {0x0114, 0x00000000}, | |
508 | {0x0118, 0x01df0280}, | |
509 | {0x0004, 0x031f0000}, | |
510 | {0x0008, 0x027f027f}, | |
511 | {0x000c, 0x015f028f}, | |
512 | {0x0010, 0x020c0000}, | |
513 | {0x0014, 0x01df01ea}, | |
514 | {0x0018, 0x00000000}, | |
515 | {0x001c, 0x01e00280}, | |
516 | {0x0100, 0x80010f00}, | |
517 | {0x0, 0x0} | |
518 | }; | |
519 | ||
520 | const gdc_regs *board_get_regs (void) | |
521 | { | |
522 | return init_regs; | |
523 | } | |
524 | ||
525 | /* Returns Lime base address */ | |
526 | unsigned int board_video_init (void) | |
527 | { | |
528 | /* | |
529 | * Reset Lime controller | |
530 | */ | |
6d0f6bcf | 531 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); |
d610a607 | 532 | udelay(500); |
6d0f6bcf | 533 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); |
d610a607 AG |
534 | |
535 | /* Lime memory clock adjusted to 100MHz */ | |
6d0f6bcf | 536 | out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ); |
d610a607 AG |
537 | /* Wait untill time expired. Because of requirements in lime manual */ |
538 | udelay(300); | |
539 | /* Write lime controller memory parameters */ | |
6d0f6bcf | 540 | out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); |
d610a607 AG |
541 | |
542 | mb862xx.winSizeX = 640; | |
543 | mb862xx.winSizeY = 480; | |
544 | mb862xx.gdfBytesPP = 2; | |
545 | mb862xx.gdfIndex = GDF_15BIT_555RGB; | |
546 | ||
6d0f6bcf | 547 | return CONFIG_SYS_LIME_BASE_0; |
d610a607 AG |
548 | } |
549 | ||
0f855a1f YT |
550 | #define DEFAULT_BRIGHTNESS 0x64 |
551 | ||
552 | static void board_backlight_brightness(int brightness) | |
d610a607 | 553 | { |
0f855a1f | 554 | if (brightness > 0) { |
d610a607 | 555 | /* pwm duty, lamp on */ |
6d0f6bcf JCPV |
556 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); |
557 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); | |
d610a607 AG |
558 | } else { |
559 | /* lamp off */ | |
6d0f6bcf JCPV |
560 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); |
561 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); | |
d610a607 AG |
562 | } |
563 | } | |
564 | ||
0f855a1f YT |
565 | void board_backlight_switch (int flag) |
566 | { | |
567 | char * param; | |
568 | int rc; | |
569 | ||
570 | if (flag) { | |
571 | param = getenv("brightness"); | |
572 | rc = param ? simple_strtol(param, NULL, 10) : -1; | |
573 | if (rc < 0) | |
574 | rc = DEFAULT_BRIGHTNESS; | |
575 | } else { | |
576 | rc = 0; | |
577 | } | |
578 | board_backlight_brightness(rc); | |
579 | } | |
580 | ||
d610a607 AG |
581 | #if defined(CONFIG_CONSOLE_EXTRA_INFO) |
582 | /* | |
583 | * Return text to be printed besides the logo. | |
584 | */ | |
585 | void video_get_info_str (int line_number, char *info) | |
586 | { | |
587 | if (line_number == 1) { | |
588 | strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); | |
589 | } else { | |
590 | info [0] = '\0'; | |
591 | } | |
592 | } | |
593 | #endif | |
594 | #endif /* CONFIG_VIDEO */ | |
ff818b21 YT |
595 | |
596 | void board_reset(void) | |
597 | { | |
6d0f6bcf | 598 | gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); |
ff818b21 | 599 | } |