[u-boot.git] / board / amcc / taishan / showinfo.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <pci.h>

void show_reset_reg(void)
{
	unsigned long reg;

	/* read clock regsiter */
	printf("===== Display reset and initialize register Start =========\n");
	mfcpr(clk_pllc,reg);
	printf("cpr_pllc   = %#010lx\n",reg);

	mfcpr(clk_plld,reg);
	printf("cpr_plld   = %#010lx\n",reg);

	mfcpr(clk_primad,reg);
	printf("cpr_primad = %#010lx\n",reg);

	mfcpr(clk_primbd,reg);
	printf("cpr_primbd = %#010lx\n",reg);

	mfcpr(clk_opbd,reg);
	printf("cpr_opbd   = %#010lx\n",reg);

	mfcpr(clk_perd,reg);
	printf("cpr_perd   = %#010lx\n",reg);

	mfcpr(clk_mald,reg);
	printf("cpr_mald   = %#010lx\n",reg);

	/* read sdr register */
	mfsdr(sdr_ebc,reg);
	printf("sdr_ebc    = %#010lx\n",reg);

	mfsdr(sdr_cp440,reg);
	printf("sdr_cp440  = %#010lx\n",reg);

	mfsdr(sdr_xcr,reg);
	printf("sdr_xcr    = %#010lx\n",reg);

	mfsdr(sdr_xpllc,reg);
	printf("sdr_xpllc  = %#010lx\n",reg);

	mfsdr(sdr_xplld,reg);
	printf("sdr_xplld  = %#010lx\n",reg);

	mfsdr(sdr_pfc0,reg);
	printf("sdr_pfc0   = %#010lx\n",reg);

	mfsdr(sdr_pfc1,reg);
	printf("sdr_pfc1   = %#010lx\n",reg);

	mfsdr(sdr_cust0,reg);
	printf("sdr_cust0  = %#010lx\n",reg);

	mfsdr(sdr_cust1,reg);
	printf("sdr_cust1  = %#010lx\n",reg);

	mfsdr(sdr_uart0,reg);
	printf("sdr_uart0  = %#010lx\n",reg);

	mfsdr(sdr_uart1,reg);
	printf("sdr_uart1  = %#010lx\n",reg);

	printf("===== Display reset and initialize register End   =========\n");
}

void show_xbridge_info(void)
{
	unsigned long reg;

	printf("PCI-X chip control registers\n");
	mfsdr(sdr_xcr, reg);
	printf("sdr_xcr    = %#010lx\n", reg);

	mfsdr(sdr_xpllc, reg);
	printf("sdr_xpllc  = %#010lx\n", reg);

	mfsdr(sdr_xplld, reg);
	printf("sdr_xplld  = %#010lx\n", reg);

	printf("PCI-X Bridge Configure registers\n");
	printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
	printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
	printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
	printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
	printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
	printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
	printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
	printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
	printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));

	printf("PCIX0_BAR0              = %#010lx\n", in32r(PCIX0_BAR0));
	printf("PCIX0_BAR1              = %#010lx\n", in32r(PCIX0_BAR1));
	printf("PCIX0_BAR2              = %#010lx\n", in32r(PCIX0_BAR2));
	printf("PCIX0_BAR3              = %#010lx\n", in32r(PCIX0_BAR3));
	printf("PCIX0_BAR4              = %#010lx\n", in32r(PCIX0_BAR4));
	printf("PCIX0_BAR5              = %#010lx\n", in32r(PCIX0_BAR5));

	printf("PCIX0_CISPTR            = %#010lx\n", in32r(PCIX0_CISPTR));
	printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
	printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
	printf("PCIX0_EROMBA            = %#010lx\n", in32r(PCIX0_EROMBA));
	printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
	printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
	printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
	printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
	printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));

	printf("PCIX0_BRDGOPT1          = %#010lx\n", in32r(PCIX0_BRDGOPT1));
	printf("PCIX0_BRDGOPT2          = %#010lx\n", in32r(PCIX0_BRDGOPT2));

	printf("PCIX0_POM0LAL           = %#010lx\n", in32r(PCIX0_POM0LAL));
	printf("PCIX0_POM0LAH           = %#010lx\n", in32r(PCIX0_POM0LAH));
	printf("PCIX0_POM0SA            = %#010lx\n", in32r(PCIX0_POM0SA));
	printf("PCIX0_POM0PCILAL        = %#010lx\n", in32r(PCIX0_POM0PCIAL));
	printf("PCIX0_POM0PCILAH        = %#010lx\n", in32r(PCIX0_POM0PCIAH));
	printf("PCIX0_POM1LAL           = %#010lx\n", in32r(PCIX0_POM1LAL));
	printf("PCIX0_POM1LAH           = %#010lx\n", in32r(PCIX0_POM1LAH));
	printf("PCIX0_POM1SA            = %#010lx\n", in32r(PCIX0_POM1SA));
	printf("PCIX0_POM1PCILAL        = %#010lx\n", in32r(PCIX0_POM1PCIAL));
	printf("PCIX0_POM1PCILAH        = %#010lx\n", in32r(PCIX0_POM1PCIAH));
	printf("PCIX0_POM2SA            = %#010lx\n", in32r(PCIX0_POM2SA));

	printf("PCIX0_PIM0SA            = %#010lx\n", in32r(PCIX0_PIM0SA));
	printf("PCIX0_PIM0LAL           = %#010lx\n", in32r(PCIX0_PIM0LAL));
	printf("PCIX0_PIM0LAH           = %#010lx\n", in32r(PCIX0_PIM0LAH));
	printf("PCIX0_PIM1SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
	printf("PCIX0_PIM1LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
	printf("PCIX0_PIM1LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
	printf("PCIX0_PIM2SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
	printf("PCIX0_PIM2LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
	printf("PCIX0_PIM2LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));

	printf("PCIX0_XSTS              = %#010lx\n", in32r(PCIX0_STS));
}

int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	show_xbridge_info();
	return 0;
}

U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
	   "Show PCIX bridge info", NULL);

#define TAISHAN_PCI_DEV_ID0 0x800
#define TAISHAN_PCI_DEV_ID1 0x1000

void show_pcix_device_info(void)
{
	int ii;
	int dev;
	u8 capp;
	u8 xcapid;
	u16 status;
	u16 xcommand;
	u32 xstatus;

	for (ii = 0; ii < 2; ii++) {
		if (ii == 0)
			dev = TAISHAN_PCI_DEV_ID0;
		else
			dev = TAISHAN_PCI_DEV_ID1;

		pci_read_config_word(dev, PCI_STATUS, &status);
		if (status & PCI_STATUS_CAP_LIST) {
			pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);

			pci_read_config_byte(dev, (int)(capp), &xcapid);
			if (xcapid == 0x07) {
				pci_read_config_word(dev, (int)(capp + 2),
						     &xcommand);
				pci_read_config_dword(dev, (int)(capp + 4),
						      &xstatus);
				printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
				       (ii + 1), xcommand, xstatus);
			} else {
				printf("BUS0 dev%d PCI-X CAP ID error,"
				       "CAP=%#04x,XCAPID=%#04x\n",
				       (ii + 1), capp, xcapid);
			}
		} else {
			printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
			       ii + 1);
		}
	}

}

int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
			     char *argv[])
{
	show_pcix_device_info();
	return 0;
}

U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
	   "Show PCIX Device info", NULL);

extern void show_reset_reg(void);

int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	show_reset_reg();
	return 0;
}

U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
	   "Show Reset REG info", NULL);
Commit	Line	Data
5fb692ca SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <config.h>
	25	#include <common.h>
	26	#include <command.h>
	27	#include <asm/processor.h>
	28	#include <pci.h>
	29
	30	void show_reset_reg(void)
	31	{
	32	unsigned long reg;
	33
	34	/* read clock regsiter */
	35	printf("===== Display reset and initialize register Start =========\n");
087dfdb7	36	mfcpr(clk_pllc,reg);
bde63587	37	printf("cpr_pllc = %#010lx\n",reg);
5fb692ca	38
087dfdb7	39	mfcpr(clk_plld,reg);
bde63587	40	printf("cpr_plld = %#010lx\n",reg);
5fb692ca	41
087dfdb7	42	mfcpr(clk_primad,reg);
bde63587	43	printf("cpr_primad = %#010lx\n",reg);
5fb692ca	44
087dfdb7	45	mfcpr(clk_primbd,reg);
bde63587	46	printf("cpr_primbd = %#010lx\n",reg);
5fb692ca	47
087dfdb7	48	mfcpr(clk_opbd,reg);
bde63587	49	printf("cpr_opbd = %#010lx\n",reg);
5fb692ca	50
087dfdb7	51	mfcpr(clk_perd,reg);
bde63587	52	printf("cpr_perd = %#010lx\n",reg);
5fb692ca	53
087dfdb7	54	mfcpr(clk_mald,reg);
bde63587	55	printf("cpr_mald = %#010lx\n",reg);
5fb692ca SR	56
	57	/* read sdr register */
	58	mfsdr(sdr_ebc,reg);
bde63587	59	printf("sdr_ebc = %#010lx\n",reg);
5fb692ca SR	60
5fb692ca SR	61	mfsdr(sdr_cp440,reg);
bde63587	62	printf("sdr_cp440 = %#010lx\n",reg);
5fb692ca SR	63
5fb692ca SR	64	mfsdr(sdr_xcr,reg);
bde63587	65	printf("sdr_xcr = %#010lx\n",reg);
5fb692ca SR	66
5fb692ca SR	67	mfsdr(sdr_xpllc,reg);
bde63587	68	printf("sdr_xpllc = %#010lx\n",reg);
5fb692ca SR	69
5fb692ca SR	70	mfsdr(sdr_xplld,reg);
bde63587	71	printf("sdr_xplld = %#010lx\n",reg);
5fb692ca SR	72
5fb692ca SR	73	mfsdr(sdr_pfc0,reg);
bde63587	74	printf("sdr_pfc0 = %#010lx\n",reg);
5fb692ca SR	75
5fb692ca SR	76	mfsdr(sdr_pfc1,reg);
bde63587	77	printf("sdr_pfc1 = %#010lx\n",reg);
5fb692ca SR	78
5fb692ca SR	79	mfsdr(sdr_cust0,reg);
bde63587	80	printf("sdr_cust0 = %#010lx\n",reg);
5fb692ca SR	81
5fb692ca SR	82	mfsdr(sdr_cust1,reg);
bde63587	83	printf("sdr_cust1 = %#010lx\n",reg);
5fb692ca SR	84
5fb692ca SR	85	mfsdr(sdr_uart0,reg);
bde63587	86	printf("sdr_uart0 = %#010lx\n",reg);
5fb692ca SR	87
5fb692ca SR	88	mfsdr(sdr_uart1,reg);
bde63587	89	printf("sdr_uart1 = %#010lx\n",reg);
5fb692ca SR	90
	91	printf("===== Display reset and initialize register End =========\n");
	92	}
	93
	94	void show_xbridge_info(void)
	95	{
	96	unsigned long reg;
	97
	98	printf("PCI-X chip control registers\n");
	99	mfsdr(sdr_xcr, reg);
bde63587	100	printf("sdr_xcr = %#010lx\n", reg);
5fb692ca SR	101
5fb692ca SR	102	mfsdr(sdr_xpllc, reg);
bde63587	103	printf("sdr_xpllc = %#010lx\n", reg);
5fb692ca SR	104
5fb692ca SR	105	mfsdr(sdr_xplld, reg);
bde63587	106	printf("sdr_xplld = %#010lx\n", reg);
5fb692ca SR	107
	108	printf("PCI-X Bridge Configure registers\n");
	109	printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
	110	printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
	111	printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
	112	printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
	113	printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
	114	printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
	115	printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
	116	printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
	117	printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
	118
bde63587 WD	119	printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
	120	printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
	121	printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
	122	printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
	123	printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
	124	printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
5fb692ca	125
bde63587	126	printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
5fb692ca SR	127	printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
5fb692ca SR	128	printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
bde63587	129	printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
5fb692ca SR	130	printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
	131	printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
	132	printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
	133	printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
	134	printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
	135
bde63587 WD	136	printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
	137	printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
	138
	139	printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
	140	printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
	141	printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
	142	printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
	143	printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
	144	printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
	145	printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
	146	printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
	147	printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
	148	printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
	149	printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
	150
	151	printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
	152	printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
	153	printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
	154	printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
	155	printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
	156	printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
	157	printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
	158	printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
	159	printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
	160
	161	printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
5fb692ca SR	162	}
	163
	164	int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	165	{
	166	show_xbridge_info();
	167	return 0;
	168	}
	169
	170	U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
2fb2604d	171	"Show PCIX bridge info", NULL);
5fb692ca SR	172
	173	#define TAISHAN_PCI_DEV_ID0 0x800
	174	#define TAISHAN_PCI_DEV_ID1 0x1000
	175
	176	void show_pcix_device_info(void)
	177	{
	178	int ii;
	179	int dev;
	180	u8 capp;
	181	u8 xcapid;
	182	u16 status;
	183	u16 xcommand;
	184	u32 xstatus;
	185
	186	for (ii = 0; ii < 2; ii++) {
	187	if (ii == 0)
	188	dev = TAISHAN_PCI_DEV_ID0;
	189	else
	190	dev = TAISHAN_PCI_DEV_ID1;
	191
	192	pci_read_config_word(dev, PCI_STATUS, &status);
	193	if (status & PCI_STATUS_CAP_LIST) {
	194	pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
	195
	196	pci_read_config_byte(dev, (int)(capp), &xcapid);
	197	if (xcapid == 0x07) {
	198	pci_read_config_word(dev, (int)(capp + 2),
	199	&xcommand);
	200	pci_read_config_dword(dev, (int)(capp + 4),
	201	&xstatus);
	202	printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
	203	(ii + 1), xcommand, xstatus);
	204	} else {
	205	printf("BUS0 dev%d PCI-X CAP ID error,"
	206	"CAP=%#04x,XCAPID=%#04x\n",
	207	(ii + 1), capp, xcapid);
	208	}
	209	} else {
	210	printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
	211	ii + 1);
	212	}
	213	}
	214
	215	}
	216
	217	int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
	218	char *argv[])
	219	{
	220	show_pcix_device_info();
	221	return 0;
	222	}
	223
	224	U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
2fb2604d	225	"Show PCIX Device info", NULL);
5fb692ca SR	226
	227	extern void show_reset_reg(void);
	228
	229	int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	230	{
	231	show_reset_reg();
	232	return 0;
	233	}
	234
	235	U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
2fb2604d	236	"Show Reset REG info", NULL);