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common: Move hang() to the same header as panic()
[u-boot.git] / board / BuR / brppt2 / board.c
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c04ac5bd
HS		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board functions for BuR BRPPT2 board
4 *
5 * Copyright (C) 2019
6 * B&R Industrial Automation GmbH - http://www.br-automation.com/
7 *
8 */
9#include <common.h>
657afb14 10#include <cpu_func.h>
29a4a9f1 11#include <hang.h>
c04ac5bd
HS		 12#include <spl.h>
13#include <dm.h>
14#include <miiphy.h>
15#include <asm/arch/crm_regs.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/arch/iomux.h>
18#include <asm/arch/mx6-pins.h>
19#ifdef CONFIG_SPL_BUILD
20# include <asm/arch/mx6-ddr.h>
21#endif
22#include <asm/arch/clock.h>
23#include <asm/io.h>
24#include <asm/gpio.h>
25
26#define USBHUB_RSTN IMX_GPIO_NR(1, 16)
27#define BKLT_EN IMX_GPIO_NR(1, 15)
28#define CAPT_INT IMX_GPIO_NR(4, 9)
29#define CAPT_RESETN IMX_GPIO_NR(4, 11)
30#define SW_INTN IMX_GPIO_NR(3, 26)
31#define VCCDISP_EN IMX_GPIO_NR(5, 18)
32#define EMMC_RSTN IMX_GPIO_NR(6, 8)
33#define PMIC_IRQN IMX_GPIO_NR(5, 22)
34#define TASTER IMX_GPIO_NR(5, 23)
35
36#define ETH0_LINK IMX_GPIO_NR(1, 27)
37#define ETH1_LINK IMX_GPIO_NR(1, 28)
38
39#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
41 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
42
43#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
45 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
46
47#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
56 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
57
58#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
60 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
61
62#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
64 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
65
66#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
67 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
68 PAD_CTL_SRE_FAST)
69
70#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
71 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
72 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
73
74#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
75 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
76 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
77
78#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
79 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
80 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
81
82#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
83
84#if !defined(CONFIG_SPL_BUILD)
85static iomux_v3_cfg_t const eth_pads[] = {
86 /*
87 * Gigabit Ethernet
88 */
89 /* CLKs */
90 MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
91 MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
92 /* MDIO */
93 MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
94 MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
95 /* RGMII */
96 MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
97 MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
98 MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
99 MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
100 MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
101 MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
102 MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
103 MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
104 MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
105 MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
106 MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
107 MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
108 /* ETH0_LINK */
109 MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
110 /* ETH1_LINK */
111 MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
112};
113
114static iomux_v3_cfg_t const board_pads[] = {
115 /*
116 * I2C #3, #4
117 */
118 MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
119 MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
120
121 /*
122 * UART#4 PADS
123 * UART_Tasten
124 */
125 MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
126 MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
127 MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
128 MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
129 /*
130 * ESCPI#1
131 * M25P32 NOR-Flash
132 */
133 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
134 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
135 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
136 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
137 /*
138 * ESCPI#2
139 * resTouch SPI ADC
140 */
141 MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
142 MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
143 MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
144 MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
145 /*
146 * USDHC#4
147 */
148 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
149 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
150 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
151 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
152 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
153 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
154 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
155 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
156 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
157 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
158 /*
159 * USB OTG power & ID
160 */
161 /* USB_OTG_5V_EN */
162 MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
163 MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
164 /* USB_OTG_JUMPER */
165 MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
166 /*
167 * PWM-Pins
168 */
169 /* BKLT_CTL */
170 MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
171 /* SPEAKER */
172 MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
173 /*
174 * GPIOs
175 */
176 /* USB_HUB_nRESET */
177 MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
178 /* BKLT_EN */
179 MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
180 /* capTouch_INT */
181 MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
182 /* capTouch_nRESET */
183 MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
184 /* SW_nINT */
185 MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
186 /* VCC_DISP_EN */
187 MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
188 /* eMMC_nRESET */
189 MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
190 /* HWID*/
191 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
192 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
193 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
194 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
195 /* PMIC_nIRQ */
196 MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
197 /* nTASTER */
198 MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
199 /* RGB LCD Display */
200 MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
201 MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
202 MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
203 MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
204 MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
205 MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
206 MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
207 MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
208 MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
209 MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
210 MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
211 MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
212 MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
213 MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
214 MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
215 MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
216 MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
217 MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
218 MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
219 MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
220 MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
221 MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
222 MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
223 MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
224 MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
225 MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
226 MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
227 MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
228 MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
229};
230
231int board_ehci_hcd_init(int port)
232{
233 gpio_direction_output(USBHUB_RSTN, 1);
234
235 return 0;
236}
237
238int board_late_init(void)
239{
240 ulong b_mode = 4;
241
242 if (gpio_get_value(TASTER) == 0)
243 b_mode = 12;
244
245 env_set_ulong("b_mode", b_mode);
246
247 return 0;
248}
249
250int board_init(void)
251{
252 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
253
254 if (gpio_request(BKLT_EN, "BKLT_EN"))
255 printf("Warning: BKLT_EN setup failed\n");
256 gpio_direction_output(BKLT_EN, 0);
257
258 if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
259 printf("Warning: USBHUB_nRST setup failed\n");
260 gpio_direction_output(USBHUB_RSTN, 0);
261
262 if (gpio_request(TASTER, "TASTER"))
263 printf("Warning: TASTER setup failed\n");
264 gpio_direction_input(TASTER);
265
266 return 0;
267}
268
269int board_early_init_f(void)
270{
271 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
272
273 SETUP_IOMUX_PADS(board_pads);
274 SETUP_IOMUX_PADS(eth_pads);
275
276 /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
277 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
278 enable_fec_anatop_clock(0, ENET_25MHZ);
279 enable_enet_clk(1);
280
281 return 0;
282}
283
284int dram_init(void)
285{
286 gd->ram_size = imx_ddr_size();
287
288 return 0;
289}
290#else
291/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
292static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
293 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
294 .dram_sdclk_0 = 0x00020030,
295 .dram_sdclk_1 = 0x00020030,
296 .dram_cas = 0x00020030,
297 .dram_ras = 0x00020030,
298 .dram_reset = 0x00020030,
299 /* SDCKE[0:1]: 100k pull-up */
300 .dram_sdcke0 = 0x00003000,
301 .dram_sdcke1 = 0x00003000,
302 /* SDBA2: pull-up disabled */
303 .dram_sdba2 = 0x00000000,
304 /* SDODT[0:1]: 100k pull-up, 40 ohm */
305 .dram_sdodt0 = 0x00003030,
306 .dram_sdodt1 = 0x00003030,
307 /* SDQS[0:7]: Differential input, 40 ohm */
308 .dram_sdqs0 = 0x00000030,
309 .dram_sdqs1 = 0x00000030,
310 .dram_sdqs2 = 0x00000030,
311 .dram_sdqs3 = 0x00000030,
312 .dram_sdqs4 = 0x00000030,
313 .dram_sdqs5 = 0x00000030,
314 .dram_sdqs6 = 0x00000030,
315 .dram_sdqs7 = 0x00000030,
316 /* DQM[0:7]: Differential input, 40 ohm */
317 .dram_dqm0 = 0x00020030,
318 .dram_dqm1 = 0x00020030,
319 .dram_dqm2 = 0x00020030,
320 .dram_dqm3 = 0x00020030,
321 .dram_dqm4 = 0x00020030,
322 .dram_dqm5 = 0x00020030,
323 .dram_dqm6 = 0x00020030,
324 .dram_dqm7 = 0x00020030,
325};
326
327/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
328static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
329 /* DDR3 */
330 .grp_ddr_type = 0x000c0000,
331 .grp_ddrmode_ctl = 0x00020000,
332 /* disable DDR pullups */
333 .grp_ddrpke = 0x00000000,
334 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
335 .grp_addds = 0x00000030,
336 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
337 .grp_ctlds = 0x00000030,
338 /* DATA[00:63]: Differential input, 40 ohm */
339 .grp_ddrmode = 0x00020000,
340 .grp_b0ds = 0x00000030,
341 .grp_b1ds = 0x00000030,
342 .grp_b2ds = 0x00000030,
343 .grp_b3ds = 0x00000030,
344 .grp_b4ds = 0x00000030,
345 .grp_b5ds = 0x00000030,
346 .grp_b6ds = 0x00000030,
347 .grp_b7ds = 0x00000030,
348};
349
350/*
351 * DDR3 desriptions - these are the memory chips we support
352 */
353
354/* NT5CC128M16FP-DII */
355static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
356 .mem_speed = 1600,
357 .density = 2,
358 .width = 16,
359 .banks = 8,
360 .rowaddr = 14,
361 .coladdr = 10,
362 .pagesz = 2,
363 .trcd = 1375,
364 .trcmin = 4875,
365 .trasmin = 3500,
366};
367
368/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
369static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
370 /* write leveling calibration determine, MR1-value = 0x0002 */
371 .p0_mpwldectrl0 = 0x003F003E,
372 .p0_mpwldectrl1 = 0x003A003A,
373 .p1_mpwldectrl0 = 0x001B001C,
374 .p1_mpwldectrl1 = 0x00190031,
375 /* Read DQS Gating calibration */
376 .p0_mpdgctrl0 = 0x02640264,
377 .p0_mpdgctrl1 = 0x02440250,
378 .p1_mpdgctrl0 = 0x02400250,
379 .p1_mpdgctrl1 = 0x0238023C,
380 /* Read Calibration: DQS delay relative to DQ read access */
381 .p0_mprddlctl = 0x40464644,
382 .p1_mprddlctl = 0x464A4842,
383 /* Write Calibration: DQ/DM delay relative to DQS write access */
384 .p0_mpwrdlctl = 0x38343034,
385 .p1_mpwrdlctl = 0x36323830,
386};
387
388/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
389static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
390 /* write leveling calibration determine, MR1-value = 0x0002 */
391 .p0_mpwldectrl0 = 0x00410043,
392 .p0_mpwldectrl1 = 0x003A003C,
393 /* Read DQS Gating calibration */
394 .p0_mpdgctrl0 = 0x023C0244,
395 .p0_mpdgctrl1 = 0x02240230,
396 /* Read Calibration: DQS delay relative to DQ read access */
397 .p0_mprddlctl = 0x484C4A48,
398 /* Write Calibration: DQ/DM delay relative to DQS write access */
399 .p0_mpwrdlctl = 0x3C363434,
400};
401
402static void spl_dram_init(void)
403{
404 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
405 u32 val, dram_strap = 0;
406 struct mx6_ddr3_cfg *mem = NULL;
407 struct mx6_mmdc_calibration *calib = NULL;
408 struct mx6_ddr_sysinfo sysinfo = {
409 /* width of data bus:0=16,1=32,2=64 */
410 .dsize = -1, /* CPU type specific (overwritten) */
411 /* config for full 4GB range so that get_mem_size() works */
412 .cs_density = 32, /* 32Gb per CS */
413 .ncs = 1, /* single chip select */
414 .cs1_mirror = 0,
415 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
416 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
417 .walat = 1, /* Write additional latency */
418 .ralat = 5, /* Read additional latency */
419 .mif3_mode = 3, /* Command prediction working mode */
420 .bi_on = 1, /* Bank interleaving enabled */
421 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
422 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
423 .ddr_type = 0, /* DDR3 */
424 };
425
426 /*
427 * MMDC Calibration requires the following data:
428 * mx6_mmdc_calibration - board-specific calibration (routing delays)
429 * these calibration values depend on board routing, SoC, and DDR
430 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
431 * mx6_ddr_cfg - chip specific timing/layout details
432 */
433
434 /* setup HWID3-2 to input */
435 val = readl(&gpio->gpio_dir);
436 val &= ~(0x1 << 0 | 0x1 << 1);
437 writel(val, &gpio->gpio_dir);
438
439 /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
440 dram_strap = readl(&gpio->gpio_psr) & 0x3;
441
442 switch (dram_strap) {
443 /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
444 case 0:
445 puts("DRAM strap 00\n");
446 mem = &cfg_nt5cc128m16fp_dii;
447 sysinfo.dsize = 2;
448 calib = &cal_nt5cc128m16fp_dii_128x64_s;
449 break;
450 /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
451 case 1:
452 puts("DRAM strap 01\n");
453 mem = &cfg_nt5cc128m16fp_dii;
454 sysinfo.dsize = 1;
455 calib = &cal_nt5cc128m16fp_dii_128x32_s;
456 break;
457 default:
458 printf("DRAM strap 0x%x (invalid)\n", dram_strap);
459 break;
460 }
461
462 if (!mem) {
463 puts("Error: Invalid Memory Configuration\n");
464 hang();
465 }
466 if (!calib) {
467 puts("Error: Invalid Board Calibration Configuration\n");
468 hang();
469 }
470
471 mx6sdl_dram_iocfg(16 << sysinfo.dsize,
472 &ddr_iomux_s,
473 &grp_iomux_s);
474
475 mx6_dram_cfg(&sysinfo, calib, mem);
476}
477
478static iomux_v3_cfg_t const board_pads_spl[] = {
479 /* UART#1 PADS */
480 MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
481 MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
482 /* ESCPI#1 PADS */
483 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
484 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
485 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
486 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
487 /* USDHC#4 PADS */
488 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
489 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
490 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
491 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
492 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
493 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
494 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
495 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
496 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
497 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
498 /* HWID*/
499 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
500 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
501 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
502 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
503};
504
505void spl_board_init(void)
506{
507 preloader_console_init();
508}
509
510static void ccgr_init(void)
511{
512 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
513
514 /*
515 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
516 * initializes DMA very early (before all board code), so the only
517 * opportunity we have to initialize APBHDMA clocks is in SPL.
518 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
519 */
520
521 writel(0x00C03F3F, &ccm->CCGR0);
522 writel(0x00F0FC03, &ccm->CCGR1);
523 writel(0x0FFFF000, &ccm->CCGR2);
524 writel(0x3FF00000, &ccm->CCGR3);
525 writel(0x00FFF300, &ccm->CCGR4);
526 writel(0x0F0030C3, &ccm->CCGR5);
527 writel(0x000003F0, &ccm->CCGR6);
528}
529
530void board_init_f(ulong dummy)
531{
532 ccgr_init();
533 arch_cpu_init();
534 timer_init();
535 gpr_init();
536
537 SETUP_IOMUX_PADS(board_pads_spl);
538 spl_dram_init();
539}
540
541void reset_cpu(ulong addr)
542{
543}
544#endif /* CONFIG_SPL_BUILD */
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