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938080dc JL |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
3 | * Jason Liu <[email protected]> | |
4 | * | |
5 | * Configuration settings for Freescale MX53 low cost board. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
938080dc JL |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_MX53 | |
14 | ||
9df82896 FE |
15 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO |
16 | ||
938080dc JL |
17 | #include <asm/arch/imx-regs.h> |
18 | ||
19 | #define CONFIG_CMDLINE_TAG | |
938080dc JL |
20 | #define CONFIG_SETUP_MEMORY_TAGS |
21 | #define CONFIG_INITRD_TAG | |
22 | ||
18fb0e3c | 23 | #define CONFIG_SYS_FSL_CLK |
6ca896f9 | 24 | |
938080dc | 25 | /* Size of malloc() pool */ |
f714b0a9 | 26 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
938080dc JL |
27 | |
28 | #define CONFIG_BOARD_EARLY_INIT_F | |
54bb8411 | 29 | #define CONFIG_BOARD_LATE_INIT |
938080dc | 30 | #define CONFIG_MXC_GPIO |
54cd1dee | 31 | #define CONFIG_REVISION_TAG |
938080dc JL |
32 | |
33 | #define CONFIG_MXC_UART | |
40f6fffe | 34 | #define CONFIG_MXC_UART_BASE UART1_BASE |
938080dc JL |
35 | |
36 | /* MMC Configs */ | |
37 | #define CONFIG_FSL_ESDHC | |
38 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
39 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
40 | ||
41 | #define CONFIG_MMC | |
938080dc | 42 | #define CONFIG_GENERIC_MMC |
938080dc JL |
43 | #define CONFIG_DOS_PARTITION |
44 | ||
45 | /* Eth Configs */ | |
938080dc | 46 | #define CONFIG_MII |
938080dc JL |
47 | |
48 | #define CONFIG_FEC_MXC | |
49 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
50 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
51 | ||
45cf6ada | 52 | /* USB Configs */ |
45cf6ada WG |
53 | #define CONFIG_USB_EHCI |
54 | #define CONFIG_USB_EHCI_MX5 | |
45cf6ada WG |
55 | #define CONFIG_USB_HOST_ETHER |
56 | #define CONFIG_USB_ETHER_ASIX | |
a743415f | 57 | #define CONFIG_USB_ETHER_MCS7830 |
45cf6ada WG |
58 | #define CONFIG_USB_ETHER_SMSC95XX |
59 | #define CONFIG_MXC_USB_PORT 1 | |
60 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
61 | #define CONFIG_MXC_USB_FLAGS 0 | |
62 | ||
e7e33722 | 63 | /* I2C Configs */ |
b089d039 | 64 | #define CONFIG_SYS_I2C |
65 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
66 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
67 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 68 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
e7e33722 FE |
69 | |
70 | /* PMIC Controller */ | |
be3b51aa ŁM |
71 | #define CONFIG_POWER |
72 | #define CONFIG_POWER_I2C | |
2988e866 | 73 | #define CONFIG_DIALOG_POWER |
be3b51aa | 74 | #define CONFIG_POWER_FSL |
913702ca | 75 | #define CONFIG_POWER_FSL_MC13892 |
e7e33722 | 76 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 |
5b547f3c | 77 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
e7e33722 | 78 | |
938080dc JL |
79 | /* allow to overwrite serial and ethaddr */ |
80 | #define CONFIG_ENV_OVERWRITE | |
81 | #define CONFIG_CONS_INDEX 1 | |
82 | #define CONFIG_BAUDRATE 115200 | |
938080dc JL |
83 | |
84 | /* Command definition */ | |
ec62c07a | 85 | #define CONFIG_SUPPORT_RAW_INITRD |
938080dc | 86 | |
938080dc | 87 | |
28b119e9 | 88 | #define CONFIG_ETHPRIME "FEC0" |
938080dc | 89 | |
fe51f787 | 90 | #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ |
938080dc JL |
91 | #define CONFIG_SYS_TEXT_BASE 0x77800000 |
92 | ||
93 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
94 | "script=boot.scr\0" \ | |
f28154b5 | 95 | "image=zImage\0" \ |
e0df5353 OS |
96 | "fdt_addr=0x71000000\0" \ |
97 | "boot_fdt=try\0" \ | |
98 | "ip_dyn=yes\0" \ | |
938080dc | 99 | "mmcdev=0\0" \ |
254fd8da OS |
100 | "mmcpart=1\0" \ |
101 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
e0df5353 | 102 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ |
938080dc | 103 | "loadbootscript=" \ |
54e0f96f | 104 | "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
938080dc JL |
105 | "bootscript=echo Running bootscript from mmc ...; " \ |
106 | "source\0" \ | |
54e0f96f GG |
107 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
108 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
938080dc JL |
109 | "mmcboot=echo Booting from mmc ...; " \ |
110 | "run mmcargs; " \ | |
e0df5353 OS |
111 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
112 | "if run loadfdt; then " \ | |
f28154b5 | 113 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
114 | "else " \ |
115 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 116 | "bootz; " \ |
e0df5353 OS |
117 | "else " \ |
118 | "echo WARN: Cannot load the DT; " \ | |
119 | "fi; " \ | |
120 | "fi; " \ | |
121 | "else " \ | |
f28154b5 | 122 | "bootz; " \ |
e0df5353 | 123 | "fi;\0" \ |
938080dc JL |
124 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
125 | "root=/dev/nfs " \ | |
126 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
127 | "netboot=echo Booting from net ...; " \ | |
128 | "run netargs; " \ | |
e0df5353 OS |
129 | "if test ${ip_dyn} = yes; then " \ |
130 | "setenv get_cmd dhcp; " \ | |
131 | "else " \ | |
132 | "setenv get_cmd tftp; " \ | |
133 | "fi; " \ | |
f28154b5 | 134 | "${get_cmd} ${image}; " \ |
e0df5353 OS |
135 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
136 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
f28154b5 | 137 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
138 | "else " \ |
139 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 140 | "bootz; " \ |
e0df5353 OS |
141 | "else " \ |
142 | "echo ERROR: Cannot load the DT; " \ | |
143 | "exit; " \ | |
144 | "fi; " \ | |
145 | "fi; " \ | |
146 | "else " \ | |
f28154b5 | 147 | "bootz; " \ |
e0df5353 | 148 | "fi;\0" |
938080dc JL |
149 | |
150 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 151 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
938080dc JL |
152 | "if run loadbootscript; then " \ |
153 | "run bootscript; " \ | |
154 | "else " \ | |
f28154b5 | 155 | "if run loadimage; then " \ |
938080dc JL |
156 | "run mmcboot; " \ |
157 | "else run netboot; " \ | |
158 | "fi; " \ | |
159 | "fi; " \ | |
160 | "else run netboot; fi" | |
161 | ||
162 | #define CONFIG_ARP_TIMEOUT 200UL | |
163 | ||
164 | /* Miscellaneous configurable options */ | |
165 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
938080dc | 166 | #define CONFIG_AUTO_COMPLETE |
e0df5353 | 167 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
938080dc | 168 | |
938080dc JL |
169 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
170 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
171 | ||
172 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
173 | #define CONFIG_SYS_MEMTEST_END 0x70010000 | |
174 | ||
175 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
176 | ||
938080dc JL |
177 | #define CONFIG_CMDLINE_EDITING |
178 | ||
938080dc JL |
179 | /* Physical Memory Map */ |
180 | #define CONFIG_NR_DRAM_BANKS 2 | |
31c832f9 MV |
181 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
182 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) | |
183 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
184 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) | |
185 | #define PHYS_SDRAM_SIZE (gd->ram_size) | |
938080dc JL |
186 | |
187 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
188 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
189 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
190 | ||
191 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
192 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
193 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
194 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
195 | ||
196 | /* FLASH and environment organization */ | |
197 | #define CONFIG_SYS_NO_FLASH | |
198 | ||
199 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
200 | #define CONFIG_ENV_SIZE (8 * 1024) | |
201 | #define CONFIG_ENV_IS_IN_MMC | |
202 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
203 | ||
f92e4e6c SB |
204 | #define CONFIG_CMD_SATA |
205 | #ifdef CONFIG_CMD_SATA | |
206 | #define CONFIG_DWC_AHSATA | |
207 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
208 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
209 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
210 | #define CONFIG_LBA48 | |
211 | #define CONFIG_LIBATA | |
212 | #endif | |
213 | ||
f714b0a9 FE |
214 | /* Framebuffer and LCD */ |
215 | #define CONFIG_PREBOOT | |
695af9ab | 216 | #define CONFIG_VIDEO_IPUV3 |
f714b0a9 FE |
217 | #define CONFIG_CFB_CONSOLE |
218 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
3e077370 SB |
219 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
220 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
f714b0a9 FE |
221 | #define CONFIG_VIDEO_BMP_RLE8 |
222 | #define CONFIG_SPLASH_SCREEN | |
223 | #define CONFIG_BMP_16BPP | |
224 | #define CONFIG_VIDEO_LOGO | |
c606608a | 225 | #define CONFIG_IPUV3_CLK 200000000 |
f714b0a9 | 226 | |
938080dc | 227 | #endif /* __CONFIG_H */ |