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854d489e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
57cd681b | 2 | /* |
854d489e | 3 | * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ |
57cd681b | 4 | * |
57cd681b TR |
5 | * Based on "omap4.dtsi" |
6 | */ | |
7 | ||
8 | #include "dra7.dtsi" | |
9 | ||
10 | / { | |
11 | compatible = "ti,dra722", "ti,dra72", "ti,dra7"; | |
12 | ||
57cd681b TR |
13 | pmu { |
14 | compatible = "arm,cortex-a15-pmu"; | |
15 | interrupt-parent = <&wakeupgen>; | |
16 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | |
17 | }; | |
18 | }; | |
19 | ||
20 | &dss { | |
21 | reg = <0x58000000 0x80>, | |
22 | <0x58004054 0x4>, | |
23 | <0x58004300 0x20>; | |
24 | reg-names = "dss", "pll1_clkctrl", "pll1"; | |
25 | ||
26 | clocks = <&dss_dss_clk>, | |
27 | <&dss_video1_clk>; | |
28 | clock-names = "fck", "video1_clk"; | |
29 | }; | |
4ddaa6ce LV |
30 | |
31 | &mailbox5 { | |
f8ae3e60 | 32 | mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { |
4ddaa6ce LV |
33 | ti,mbox-tx = <6 2 2>; |
34 | ti,mbox-rx = <4 2 2>; | |
35 | status = "disabled"; | |
36 | }; | |
f8ae3e60 | 37 | mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { |
4ddaa6ce LV |
38 | ti,mbox-tx = <5 2 2>; |
39 | ti,mbox-rx = <1 2 2>; | |
40 | status = "disabled"; | |
41 | }; | |
42 | }; | |
43 | ||
44 | &mailbox6 { | |
f8ae3e60 | 45 | mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { |
4ddaa6ce LV |
46 | ti,mbox-tx = <6 2 2>; |
47 | ti,mbox-rx = <4 2 2>; | |
48 | status = "disabled"; | |
49 | }; | |
50 | }; |