[u-boot.git] / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <[email protected]>
 *
 * minor modifications by
 * Wolfgang Denk <[email protected]>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

void board_reset(void);

/*
 * To provide an interface to detect CPU number for boards that support
 * more then one CPU, we implement the "weak" default functions here.
 *
 * Returns CPU number
 */
int __get_cpu_num(void)
{
	return NA_OR_UNKNOWN_CPU;
}
int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));

#if defined(CONFIG_405GP) || \
    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)

#define PCI_ASYNC

static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
    !defined(CONFIG_405) && !defined(CONFIG_405EX)
static int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned long val;

	mfsdr(sdr_xcr, val);
	return (val & 0x80000000);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(sdr_pci0, val);
	return (val & 0x80000000);
#endif
}
#endif

#if defined(CONFIG_405EP)
#define I2C_BOOTROM

static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#else
	unsigned long val;

	mfsdr(sdr_sdcs, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif

#if defined(CONFIG_440GX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (16 bits)",
	"EBC (8 bits)",
	"EBC (32 bits)",
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"Reserved",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
#endif

#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define SDR0_PINSTP_SHIFT	30
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"NAND (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"PCI",
	"PCI",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",	/* A8 */
	"I2C (Addr 0x52)",	/* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_460SX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (32 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",      /* A8 */
	"I2C (Addr 0x52)",      /* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
#endif

#if defined(CONFIG_405EZ)
#define SDR0_PINSTP_SHIFT	28
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"SPI (fast)",
	"NAND (512 page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (32 bits)",
	"I2C (Addr 0x50)",
	"NAND (2K page, 5 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (16 bits)",
	"Reserved",
	"NAND (2K page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"NAND (512 page, 3 addr cycle)",
	"I2C (Addr 0x50)",
	"SPI (slow)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
				 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
#endif

#if defined(CONFIG_405EX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",
	"EBC (8 bits)",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
{
	unsigned long val;

	mfsdr(SDR_PINSTP, val);
	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
}
#endif /* SDR0_PINSTP_SHIFT */


#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	 * reset.
	 */
	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
	mtdcr (cpc0_sys0, sys0);
	mtdcr (cpc0_sys1, sys1);
	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
	mtspr (dbcr0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];

#if !defined(CONFIG_IOP480)
	char addstr[64] = "";
	sys_info_t sys_info;
	int cpu_num;

	cpu_num = get_cpu_num();
	if (cpu_num >= 0)
		printf("CPU%d:  ", cpu_num);
	else
		puts("CPU:   ");

	get_sys_info(&sys_info);

#if defined(CONFIG_XILINX_440)
	puts("IBM PowerPC 4");
#else
	puts("AMCC PowerPC 4");
#endif

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
    defined(CONFIG_405EX)
	puts("05");
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	puts("60");
#else
	puts("40");
#endif
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

	case PVR_405EZ_RA:
		puts("EZ Rev. A");
		break;

	case PVR_405EX1_RA:
		puts("EX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RA:
		puts("EX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EX1_RC:
		puts("EX Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RC:
		puts("EX Rev. C");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RC:
		puts("EXr Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RC:
		puts("EXr Rev. C");
		strcpy(addstr, "No Security support");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(cpc0_strp0),
					mfdcr(cpc0_strp1) );
		}
		break;

	case PVR_440GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_440GX_RA:
		puts("GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("EP Rev. B");
		break;

	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
		puts("EP Rev. C");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("GR Rev. A");
		break;

	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
		puts("GR Rev. B");
		break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */

#ifdef CONFIG_440EPX
	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("EPx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("EPx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440EPX */

#ifdef CONFIG_440GRX
	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("GRx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("GRx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440GRX */

	case PVR_440SP_6_RAB:
		puts("SP Rev. A/B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RAB:
		puts("SP Rev. A/B");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SP_6_RC:
		puts("SP Rev. C");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RC:
		puts("SP Rev. C");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RA:
		puts("SPe Rev. A");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RA:
		puts("SPe Rev. A");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RB:
		puts("SPe Rev. B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RB:
		puts("SPe Rev. B");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_460EX_RA:
		puts("EX Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460EX_SE_RA:
		puts("EX Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460GT_RA:
		puts("GT Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460GT_SE_RA:
		puts("GT Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460SX_RA:
		puts("SX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460SX_RA_V1:
		puts("SX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_460GX_RA:
		puts("GX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460GX_RA_V1:
		puts("GX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_VIRTEX5:
		puts("x5 VIRTEX5");
		break;

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
		sys_info.freqPLB / 1000000,
		get_OPB_freq() / 1000000,
		sys_info.freqEBC / 1000000);

	if (addstr[0] != 0)
		printf("       %s\n", addstr);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif	/* I2C_BOOTROM */
#if defined(SDR0_PINSTP_SHIFT)
	printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
#endif	/* SDR0_PINSTP_SHIFT */

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	putc('\n');
#endif

#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
	printf ("       16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
	printf ("       32 kB I-Cache 32 kB D-Cache");
#else
	printf ("       16 kB I-Cache %d kB D-Cache",
		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */

#if defined(CONFIG_IOP480)
	printf ("PLX IOP480 (PVR=%08x)", pvr);
	printf (" at %s MHz:", strmhz(buf, clock));
	printf (" %u kB I-Cache", 4);
	printf (" %u kB D-Cache", 2);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}

int ppc440spe_revB() {
	unsigned int pvr;

	pvr = get_pvr();
	if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
		return 1;
	else
		return 0;
}

/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_BOARD_RESET)
	board_reset();
#else
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
	/*
	 * Initiate system reset in debug control register DBCR
	 */
	mtspr(dbcr0, 0x30000000);
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */

	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
#else
	return (66000000);
#endif

}


#if defined(CONFIG_WATCHDOG)
void watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(tsr, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */

/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_PPC4xx_EMAC)
	ppc_4xx_eth_initialize(bis);
#endif
	return 0;
}
Commit	Line	Data
c609719b	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
c609719b WD	25	* CPU specific code
	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <[email protected]>
	29	*
	30	* minor modifications by
	31	* Wolfgang Denk <[email protected]>
	32	*/
	33
	34	#include <common.h>
	35	#include <watchdog.h>
	36	#include <command.h>
	37	#include <asm/cache.h>
	38	#include <ppc4xx.h>
25a85906	39	#include <netdev.h>
c609719b	40
d87080b7	41	DECLARE_GLOBAL_DATA_PTR;
d87080b7	42
f3443867	43	void board_reset(void);
f3443867	44
c9c11d75 AG	45	/*
	46	* To provide an interface to detect CPU number for boards that support
	47	* more then one CPU, we implement the "weak" default functions here.
	48	*
	49	* Returns CPU number
	50	*/
	51	int __get_cpu_num(void)
	52	{
	53	return NA_OR_UNKNOWN_CPU;
	54	}
	55	int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
	56
887e2ec9 SR	57	#if defined(CONFIG_405GP) \|\| \
	58	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
	59	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
6e7fb6ea SR	60
	61	#define PCI_ASYNC
	62
c7f69c34	63	static int pci_async_enabled(void)
6e7fb6ea SR	64	{
	65	#if defined(CONFIG_405GP)
	66	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	67	#endif
3d9569b2 SR	68
887e2ec9	69	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	70	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	71	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
6e7fb6ea SR	72	unsigned long val;
6e7fb6ea SR	73
7481266e	74	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	75	return (val & SDR0_SDSTP1_PAME_MASK);
	76	#endif
	77	}
	78	#endif
	79
dbbd1257 SR	80	#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
dbbd1257 SR	81	!defined(CONFIG_405) && !defined(CONFIG_405EX)
c7f69c34	82	static int pci_arbiter_enabled(void)
6e7fb6ea SR	83	{
	84	#if defined(CONFIG_405GP)
	85	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
	86	#endif
3d9569b2	87
6e7fb6ea SR	88	#if defined(CONFIG_405EP)
6e7fb6ea SR	89	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	90	#endif
	91
	92	#if defined(CONFIG_440GP)
6e7fb6ea SR	93	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
	94	#endif
	95
7372ca68	96	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
6e7fb6ea	97	unsigned long val;
3d9569b2	98
7372ca68 SR	99	mfsdr(sdr_xcr, val);
	100	return (val & 0x80000000);
	101	#endif
	102	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	103	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	104	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
7372ca68 SR	105	unsigned long val;
	106
	107	mfsdr(sdr_pci0, val);
	108	return (val & 0x80000000);
3d9569b2	109	#endif
6e7fb6ea SR	110	}
	111	#endif
	112
c7f69c34	113	#if defined(CONFIG_405EP)
6e7fb6ea	114	#define I2C_BOOTROM
3d9569b2	115
c7f69c34	116	static int i2c_bootrom_enabled(void)
6e7fb6ea SR	117	{
	118	#if defined(CONFIG_405EP)
	119	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
887e2ec9	120	#else
6e7fb6ea SR	121	unsigned long val;
	122
	123	mfsdr(sdr_sdcs, val);
	124	return (val & SDR0_SDCS_SDD);
	125	#endif
	126	}
90e6f41c	127	#endif
887e2ec9 SR	128
	129	#if defined(CONFIG_440GX)
	130	#define SDR0_PINSTP_SHIFT 29
	131	static char *bootstrap_str[] = {
	132	"EBC (16 bits)",
	133	"EBC (8 bits)",
	134	"EBC (32 bits)",
	135	"EBC (8 bits)",
	136	"PCI",
	137	"I2C (Addr 0x54)",
	138	"Reserved",
	139	"I2C (Addr 0x50)",
	140	};
e3cbe1f9	141	static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
887e2ec9 SR	142	#endif
	143
	144	#if defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	145	#define SDR0_PINSTP_SHIFT 30
	146	static char *bootstrap_str[] = {
	147	"EBC (8 bits)",
	148	"PCI",
	149	"I2C (Addr 0x54)",
	150	"I2C (Addr 0x50)",
	151	};
e3cbe1f9	152	static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
887e2ec9 SR	153	#endif
	154
	155	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	156	#define SDR0_PINSTP_SHIFT 29
	157	static char *bootstrap_str[] = {
	158	"EBC (8 bits)",
	159	"PCI",
	160	"NAND (8 bits)",
	161	"EBC (16 bits)",
	162	"EBC (16 bits)",
	163	"I2C (Addr 0x54)",
	164	"PCI",
	165	"I2C (Addr 0x52)",
	166	};
e3cbe1f9	167	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	168	#endif
	169
	170	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	171	#define SDR0_PINSTP_SHIFT 29
	172	static char *bootstrap_str[] = {
	173	"EBC (8 bits)",
	174	"EBC (16 bits)",
	175	"EBC (16 bits)",
	176	"NAND (8 bits)",
	177	"PCI",
	178	"I2C (Addr 0x54)",
	179	"PCI",
	180	"I2C (Addr 0x52)",
	181	};
e3cbe1f9	182	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	183	#endif
887e2ec9 SR	184
2801b2d2 SR	185	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	186	#define SDR0_PINSTP_SHIFT 29
	187	static char *bootstrap_str[] = {
	188	"EBC (8 bits)",
	189	"EBC (16 bits)",
	190	"PCI",
	191	"PCI",
	192	"EBC (16 bits)",
	193	"NAND (8 bits)",
	194	"I2C (Addr 0x54)", /* A8 */
	195	"I2C (Addr 0x52)", /* A4 */
	196	};
	197	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
	198	#endif
	199
7d307936 FK	200	#if defined(CONFIG_460SX)
	201	#define SDR0_PINSTP_SHIFT 29
	202	static char *bootstrap_str[] = {
	203	"EBC (8 bits)",
	204	"EBC (16 bits)",
	205	"EBC (32 bits)",
	206	"NAND (8 bits)",
	207	"I2C (Addr 0x54)", /* A8 */
	208	"I2C (Addr 0x52)", /* A4 */
	209	};
	210	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
	211	#endif
	212
90e6f41c SR	213	#if defined(CONFIG_405EZ)
	214	#define SDR0_PINSTP_SHIFT 28
	215	static char *bootstrap_str[] = {
	216	"EBC (8 bits)",
	217	"SPI (fast)",
	218	"NAND (512 page, 4 addr cycle)",
	219	"I2C (Addr 0x50)",
	220	"EBC (32 bits)",
	221	"I2C (Addr 0x50)",
	222	"NAND (2K page, 5 addr cycle)",
	223	"I2C (Addr 0x50)",
	224	"EBC (16 bits)",
	225	"Reserved",
	226	"NAND (2K page, 4 addr cycle)",
	227	"I2C (Addr 0x50)",
	228	"NAND (512 page, 3 addr cycle)",
	229	"I2C (Addr 0x50)",
	230	"SPI (slow)",
	231	"I2C (Addr 0x50)",
	232	};
e3cbe1f9 BM	233	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
e3cbe1f9 BM	234	'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
90e6f41c SR	235	#endif
90e6f41c SR	236
dbbd1257 SR	237	#if defined(CONFIG_405EX)
	238	#define SDR0_PINSTP_SHIFT 29
	239	static char *bootstrap_str[] = {
	240	"EBC (8 bits)",
	241	"EBC (16 bits)",
	242	"EBC (16 bits)",
	243	"NAND (8 bits)",
	244	"NAND (8 bits)",
	245	"I2C (Addr 0x54)",
	246	"EBC (8 bits)",
	247	"I2C (Addr 0x52)",
	248	};
	249	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
	250	#endif
	251
887e2ec9 SR	252	#if defined(SDR0_PINSTP_SHIFT)
	253	static int bootstrap_option(void)
	254	{
	255	unsigned long val;
	256
90e6f41c SR	257	mfsdr(SDR_PINSTP, val);
90e6f41c SR	258	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
887e2ec9 SR	259	}
887e2ec9 SR	260	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2 SR	261
3d9569b2 SR	262
c609719b	263	#if defined(CONFIG_440)
c7f69c34 SR	264	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
	265	{
	266	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	267	* reset.
	268	*/
	269	mtdcr (cntrl0, mfdcr (cntrl0) \| 0x80000000); /* Set SWE */
	270	mtdcr (cpc0_sys0, sys0);
	271	mtdcr (cpc0_sys1, sys1);
	272	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
	273	mtspr (dbcr0, 0x20000000); /* Reset the chip */
	274
	275	return 1;
	276	}
c609719b WD	277	#endif
c609719b WD	278
c609719b WD	279
	280	int checkcpu (void)
	281	{
3d9569b2	282	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2	283	uint pvr = get_pvr();
c609719b WD	284	ulong clock = gd->cpu_clk;
c609719b WD	285	char buf[32];
c609719b	286
3d9569b2	287	#if !defined(CONFIG_IOP480)
ba999c53	288	char addstr[64] = "";
3d9569b2	289	sys_info_t sys_info;
c9c11d75	290	int cpu_num;
c609719b	291
c9c11d75 AG	292	cpu_num = get_cpu_num();
	293	if (cpu_num >= 0)
	294	printf("CPU%d: ", cpu_num);
	295	else
	296	puts("CPU: ");
c609719b WD	297
	298	get_sys_info(&sys_info);
	299
d865fd09 RR	300	#if defined(CONFIG_XILINX_440)
	301	puts("IBM PowerPC 4");
	302	#else
3d9569b2	303	puts("AMCC PowerPC 4");
d865fd09	304	#endif
3d9569b2	305
e01bd218	306	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
dbbd1257 SR	307	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257 SR	308	defined(CONFIG_405EX)
3d9569b2	309	puts("05");
b867d705	310	#endif
3d9569b2	311	#if defined(CONFIG_440)
2801b2d2 SR	312	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	313	puts("60");
	314	#else
3d9569b2	315	puts("40");
2801b2d2	316	#endif
c609719b	317	#endif
3d9569b2	318
c609719b WD	319	switch (pvr) {
c609719b WD	320	case PVR_405GP_RB:
3d9569b2	321	puts("GP Rev. B");
c609719b	322	break;
3d9569b2	323
c609719b	324	case PVR_405GP_RC:
3d9569b2	325	puts("GP Rev. C");
c609719b	326	break;
3d9569b2	327
c609719b	328	case PVR_405GP_RD:
3d9569b2	329	puts("GP Rev. D");
c609719b	330	break;
3d9569b2	331
42dfe7a1	332	#ifdef CONFIG_405GP
3d9569b2 SR	333	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
3d9569b2 SR	334	puts("GP Rev. E");
c609719b WD	335	break;
c609719b WD	336	#endif
3d9569b2	337
c609719b	338	case PVR_405CR_RA:
3d9569b2	339	puts("CR Rev. A");
c609719b	340	break;
3d9569b2	341
c609719b	342	case PVR_405CR_RB:
3d9569b2	343	puts("CR Rev. B");
c609719b	344	break;
c609719b	345
3d9569b2 SR	346	#ifdef CONFIG_405CR
	347	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
	348	puts("CR Rev. C");
	349	break;
c609719b WD	350	#endif
c609719b WD	351
3d9569b2 SR	352	case PVR_405GPR_RB:
	353	puts("GPr Rev. B");
	354	break;
c609719b	355
3d9569b2 SR	356	case PVR_405EP_RB:
	357	puts("EP Rev. B");
	358	break;
c609719b	359
e01bd218 SR	360	case PVR_405EZ_RA:
	361	puts("EZ Rev. A");
	362	break;
	363
dbbd1257 SR	364	case PVR_405EX1_RA:
	365	puts("EX Rev. A");
	366	strcpy(addstr, "Security support");
	367	break;
	368
	369	case PVR_405EX2_RA:
	370	puts("EX Rev. A");
	371	strcpy(addstr, "No Security support");
	372	break;
	373
	374	case PVR_405EXR1_RA:
	375	puts("EXr Rev. A");
	376	strcpy(addstr, "Security support");
	377	break;
	378
	379	case PVR_405EXR2_RA:
	380	puts("EXr Rev. A");
	381	strcpy(addstr, "No Security support");
	382	break;
	383
70fab190 SR	384	case PVR_405EX1_RC:
	385	puts("EX Rev. C");
	386	strcpy(addstr, "Security support");
	387	break;
	388
	389	case PVR_405EX2_RC:
	390	puts("EX Rev. C");
	391	strcpy(addstr, "No Security support");
	392	break;
	393
	394	case PVR_405EXR1_RC:
	395	puts("EXr Rev. C");
	396	strcpy(addstr, "Security support");
	397	break;
	398
	399	case PVR_405EXR2_RC:
	400	puts("EXr Rev. C");
	401	strcpy(addstr, "No Security support");
	402	break;
	403
c609719b	404	#if defined(CONFIG_440)
8bde7f77	405	case PVR_440GP_RB:
c157d8e2	406	puts("GP Rev. B");
4d816774 WD	407	/* See errata 1.12: CHIP_4 */
	408	if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) \|\|
	409	(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
	410	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	411	"Resetting chip ...\n");
	412	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
	413	do_chip_reset ( mfdcr(cpc0_strp0),
	414	mfdcr(cpc0_strp1) );
	415	}
c609719b	416	break;
3d9569b2	417
8bde7f77	418	case PVR_440GP_RC:
c157d8e2	419	puts("GP Rev. C");
ba56f625	420	break;
3d9569b2	421
ba56f625	422	case PVR_440GX_RA:
c157d8e2	423	puts("GX Rev. A");
ba56f625	424	break;
3d9569b2	425
ba56f625	426	case PVR_440GX_RB:
c157d8e2	427	puts("GX Rev. B");
c609719b	428	break;
3d9569b2	429
0a7c5391	430	case PVR_440GX_RC:
c157d8e2	431	puts("GX Rev. C");
0a7c5391	432	break;
3d9569b2	433
57275b69 SR	434	case PVR_440GX_RF:
	435	puts("GX Rev. F");
	436	break;
3d9569b2	437
c157d8e2 SR	438	case PVR_440EP_RA:
	439	puts("EP Rev. A");
	440	break;
3d9569b2	441
9a8d82fd SR	442	#ifdef CONFIG_440EP
9a8d82fd SR	443	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2 SR	444	puts("EP Rev. B");
c157d8e2 SR	445	break;
512f8d5d SR	446
	447	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
	448	puts("EP Rev. C");
	449	break;
9a8d82fd	450	#endif /* CONFIG_440EP */
3d9569b2	451
9a8d82fd SR	452	#ifdef CONFIG_440GR
	453	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
	454	puts("GR Rev. A");
	455	break;
512f8d5d	456
5770a1e4	457	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
512f8d5d SR	458	puts("GR Rev. B");
512f8d5d SR	459	break;
9a8d82fd	460	#endif /* CONFIG_440GR */
3d9569b2 SR	461	#endif /* CONFIG_440 */
3d9569b2 SR	462
2902fada SR	463	#ifdef CONFIG_440EPX
2902fada SR	464	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	465	puts("EPx Rev. A");
edf0b543 SR	466	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	467	break;
887e2ec9 SR	468
2902fada	469	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	470	puts("EPx Rev. A");
edf0b543 SR	471	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	472	break;
2902fada	473	#endif /* CONFIG_440EPX */
887e2ec9	474
2902fada SR	475	#ifdef CONFIG_440GRX
2902fada SR	476	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	477	puts("GRx Rev. A");
edf0b543 SR	478	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	479	break;
887e2ec9 SR	480
2902fada	481	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	482	puts("GRx Rev. A");
edf0b543 SR	483	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	484	break;
2902fada	485	#endif /* CONFIG_440GRX */
887e2ec9	486
95981778 SR	487	case PVR_440SP_6_RAB:
	488	puts("SP Rev. A/B");
	489	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	490	break;
6e7fb6ea SR	491
95981778 SR	492	case PVR_440SP_RAB:
	493	puts("SP Rev. A/B");
	494	strcpy(addstr, "No RAID 6 support");
	495	break;
	496
	497	case PVR_440SP_6_RC:
	498	puts("SP Rev. C");
	499	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	500	break;
6e7fb6ea SR	501
e732faec SR	502	case PVR_440SP_RC:
e732faec SR	503	puts("SP Rev. C");
95981778 SR	504	strcpy(addstr, "No RAID 6 support");
	505	break;
	506
	507	case PVR_440SPe_6_RA:
	508	puts("SPe Rev. A");
	509	strcpy(addstr, "RAID 6 support");
e732faec SR	510	break;
e732faec SR	511
6c5879f3	512	case PVR_440SPe_RA:
fe84b48a	513	puts("SPe Rev. A");
95981778 SR	514	strcpy(addstr, "No RAID 6 support");
	515	break;
	516
	517	case PVR_440SPe_6_RB:
	518	puts("SPe Rev. B");
	519	strcpy(addstr, "RAID 6 support");
6c5879f3	520	break;
fe84b48a	521
6c5879f3	522	case PVR_440SPe_RB:
fe84b48a	523	puts("SPe Rev. B");
95981778	524	strcpy(addstr, "No RAID 6 support");
6c5879f3	525	break;
fe84b48a	526
2801b2d2 SR	527	case PVR_460EX_RA:
	528	puts("EX Rev. A");
	529	strcpy(addstr, "No Security/Kasumi support");
	530	break;
	531
	532	case PVR_460EX_SE_RA:
	533	puts("EX Rev. A");
	534	strcpy(addstr, "Security/Kasumi support");
	535	break;
	536
	537	case PVR_460GT_RA:
	538	puts("GT Rev. A");
	539	strcpy(addstr, "No Security/Kasumi support");
	540	break;
	541
	542	case PVR_460GT_SE_RA:
	543	puts("GT Rev. A");
	544	strcpy(addstr, "Security/Kasumi support");
	545	break;
	546
7d307936 FK	547	case PVR_460SX_RA:
	548	puts("SX Rev. A");
	549	strcpy(addstr, "Security support");
	550	break;
	551
	552	case PVR_460SX_RA_V1:
	553	puts("SX Rev. A");
	554	strcpy(addstr, "No Security support");
	555	break;
	556
	557	case PVR_460GX_RA:
	558	puts("GX Rev. A");
	559	strcpy(addstr, "Security support");
	560	break;
	561
	562	case PVR_460GX_RA_V1:
	563	puts("GX Rev. A");
	564	strcpy(addstr, "No Security support");
	565	break;
	566
d865fd09 RR	567	case PVR_VIRTEX5:
	568	puts("x5 VIRTEX5");
	569	break;
	570
8bde7f77	571	default:
17f50f22	572	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	573	break;
c609719b WD	574	}
3d9569b2 SR	575
3d9569b2 SR	576	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
e01bd218 SR	577	sys_info.freqPLB / 1000000,
e01bd218 SR	578	get_OPB_freq() / 1000000,
dbbd1257	579	sys_info.freqEBC / 1000000);
3d9569b2	580
edf0b543 SR	581	if (addstr[0] != 0)
	582	printf(" %s\n", addstr);
	583
6e7fb6ea SR	584	#if defined(I2C_BOOTROM)
6e7fb6ea SR	585	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
90e6f41c	586	#endif /* I2C_BOOTROM */
887e2ec9	587	#if defined(SDR0_PINSTP_SHIFT)
e3cbe1f9	588	printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
887e2ec9	589	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
ba999c53	590	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2	591
dbbd1257	592	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
6e7fb6ea	593	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	594	#endif
3d9569b2 SR	595
6e7fb6ea SR	596	#if defined(PCI_ASYNC)
6e7fb6ea SR	597	if (pci_async_enabled()) {
3d9569b2 SR	598	printf (", PCI async ext clock used");
	599	} else {
	600	printf (", PCI sync clock at %lu MHz",
	601	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	602	}
c609719b	603	#endif
3d9569b2	604
dbbd1257	605	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
3d9569b2 SR	606	putc('\n');
	607	#endif
	608
dbbd1257	609	#if defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| defined(CONFIG_405EX)
3d9569b2 SR	610	printf (" 16 kB I-Cache 16 kB D-Cache");
	611	#elif defined(CONFIG_440)
	612	printf (" 32 kB I-Cache 32 kB D-Cache");
	613	#else
	614	printf (" 16 kB I-Cache %d kB D-Cache",
	615	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
	616	#endif
	617	#endif /* !defined(CONFIG_IOP480) */
	618
	619	#if defined(CONFIG_IOP480)
	620	printf ("PLX IOP480 (PVR=%08x)", pvr);
	621	printf (" at %s MHz:", strmhz(buf, clock));
	622	printf (" %u kB I-Cache", 4);
	623	printf (" %u kB D-Cache", 2);
	624	#endif
	625
	626	#endif /* !defined(CONFIG_405) */
	627
	628	putc ('\n');
c609719b WD	629
	630	return 0;
	631	}
	632
692519b1 RJ	633	int ppc440spe_revB() {
	634	unsigned int pvr;
	635
	636	pvr = get_pvr();
5a5c5698	637	if ((pvr == PVR_440SPe_6_RB) \|\| (pvr == PVR_440SPe_RB))
692519b1 RJ	638	return 1;
	639	else
	640	return 0;
	641	}
c609719b WD	642
	643	/* ------------------------------------------------------------------------- */
	644
8bde7f77	645	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b	646	{
1f94d162 SR	647	#if defined(CONFIG_BOARD_RESET)
1f94d162 SR	648	board_reset();
1729b92c	649	#else
6d0f6bcf JCPV	650	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
6d0f6bcf JCPV	651	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
c157d8e2	652	#else
8bde7f77 WD	653	/*
	654	* Initiate system reset in debug control register DBCR
	655	*/
f3443867	656	mtspr(dbcr0, 0x30000000);
6d0f6bcf	657	#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
f3443867	658	#endif /* defined(CONFIG_BOARD_RESET) */
c157d8e2	659
c609719b WD	660	return 1;
	661	}
	662
c609719b WD	663
	664	/*
	665	* Get timebase clock frequency
	666	*/
	667	unsigned long get_tbclk (void)
	668	{
3d9569b2	669	#if !defined(CONFIG_IOP480)
c609719b WD	670	sys_info_t sys_info;
	671
	672	get_sys_info(&sys_info);
	673	return (sys_info.freqProcessor);
c609719b	674	#else
3d9569b2	675	return (66000000);
c609719b WD	676	#endif
	677
	678	}
	679
	680
	681	#if defined(CONFIG_WATCHDOG)
c7f69c34	682	void watchdog_reset(void)
c609719b WD	683	{
	684	int re_enable = disable_interrupts();
	685	reset_4xx_watchdog();
	686	if (re_enable) enable_interrupts();
	687	}
	688
c7f69c34	689	void reset_4xx_watchdog(void)
c609719b WD	690	{
	691	/*
	692	* Clear TSR(WIS) bit
	693	*/
	694	mtspr(tsr, 0x40000000);
	695	}
	696	#endif /* CONFIG_WATCHDOG */
25a85906 BW	697
	698	/*
	699	* Initializes on-chip ethernet controllers.
	700	* to override, implement board_eth_init()
	701	*/
	702	int cpu_eth_init(bd_t *bis)
	703	{
	704	#if defined(CONFIG_PPC4xx_EMAC)
	705	ppc_4xx_eth_initialize(bis);
	706	#endif
	707	return 0;
	708	}
	709