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| Commit | Line | Data |
|---|---|---|
| 53633a89 TR |
1 | Atmel system registers |
| 2 | ||
| 3 | Chipid required properties: | |
| 4 | - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" | |
| 5 | - reg : Should contain registers location and length | |
| 6 | ||
| 7 | PIT Timer required properties: | |
| 8 | - compatible: Should be "atmel,at91sam9260-pit" | |
| 9 | - reg: Should contain registers location and length | |
| 10 | - interrupts: Should contain interrupt for the PIT which is the IRQ line | |
| 11 | shared across all System Controller members. | |
| 12 | ||
| 13 | PIT64B Timer required properties: | |
| 14 | - compatible: Should be "microchip,sam9x60-pit64b" | |
| 15 | - reg: Should contain registers location and length | |
| 16 | - interrupts: Should contain interrupt for PIT64B timer | |
| 17 | - clocks: Should contain the available clock sources for PIT64B timer. | |
| 18 | ||
| 19 | System Timer (ST) required properties: | |
| 20 | - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" | |
| 21 | - reg: Should contain registers location and length | |
| 22 | - interrupts: Should contain interrupt for the ST which is the IRQ line | |
| 23 | shared across all System Controller members. | |
| 24 | - clocks: phandle to input clock. | |
| 25 | Its subnodes can be: | |
| 26 | - watchdog: compatible should be "atmel,at91rm9200-wdt" | |
| 27 | ||
| 28 | RAMC SDRAM/DDR Controller required properties: | |
| 29 | - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" | |
| 30 | "atmel,at91sam9260-sdramc", | |
| 31 | "atmel,at91sam9g45-ddramc", | |
| 32 | "atmel,sama5d3-ddramc", | |
| 33 | "microchip,sam9x60-ddramc", | |
| 34 | "microchip,sama7g5-uddrc" | |
| 35 | - reg: Should contain registers location and length | |
| 36 | ||
| 37 | Examples: | |
| 38 | ||
| 39 | ramc0: ramc@ffffe800 { | |
| 40 | compatible = "atmel,at91sam9g45-ddramc"; | |
| 41 | reg = <0xffffe800 0x200>; | |
| 42 | }; | |
| 43 | ||
| 53633a89 TR |
44 | Security Module (SECUMOD) |
| 45 | ||
| 46 | The Security Module macrocell provides all necessary secure functions to avoid | |
| 47 | voltage, temperature, frequency and mechanical attacks on the chip. It also | |
| 48 | embeds secure memories that can be scrambled. | |
| 49 | ||
| 50 | The Security Module also offers the PIOBU pins which can be used as GPIO pins. | |
| 51 | Note that they maintain their voltage during Backup/Self-refresh. | |
| 52 | ||
| 53 | required properties: | |
| 54 | - compatible: Should be "atmel,<chip>-secumod", "syscon". | |
| 55 | <chip> can be "sama5d2". | |
| 56 | - reg: Should contain registers location and length | |
| 57 | - gpio-controller: Marks the port as GPIO controller. | |
| 58 | - #gpio-cells: There are 2. The pin number is the | |
| 59 | first, the second represents additional | |
| 60 | parameters such as GPIO_ACTIVE_HIGH/LOW. | |
| 61 | ||
| 62 | ||
| 63 | secumod@fc040000 { | |
| 64 | compatible = "atmel,sama5d2-secumod", "syscon"; | |
| 65 | reg = <0xfc040000 0x100>; | |
| 66 | gpio-controller; | |
| 67 | #gpio-cells = <2>; | |
| 68 | }; |