projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 49249e13 PA |
2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
| 2703e640 | 4 | * Copyright 2020 NXP |
| 49249e13 PA |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * P010 RDB board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| 74fa22ed | 16 | #include <asm/config_mpc85xx.h> |
| 49249e13 PA |
17 | |
| 18 | #ifdef CONFIG_SDCARD | |
| c9e1f588 YZ |
19 | #define CONFIG_SPL_FLUSH_IMAGE |
| 20 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
21 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 22 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 23 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) | |
| 24 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
| 25 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| 26 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) | |
| 27 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
28 | #ifdef CONFIG_SPL_BUILD |
| 29 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 30 | #endif | |
| 49249e13 PA |
31 | #endif |
| 32 | ||
| 33 | #ifdef CONFIG_SPIFLASH | |
| bef18454 | 34 | #ifdef CONFIG_NXP_ESBC |
| 49249e13 | 35 | #define CONFIG_RAMBOOT_SPIFLASH |
| 84e0fb40 | 36 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| c9e1f588 | 37 | #else |
| c9e1f588 YZ |
38 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 39 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 40 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
41 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 42 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 43 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) | |
| 44 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
| 45 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| 46 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) | |
| 47 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
48 | #ifdef CONFIG_SPL_BUILD |
| 49 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 50 | #endif | |
| 51 | #endif | |
| 49249e13 PA |
52 | #endif |
| 53 | ||
| 88718be3 | 54 | #ifdef CONFIG_MTD_RAW_NAND |
| bef18454 | 55 | #ifdef CONFIG_NXP_ESBC |
| 0fa934d2 | 56 | #define CONFIG_SPL_INIT_MINIMAL |
| 0fa934d2 PK |
57 | #define CONFIG_SPL_FLUSH_IMAGE |
| 58 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 59 | ||
| 0fa934d2 PK |
60 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 61 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
| 62 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
| e222b1f3 | 63 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
| 0fa934d2 PK |
64 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 65 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 66 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
| c9e1f588 | 67 | #else |
| c9e1f588 | 68 | #ifdef CONFIG_TPL_BUILD |
| c9e1f588 | 69 | #define CONFIG_SPL_FLUSH_IMAGE |
| c9e1f588 | 70 | #define CONFIG_SPL_NAND_INIT |
| c9e1f588 YZ |
71 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 72 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| c9e1f588 YZ |
73 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 74 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) | |
| 75 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
| 76 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| 77 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
| 78 | #elif defined(CONFIG_SPL_BUILD) | |
| 79 | #define CONFIG_SPL_INIT_MINIMAL | |
| c9e1f588 YZ |
80 | #define CONFIG_SPL_NAND_MINIMAL |
| 81 | #define CONFIG_SPL_FLUSH_IMAGE | |
| c9e1f588 YZ |
82 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 83 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
| 84 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 | |
| 85 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 | |
| 86 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
| 87 | #endif | |
| 88 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 89 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 90 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 | 91 | #endif |
| d793e5a8 | 92 | #endif |
| 2f439e80 RG |
93 | |
| 94 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
| 95 | #define CONFIG_RAMBOOT_NAND | |
| e222b1f3 | 96 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 2f439e80 RG |
97 | #endif |
| 98 | ||
| 49249e13 PA |
99 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 100 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 101 | #endif | |
| 102 | ||
| a6d6812a | 103 | #ifdef CONFIG_TPL_BUILD |
| 1b465187 | 104 | #define CONFIG_SYS_MONITOR_BASE 0xD0001000 |
| a6d6812a | 105 | #elif defined(CONFIG_SPL_BUILD) |
| 0fa934d2 PK |
106 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 107 | #else | |
| 108 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 49249e13 PA |
109 | #endif |
| 110 | ||
| 111 | /* High Level Configuration Options */ | |
| 49249e13 | 112 | |
| 49249e13 | 113 | #if defined(CONFIG_PCI) |
| b38eaec5 RD |
114 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 115 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 49249e13 | 116 | |
| 49249e13 PA |
117 | /* |
| 118 | * PCI Windows | |
| 119 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 120 | */ | |
| 121 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 49249e13 PA |
122 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 123 | #ifdef CONFIG_PHYS_64BIT | |
| 49249e13 PA |
124 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 125 | #else | |
| 49249e13 PA |
126 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 127 | #endif | |
| 49249e13 | 128 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 49249e13 PA |
129 | #ifdef CONFIG_PHYS_64BIT |
| 130 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 131 | #else | |
| 132 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
| 133 | #endif | |
| 134 | ||
| 135 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 9de7c76b HZ |
136 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 137 | #ifdef CONFIG_PHYS_64BIT | |
| 138 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 139 | #else | |
| 140 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 141 | #endif | |
| 142 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 143 | #ifdef CONFIG_PHYS_64BIT | |
| 144 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 145 | #else | |
| 146 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 147 | #endif | |
| 148 | ||
| 49249e13 | 149 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 49249e13 PA |
150 | #endif |
| 151 | ||
| 49249e13 PA |
152 | #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ |
| 153 | ||
| 49249e13 PA |
154 | #define CONFIG_HWCONFIG |
| 155 | /* | |
| 156 | * These can be toggled for performance analysis, otherwise use default. | |
| 157 | */ | |
| 158 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 159 | #define CONFIG_BTB /* toggle branch predition */ | |
| 160 | ||
| 49249e13 PA |
161 | |
| 162 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 163 | ||
| 49249e13 | 164 | /* DDR Setup */ |
| 1ba62f10 | 165 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 49249e13 PA |
166 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 167 | #define SPD_EEPROM_ADDRESS 0x52 | |
| 168 | ||
| 169 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 170 | ||
| 171 | #ifndef __ASSEMBLY__ | |
| 172 | extern unsigned long get_sdram_size(void); | |
| 173 | #endif | |
| 174 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
| 175 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 176 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 177 | ||
| 178 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 179 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 180 | ||
| 181 | /* DDR3 Controller Settings */ | |
| 182 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
| 183 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 184 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 185 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 186 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 187 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 188 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 49249e13 PA |
189 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 190 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 191 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 192 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| e512c50b SL |
193 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ |
| 194 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 | |
| 49249e13 PA |
195 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
| 196 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 197 | ||
| e512c50b SL |
198 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
| 199 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 | |
| 200 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 | |
| 49249e13 PA |
201 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF |
| 202 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| e512c50b SL |
203 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
| 204 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 | |
| 49249e13 | 205 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 |
| e512c50b | 206 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
| 49249e13 PA |
207 | |
| 208 | /* settings for DDR3 at 667MT/s */ | |
| 209 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 | |
| 210 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 | |
| 211 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 | |
| 212 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD | |
| 213 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 | |
| 214 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 | |
| 215 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 | |
| 216 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 | |
| 217 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 | |
| 218 | ||
| 219 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 220 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 221 | ||
| d793e5a8 | 222 | /* Don't relocate CCSRBAR while in NAND_SPL */ |
| 0fa934d2 | 223 | #ifdef CONFIG_SPL_BUILD |
| d793e5a8 DD |
224 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 225 | #endif | |
| 226 | ||
| 49249e13 PA |
227 | /* |
| 228 | * Memory map | |
| 229 | * | |
| 230 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
| 231 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
| 232 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 233 | * | |
| 234 | * Localbus non-cacheable | |
| 235 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
| 236 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
| 237 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 238 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 239 | */ | |
| 240 | ||
| 49249e13 PA |
241 | /* |
| 242 | * IFC Definitions | |
| 243 | */ | |
| 244 | /* NOR Flash on IFC */ | |
| 0fa934d2 | 245 | |
| 49249e13 PA |
246 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
| 247 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
| 248 | ||
| 249 | #ifdef CONFIG_PHYS_64BIT | |
| 250 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 251 | #else | |
| 252 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 253 | #endif | |
| 254 | ||
| 255 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 256 | CSPR_PORT_SIZE_16 | \ | |
| 257 | CSPR_MSEL_NOR | \ | |
| 258 | CSPR_V) | |
| 259 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
| 260 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
| 261 | /* NOR Flash Timing Params */ | |
| 262 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
| 263 | FTIM0_NOR_TEADC(0x5) | \ | |
| 264 | FTIM0_NOR_TEAHC(0x5) | |
| 265 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
| 266 | FTIM1_NOR_TRAD_NOR(0x0f) | |
| 267 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
| 268 | FTIM2_NOR_TCH(0x4) | \ | |
| 269 | FTIM2_NOR_TWP(0x1c) | |
| 270 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 271 | ||
| 272 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 273 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 274 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 275 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 276 | ||
| 277 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 278 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 279 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 280 | ||
| 281 | /* CFI for NOR Flash */ | |
| 49249e13 | 282 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 49249e13 PA |
283 | |
| 284 | /* NAND Flash on IFC */ | |
| 285 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 286 | #ifdef CONFIG_PHYS_64BIT | |
| 287 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
| 288 | #else | |
| 289 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 290 | #endif | |
| 291 | ||
| ac688078 | 292 | #define CONFIG_MTD_PARTITION |
| ac688078 | 293 | |
| 49249e13 PA |
294 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 295 | | CSPR_PORT_SIZE_8 \ | |
| 296 | | CSPR_MSEL_NAND \ | |
| 297 | | CSPR_V) | |
| 298 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| e512c50b | 299 | |
| 7601686c | 300 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
301 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 302 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 303 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 304 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
| 305 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
| 306 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
| 307 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
| e512c50b | 308 | |
| 7601686c | 309 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
310 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 311 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 312 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 313 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 314 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 315 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
| 316 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ | |
| e512c50b | 317 | #endif |
| 49249e13 | 318 | |
| d793e5a8 DD |
319 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 320 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| d793e5a8 | 321 | |
| 7601686c | 322 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
323 | /* NAND Flash Timing Params */ |
| 324 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
| 325 | FTIM0_NAND_TWP(0x0C) | \ | |
| 326 | FTIM0_NAND_TWCHT(0x04) | \ | |
| 327 | FTIM0_NAND_TWH(0x05) | |
| 328 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
| 329 | FTIM1_NAND_TWBE(0x1d) | \ | |
| 330 | FTIM1_NAND_TRR(0x07) | \ | |
| 331 | FTIM1_NAND_TRP(0x0c) | |
| 332 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
| 333 | FTIM2_NAND_TREH(0x05) | \ | |
| 334 | FTIM2_NAND_TWHRE(0x0f) | |
| 335 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
| 336 | ||
| 7601686c | 337 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
338 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
| 339 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 340 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ | |
| 341 | FTIM0_NAND_TWP(0x18) | \ | |
| 342 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 343 | FTIM0_NAND_TWH(0x0a)) | |
| 344 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ | |
| 345 | FTIM1_NAND_TWBE(0x39) | \ | |
| 346 | FTIM1_NAND_TRR(0x0e) | \ | |
| 347 | FTIM1_NAND_TRP(0x18)) | |
| 348 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 349 | FTIM2_NAND_TREH(0x0a) | \ | |
| 350 | FTIM2_NAND_TWHRE(0x1e)) | |
| 351 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 352 | #endif | |
| 353 | ||
| 49249e13 PA |
354 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 355 | ||
| 356 | /* Set up IFC registers for boot location NOR/NAND */ | |
| 88718be3 | 357 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) |
| d793e5a8 DD |
358 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 359 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 360 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 361 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 362 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 363 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 364 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 365 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 366 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 367 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 368 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 369 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 370 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 371 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 372 | #else | |
| 49249e13 PA |
373 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 374 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 375 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 376 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 377 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 378 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 379 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 380 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 381 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 382 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 383 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 384 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 385 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 386 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| d793e5a8 DD |
387 | #endif |
| 388 | ||
| 49249e13 PA |
389 | /* CPLD on IFC */ |
| 390 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
| 391 | ||
| 392 | #ifdef CONFIG_PHYS_64BIT | |
| 393 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
| 394 | #else | |
| 395 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
| 396 | #endif | |
| 397 | ||
| 398 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
| 399 | | CSPR_PORT_SIZE_8 \ | |
| 400 | | CSPR_MSEL_GPCM \ | |
| 401 | | CSPR_V) | |
| 402 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
| 403 | #define CONFIG_SYS_CSOR3 0x0 | |
| 404 | /* CPLD Timing parameters for IFC CS3 */ | |
| 405 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 406 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 407 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 408 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 409 | FTIM1_GPCM_TRAD(0x1f)) | |
| 410 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 411 | FTIM2_GPCM_TCH(0x8) | \ |
| 49249e13 PA |
412 | FTIM2_GPCM_TWP(0x1f)) |
| 413 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 49249e13 | 414 | |
| 76c9aaf5 AB |
415 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ |
| 416 | defined(CONFIG_RAMBOOT_NAND) | |
| 49249e13 | 417 | #define CONFIG_SYS_RAMBOOT |
| 49249e13 PA |
418 | #else |
| 419 | #undef CONFIG_SYS_RAMBOOT | |
| 420 | #endif | |
| 421 | ||
| 74fa22ed | 422 | #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
| 50c76367 | 423 | #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) |
| 74fa22ed PK |
424 | #define CONFIG_A003399_NOR_WORKAROUND |
| 425 | #endif | |
| 426 | #endif | |
| 427 | ||
| 49249e13 PA |
428 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 429 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| b39d1213 | 430 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
| 49249e13 | 431 | |
| b39d1213 | 432 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 49249e13 PA |
433 | - GENERATED_GBL_DATA_SIZE) |
| 434 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 435 | ||
| 9307cbab | 436 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 49249e13 | 437 | |
| c9e1f588 YZ |
438 | /* |
| 439 | * Config the L2 Cache as L2 SRAM | |
| 440 | */ | |
| 441 | #if defined(CONFIG_SPL_BUILD) | |
| 442 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
| 443 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 444 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 445 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 446 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 447 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 448 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
| c9e1f588 YZ |
449 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) |
| 450 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) | |
| 451 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) | |
| 88718be3 | 452 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 YZ |
453 | #ifdef CONFIG_TPL_BUILD |
| 454 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 455 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 456 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 457 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 458 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 459 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 460 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 461 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 462 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| 463 | #else | |
| 464 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 465 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 466 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 467 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 468 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) | |
| 469 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 470 | #endif | |
| 471 | #endif | |
| 472 | #endif | |
| 473 | ||
| 49249e13 | 474 | /* Serial Port */ |
| 49249e13 | 475 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 49249e13 PA |
476 | #define CONFIG_SYS_NS16550_SERIAL |
| 477 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 478 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| c9e1f588 | 479 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| d793e5a8 DD |
480 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 481 | #endif | |
| 49249e13 | 482 | |
| 49249e13 PA |
483 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 484 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 485 | ||
| 486 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 487 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 488 | ||
| 00f792e0 | 489 | /* I2C */ |
| ad89da0c | 490 | #define I2C_PCA9557_ADDR1 0x18 |
| e512c50b | 491 | #define I2C_PCA9557_ADDR2 0x19 |
| ad89da0c | 492 | #define I2C_PCA9557_BUS_NUM 0 |
| 49249e13 PA |
493 | |
| 494 | /* I2C EEPROM */ | |
| 7601686c | 495 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
496 | #ifdef CONFIG_ID_EEPROM |
| 497 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 498 | #endif | |
| e512c50b SL |
499 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 500 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ | |
| 501 | #endif | |
| 49249e13 | 502 | /* enable read and write access to EEPROM */ |
| 49249e13 PA |
503 | |
| 504 | /* RTC */ | |
| 505 | #define CONFIG_RTC_PT7C4338 | |
| 506 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 507 | ||
| 49249e13 PA |
508 | /* |
| 509 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
| 510 | * used for SLIC | |
| 511 | */ | |
| 88718be3 | 512 | #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) |
| 49249e13 | 513 | /* eSPI - Enhanced SPI */ |
| d793e5a8 | 514 | #endif |
| 49249e13 PA |
515 | |
| 516 | #if defined(CONFIG_TSEC_ENET) | |
| 49249e13 PA |
517 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 518 | #define CONFIG_TSEC1 1 | |
| 519 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 520 | #define CONFIG_TSEC2 1 | |
| 521 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 522 | #define CONFIG_TSEC3 1 | |
| 523 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 524 | ||
| 525 | #define TSEC1_PHY_ADDR 1 | |
| 526 | #define TSEC2_PHY_ADDR 0 | |
| 527 | #define TSEC3_PHY_ADDR 2 | |
| 528 | ||
| 529 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 530 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 531 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 532 | ||
| 533 | #define TSEC1_PHYIDX 0 | |
| 534 | #define TSEC2_PHYIDX 0 | |
| 535 | #define TSEC3_PHYIDX 0 | |
| 536 | ||
| 537 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 538 | ||
| 49249e13 PA |
539 | /* TBI PHY configuration for SGMII mode */ |
| 540 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 541 | TBICR_PHY_RESET \ | |
| 542 | | TBICR_ANEG_ENABLE \ | |
| 543 | | TBICR_FULL_DUPLEX \ | |
| 544 | | TBICR_SPEED1_SET \ | |
| 545 | ) | |
| 546 | ||
| 547 | #endif /* CONFIG_TSEC_ENET */ | |
| 548 | ||
| 49249e13 | 549 | /* SATA */ |
| 9760b274 | 550 | #define CONFIG_FSL_SATA_V2 |
| 49249e13 PA |
551 | |
| 552 | #ifdef CONFIG_FSL_SATA | |
| 553 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 554 | #define CONFIG_SATA1 | |
| 555 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 556 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 557 | #define CONFIG_SATA2 | |
| 558 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 559 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 560 | ||
| 49249e13 PA |
561 | #define CONFIG_LBA48 |
| 562 | #endif /* #ifdef CONFIG_FSL_SATA */ | |
| 563 | ||
| 49249e13 | 564 | #ifdef CONFIG_MMC |
| 49249e13 PA |
565 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 566 | #endif | |
| 567 | ||
| 568 | #define CONFIG_HAS_FSL_DR_USB | |
| 569 | ||
| 570 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 8850c5d5 | 571 | #ifdef CONFIG_USB_EHCI_HCD |
| 49249e13 | 572 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 49249e13 PA |
573 | #endif |
| 574 | #endif | |
| 575 | ||
| 576 | /* | |
| 577 | * Environment | |
| 578 | */ | |
| c9e1f588 | 579 | #if defined(CONFIG_SDCARD) |
| 4394d0c2 | 580 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 88718be3 | 581 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 | 582 | #ifdef CONFIG_TPL_BUILD |
| a09fea1d | 583 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| c9e1f588 | 584 | #else |
| 7601686c | 585 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| e512c50b | 586 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ |
| 7601686c | 587 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
588 | #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ |
| 589 | #endif | |
| c9e1f588 | 590 | #endif |
| 49249e13 PA |
591 | #endif |
| 592 | ||
| 593 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 594 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 595 | ||
| 8850c5d5 | 596 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ |
| 49249e13 | 597 | || defined(CONFIG_FSL_SATA) |
| 49249e13 PA |
598 | #endif |
| 599 | ||
| 600 | /* | |
| 601 | * Miscellaneous configurable options | |
| 602 | */ | |
| 49249e13 | 603 | |
| 49249e13 PA |
604 | /* |
| 605 | * For booting Linux, the board info and command line data | |
| 606 | * have to be in the first 64 MB of memory, since this is | |
| 607 | * the maximum mapped by the Linux kernel during initialization. | |
| 608 | */ | |
| 609 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 610 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 611 | ||
| 49249e13 PA |
612 | /* |
| 613 | * Environment Configuration | |
| 614 | */ | |
| 615 | ||
| 616 | #if defined(CONFIG_TSEC_ENET) | |
| 617 | #define CONFIG_HAS_ETH0 | |
| 618 | #define CONFIG_HAS_ETH1 | |
| 619 | #define CONFIG_HAS_ETH2 | |
| 620 | #endif | |
| 621 | ||
| 8b3637c6 | 622 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 623 | #define CONFIG_BOOTFILE "uImage" |
| 49249e13 PA |
624 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
| 625 | ||
| 49249e13 | 626 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 5368c55d | 627 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
| 49249e13 | 628 | "netdev=eth0\0" \ |
| 5368c55d | 629 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 49249e13 PA |
630 | "loadaddr=1000000\0" \ |
| 631 | "consoledev=ttyS0\0" \ | |
| 632 | "ramdiskaddr=2000000\0" \ | |
| 633 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 634 | "fdtaddr=1e00000\0" \ |
| 49249e13 PA |
635 | "fdtfile=p1010rdb.dtb\0" \ |
| 636 | "bdev=sda1\0" \ | |
| 637 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
| 638 | "othbootargs=ramdisk_size=600000\0" \ | |
| 639 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
| 640 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 641 | "usb start;" \ | |
| 642 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 643 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 644 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 645 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 646 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 647 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 648 | "usb start;" \ | |
| 649 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 650 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 651 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| e512c50b SL |
652 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
| 653 | CONFIG_BOOTMODE | |
| 654 | ||
| 7601686c | 655 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| e512c50b SL |
656 | #define CONFIG_BOOTMODE \ |
| 657 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
| 658 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ | |
| 659 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
| 660 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ | |
| 661 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ | |
| 662 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" | |
| 663 | ||
| 7601686c | 664 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
665 | #define CONFIG_BOOTMODE \ |
| 666 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
| 667 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ | |
| 668 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
| 669 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ | |
| 670 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ | |
| 671 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ | |
| 672 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ | |
| 673 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ | |
| 674 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ | |
| 675 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" | |
| 676 | #endif | |
| 49249e13 | 677 | |
| 2f439e80 | 678 | #include <asm/fsl_secure_boot.h> |
| 2f439e80 | 679 | |
| 49249e13 | 680 | #endif /* __CONFIG_H */ |