[u-boot.git] / include / configs / ls1043aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 */

#ifndef __LS1043AQDS_H__
#define __LS1043AQDS_H__

#include "ls1043a_common.h"

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()

#define CONFIG_LAYERSCAPE_NS_ACCESS

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR		0x1
#define RGMII_PHY2_ADDR		0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* PHY address on QSGMII riser card on slot 1 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
/* PHY address on QSGMII riser card on slot 2 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif

/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#endif

/* SATA */
#define CONFIG_SCSI_AHCI_PLAT

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0

#define CONFIG_SYS_SATA				AHCI_BASE_ADDR

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
#endif

#if defined(CONFIG_TFABOOT) || \
	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_SD_QSPI		0xff
#define QIXIS_LBMAP_QSPI		0xff
#define QIXIS_RCW_SRC_NAND		0x106
#define QIXIS_RCW_SRC_SD		0x040
#define QIXIS_RCW_SRC_QSPI		0x045
#define QIXIS_RST_CTL_RESET		0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
					FTIM0_GPCM_TEADC(0x20) | \
					FTIM0_GPCM_TEAHC(0x10))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif
#endif

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC
#define I2C_MUX_CH5			0xD
#define I2C_MUX_CH7			0xF

#define I2C_MUX_CH_VOL_MONITOR 0xa

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3

#define CONFIG_VID_FLS_ENV		"ls1043aqds_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1043AQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */

#include <asm/fsl_secure_boot.h>

#endif /* __LS1043AQDS_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
02b5d2ed SX	2	/*
02b5d2ed SX	3	* Copyright 2015 Freescale Semiconductor, Inc.
02b5d2ed SX	4	*/
	5
	6	#ifndef __LS1043AQDS_H__
	7	#define __LS1043AQDS_H__
	8
	9	#include "ls1043a_common.h"
	10
02b5d2ed SX	11	#ifndef __ASSEMBLY__
02b5d2ed SX	12	unsigned long get_board_sys_clk(void);
02b5d2ed SX	13	#endif
02b5d2ed SX	14
581ff00b	15	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
02b5d2ed	16
02b5d2ed SX	17	#define CONFIG_LAYERSCAPE_NS_ACCESS
	18
	19	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	20	/* Physical Memory Map */
	21	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
02b5d2ed	22
02b5d2ed SX	23	#define SPD_EEPROM_ADDRESS 0x51
	24	#define CONFIG_SYS_SPD_BUS_NUM 0
	25
02b5d2ed	26	#ifdef CONFIG_DDR_ECC
02b5d2ed SX	27	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	28	#endif
	29
02b5d2ed	30	#ifdef CONFIG_SYS_DPAA_FMAN
02b5d2ed SX	31	#define RGMII_PHY1_ADDR 0x1
	32	#define RGMII_PHY2_ADDR 0x2
	33	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	34	#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
	35	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	36	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	37	/* PHY address on QSGMII riser card on slot 1 */
	38	#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
	39	#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
	40	#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
	41	#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
	42	/* PHY address on QSGMII riser card on slot 2 */
	43	#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
	44	#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
	45	#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
	46	#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
	47	#endif
	48
2970e14f WS	49	/* LPUART */
	50	#ifdef CONFIG_LPUART
	51	#define CONFIG_LPUART_32B_REG
	52	#endif
	53
989c5f0a	54	/* SATA */
989c5f0a	55	#define CONFIG_SCSI_AHCI_PLAT
989c5f0a	56
ceded371	57	/* EEPROM */
ceded371 WS	58	#define CONFIG_SYS_I2C_EEPROM_NXID
ceded371 WS	59	#define CONFIG_SYS_EEPROM_BUS_NUM 0
ceded371	60
989c5f0a TY	61	#define CONFIG_SYS_SATA AHCI_BASE_ADDR
	62
	63	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	64	#define CONFIG_SYS_SCSI_MAX_LUN 1
	65	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	66	CONFIG_SYS_SCSI_MAX_LUN)
	67
02b5d2ed SX	68	/*
	69	* IFC Definitions
	70	*/
b0f20caf	71	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
02b5d2ed SX	72	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	73	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	74	CSPR_PORT_SIZE_16 \| \
	75	CSPR_MSEL_NOR \| \
	76	CSPR_V)
	77	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	78	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	79	+ 0x8000000) \| \
	80	CSPR_PORT_SIZE_16 \| \
	81	CSPR_MSEL_NOR \| \
	82	CSPR_V)
	83	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	84
	85	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	86	CSOR_NOR_TRHZ_80)
	87	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	88	FTIM0_NOR_TEADC(0x5) \| \
	89	FTIM0_NOR_TEAHC(0x5))
	90	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	91	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	92	FTIM1_NOR_TSEQRAD_NOR(0x13))
	93	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	94	FTIM2_NOR_TCH(0x4) \| \
	95	FTIM2_NOR_TWPH(0xe) \| \
	96	FTIM2_NOR_TWP(0x1c))
	97	#define CONFIG_SYS_NOR_FTIM3 0
	98
1b245d9a	99	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
02b5d2ed SX	100	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	101	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	102	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	103
	104	#define CONFIG_SYS_FLASH_EMPTY_INFO
	105	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	106	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	107
	108	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	109	#define CONFIG_SYS_WRITE_SWAPPED_DATA
	110
	111	/*
	112	* NAND Flash Definitions
	113	*/
02b5d2ed SX	114
	115	#define CONFIG_SYS_NAND_BASE 0x7e800000
	116	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	117
	118	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	119
	120	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	121	\| CSPR_PORT_SIZE_8 \
	122	\| CSPR_MSEL_NAND \
	123	\| CSPR_V)
	124	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	125	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	126	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	127	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	128	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	129	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	130	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	131	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	132
02b5d2ed SX	133	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	134	FTIM0_NAND_TWP(0x18) \| \
	135	FTIM0_NAND_TWCHT(0x7) \| \
	136	FTIM0_NAND_TWH(0xa))
	137	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	138	FTIM1_NAND_TWBE(0x39) \| \
	139	FTIM1_NAND_TRR(0xe) \| \
	140	FTIM1_NAND_TRP(0x18))
	141	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	142	FTIM2_NAND_TREH(0xa) \| \
	143	FTIM2_NAND_TWHRE(0x1e))
	144	#define CONFIG_SYS_NAND_FTIM3 0x0
	145
	146	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	147	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	148	#define CONFIG_MTD_NAND_VERIFY_WRITE
166ef1e9	149	#endif
02b5d2ed SX	150
	151	#ifdef CONFIG_NAND_BOOT
	152	#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
02b5d2ed SX	153	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
	154	#endif
	155
8aa6b17a RB	156	#if defined(CONFIG_TFABOOT) \|\| \
8aa6b17a RB	157	defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
166ef1e9	158	#define CONFIG_QIXIS_I2C_ACCESS
166ef1e9 GQ	159	#endif
166ef1e9 GQ	160
02b5d2ed SX	161	/*
	162	* QIXIS Definitions
	163	*/
	164	#define CONFIG_FSL_QIXIS
	165
	166	#ifdef CONFIG_FSL_QIXIS
	167	#define QIXIS_BASE 0x7fb00000
	168	#define QIXIS_BASE_PHYS QIXIS_BASE
	169	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	170	#define QIXIS_LBMAP_SWITCH 6
	171	#define QIXIS_LBMAP_MASK 0x0f
	172	#define QIXIS_LBMAP_SHIFT 0
	173	#define QIXIS_LBMAP_DFLTBANK 0x00
	174	#define QIXIS_LBMAP_ALTBANK 0x04
ee2a4eee GQ	175	#define QIXIS_LBMAP_NAND 0x09
ee2a4eee GQ	176	#define QIXIS_LBMAP_SD 0x00
166ef1e9	177	#define QIXIS_LBMAP_SD_QSPI 0xff
b0f20caf	178	#define QIXIS_LBMAP_QSPI 0xff
ee2a4eee GQ	179	#define QIXIS_RCW_SRC_NAND 0x106
ee2a4eee GQ	180	#define QIXIS_RCW_SRC_SD 0x040
b0f20caf	181	#define QIXIS_RCW_SRC_QSPI 0x045
a4b7d68c	182	#define QIXIS_RST_CTL_RESET 0x41
02b5d2ed SX	183	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	184	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	185	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	186
	187	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	188	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	189	CSPR_PORT_SIZE_8 \| \
	190	CSPR_MSEL_GPCM \| \
	191	CSPR_V)
	192	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	193	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	194	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	195	CSOR_NOR_TRHZ_80)
	196
	197	/*
	198	* QIXIS Timing parameters for IFC GPCM
	199	*/
	200	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) \| \
	201	FTIM0_GPCM_TEADC(0x20) \| \
	202	FTIM0_GPCM_TEAHC(0x10))
	203	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) \| \
	204	FTIM1_GPCM_TRAD(0x1f))
	205	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) \| \
	206	FTIM2_GPCM_TCH(0x8) \| \
	207	FTIM2_GPCM_TWP(0xf0))
	208	#define CONFIG_SYS_FPGA_FTIM3 0x0
	209	#endif
	210
8aa6b17a RB	211	#ifdef CONFIG_TFABOOT
	212	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	213	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	214	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	215	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	216	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	217	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	218	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	219	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	220	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	221	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	222	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	223	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	224	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	225	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	226	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	227	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	228	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	229	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	230	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	231	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	232	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	233	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	234	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	235	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	236	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	237	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	238	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	239	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	240	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	241	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	242	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	243	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	244	#else
02b5d2ed SX	245	#ifdef CONFIG_NAND_BOOT
	246	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	247	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	248	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	249	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	250	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	251	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	252	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	253	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	254	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	255	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	256	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	257	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	258	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	259	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	260	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	261	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	262	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	263	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	264	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	265	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	266	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	267	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	268	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	269	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	270	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	271	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	272	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	273	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	274	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	275	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	276	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	277	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	278	#else
	279	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	280	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	281	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	282	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	283	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	284	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	285	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	286	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	287	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	288	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	289	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	290	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	291	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	292	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	293	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	294	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	295	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	296	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	297	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	298	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	299	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	300	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	301	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	302	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	303	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	304	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	305	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	306	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	307	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	308	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
309	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
310	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
311	#endif
8aa6b17a	312	#endif
02b5d2ed SX	313
	314	/*
	315	* I2C bus multiplexer
	316	*/
	317	#define I2C_MUX_PCA_ADDR_PRI 0x77
	318	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
	319	#define I2C_RETIMER_ADDR 0x18
	320	#define I2C_MUX_CH_DEFAULT 0x8
	321	#define I2C_MUX_CH_CH7301 0xC
	322	#define I2C_MUX_CH5 0xD
	323	#define I2C_MUX_CH7 0xF
	324
	325	#define I2C_MUX_CH_VOL_MONITOR 0xa
	326
	327	/* Voltage monitor on channel 2*/
	328	#define I2C_VOL_MONITOR_ADDR 0x40
	329	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	330	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	331	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
	332
	333	#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
	334	#ifndef CONFIG_SPL_BUILD
	335	#define CONFIG_VID
	336	#endif
	337	#define CONFIG_VOL_MONITOR_IR36021_SET
	338	#define CONFIG_VOL_MONITOR_INA220
	339	/* The lowest and highest voltage allowed for LS1043AQDS */
	340	#define VDD_MV_MIN 819
	341	#define VDD_MV_MAX 1212
	342
	343	/*
	344	* Miscellaneous configurable options
	345	*/
02b5d2ed	346
02b5d2ed SX	347	#define CONFIG_SYS_INIT_SP_OFFSET \
	348	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	349
	350	#ifdef CONFIG_SPL_BUILD
	351	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	352	#else
	353	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	354	#endif
	355
	356	/*
	357	* Environment
	358	*/
02b5d2ed	359
ef6c55a2 AB	360	#include <asm/fsl_secure_boot.h>
ef6c55a2 AB	361
02b5d2ed	362	#endif /* __LS1043AQDS_H__ */