[u-boot.git] / board / inka4x0 / inka4x0.c

/*
 * (C) Copyright 2008-2009
 * Andreas Pfefferle, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2009
 * Detlev Zundel, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, [email protected].
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, [email protected]
 *
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <asm/io.h>
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
#elif defined(CONFIG_DDR_MT46V32M16)
#include "mt46v32m16.h"
#elif defined(CONFIG_DDR_HYB25D512160BF)
#include "hyb25d512160bf.h"
#elif defined(CONFIG_DDR_K4H511638C)
#include "k4h511638c.h"
#else
#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

#if SDRAM_DDR
	/* set mode register: extended mode */
	out_be32(&sdram->mode, SDRAM_EMODE);

	/* set mode register: reset DLL */
	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
#endif

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

	/* auto refresh */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);

	/* set mode register */
	out_be32(&sdram->mode, SDRAM_MODE);

	/* normal operation */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

phys_size_t initdram (int board_type)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	volatile struct mpc5xxx_cdm     *cdm =
		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	long test1, test2;

	/* setup SDRAM chip selects */
	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
	out_be32(&mm->sdram1, 0x40000000);	/* disabled */

	/* setup config registers */
	out_be32(&sdram->config1, SDRAM_CONFIG1);
	out_be32(&sdram->config2, SDRAM_CONFIG2);

#if SDRAM_DDR
	/* set tap delay */
	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		out_be32(&mm->sdram0, 0x13 +
			 __builtin_ffs(dramsize >> 20) - 1);
	} else {
		out_be32(&mm->sdram0, 0); /* disabled */
	}

	out_be32(&mm->sdram1, dramsize); /* disabled */
#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = in_be32(&mm->sdram0) & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}
#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize;
}

int checkboard (void)
{
	puts ("Board: INKA 4X0\n");
	return 0;
}

void flash_preinit(void)
{
	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;

	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT (CS0) cannot be cleared when
	 * executing in flash.
	 */
	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
}

int misc_init_f (void)
{
	volatile struct mpc5xxx_gpio	*gpio    =
		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	volatile struct mpc5xxx_gpt	*gpt;
	char tmp[10];
	int i, br;

	i = getenv_f("brightness", tmp, sizeof(tmp));
	br = (i > 0)
		? (int) simple_strtoul (tmp, NULL, 10)
		: CONFIG_SYS_BRIGHTNESS;
	if (br > 255)
		br = 255;

	/* Initialize GPIO output pins.
	 */
	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
	for (i = 0; i <= 5; i++) {
		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
		out_be32(&gpt->emsr, 0x34);
	}

	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
	out_be32(&gpt->emsr,  0);		/* Disable */
	out_be32(&gpt->cir,   0x020000fe);
	out_be32(&gpt->pwmcr, (br << 16));
	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */

	/* Configure PSC3_6,7 as GPIO output */
	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);

	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Set LR mirror bit because it is low-active */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);

	/* Reset Coral-P graphics controller */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Enable display backlight */
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);

	/*
	 * Configure three wire serial interface to RTC (PSC1_4,
	 * PSC2_4, PSC3_4, PSC3_5)
	 */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);

	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif
Commit	Line	Data
138ff60c	1	/*
7b5611cd DZ	2	* (C) Copyright 2008-2009
	3	* Andreas Pfefferle, DENX Software Engineering, [email protected].
	4	*
	5	* (C) Copyright 2009
	6	* Detlev Zundel, DENX Software Engineering, [email protected].
138ff60c WD	7	*
	8	* (C) Copyright 2004
	9	* Mark Jonas, Freescale Semiconductor, [email protected].
	10	*
	11	* (C) Copyright 2004
	12	* Martin Krause, TQ-Systems GmbH, [email protected]
	13	*
7b5611cd DZ	14	* (C) Copyright 2003-2004
	15	* Wolfgang Denk, DENX Software Engineering, [email protected].
	16	*
1a459660	17	* SPDX-License-Identifier: GPL-2.0+
138ff60c WD	18	*/
138ff60c WD	19
e979e85f	20	#include <asm/io.h>
138ff60c WD	21	#include <common.h>
	22	#include <mpc5xxx.h>
	23	#include <pci.h>
	24
5fb6d719	25	#if defined(CONFIG_DDR_MT46V16M16)
138ff60c	26	#include "mt46v16m16-75.h"
5fb6d719	27	#elif defined(CONFIG_SDR_MT48LC16M16A2)
138ff60c	28	#include "mt48lc16m16a2-75.h"
5fb6d719 MB	29	#elif defined(CONFIG_DDR_MT46V32M16)
	30	#include "mt46v32m16.h"
	31	#elif defined(CONFIG_DDR_HYB25D512160BF)
	32	#include "hyb25d512160bf.h"
	33	#elif defined(CONFIG_DDR_K4H511638C)
	34	#include "k4h511638c.h"
	35	#else
	36	#error "INKA4x0 SDRAM: invalid chip type specified!"
138ff60c WD	37	#endif
138ff60c WD	38
6d0f6bcf	39	#ifndef CONFIG_SYS_RAMBOOT
138ff60c WD	40	static void sdram_start (int hi_addr)
138ff60c WD	41	{
2344bb8d DZ	42	volatile struct mpc5xxx_sdram *sdram =
2344bb8d DZ	43	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
138ff60c WD	44	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	45
	46	/* unlock mode register */
2344bb8d	47	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit);
138ff60c WD	48
138ff60c WD	49	/* precharge all banks */
2344bb8d	50	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	51
	52	#if SDRAM_DDR
	53	/* set mode register: extended mode */
2344bb8d	54	out_be32(&sdram->mode, SDRAM_EMODE);
138ff60c WD	55
138ff60c WD	56	/* set mode register: reset DLL */
2344bb8d	57	out_be32(&sdram->mode, SDRAM_MODE \| 0x04000000);
138ff60c WD	58	#endif
	59
	60	/* precharge all banks */
2344bb8d	61	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	62
138ff60c WD	63	/* auto refresh */
2344bb8d	64	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit);
138ff60c WD	65
138ff60c WD	66	/* set mode register */
2344bb8d	67	out_be32(&sdram->mode, SDRAM_MODE);
138ff60c WD	68
138ff60c WD	69	/* normal operation */
2344bb8d	70	out_be32(&sdram->ctrl, SDRAM_CONTROL \| hi_addr_bit);
138ff60c WD	71	}
	72	#endif
	73
	74	/*
	75	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	76	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
138ff60c WD	77	* is something else than 0x00000000.
	78	*/
	79
9973e3c6	80	phys_size_t initdram (int board_type)
138ff60c	81	{
2344bb8d DZ	82	volatile struct mpc5xxx_mmap_ctl *mm =
	83	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	84	volatile struct mpc5xxx_cdm *cdm =
	85	(struct mpc5xxx_cdm *) MPC5XXX_CDM;
	86	volatile struct mpc5xxx_sdram *sdram =
	87	(struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
138ff60c	88	ulong dramsize = 0;
6d0f6bcf	89	#ifndef CONFIG_SYS_RAMBOOT
f23cb34c	90	long test1, test2;
138ff60c WD	91
138ff60c WD	92	/* setup SDRAM chip selects */
2344bb8d DZ	93	out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
2344bb8d DZ	94	out_be32(&mm->sdram1, 0x40000000); /* disabled */
138ff60c WD	95
138ff60c WD	96	/* setup config registers */
2344bb8d DZ	97	out_be32(&sdram->config1, SDRAM_CONFIG1);
2344bb8d DZ	98	out_be32(&sdram->config2, SDRAM_CONFIG2);
138ff60c WD	99
	100	#if SDRAM_DDR
	101	/* set tap delay */
2344bb8d	102	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
138ff60c WD	103	#endif
	104
	105	/* find RAM size using SDRAM CS0 only */
	106	sdram_start(0);
6d0f6bcf	107	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c	108	sdram_start(1);
6d0f6bcf	109	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c WD	110	if (test1 > test2) {
	111	sdram_start(0);
	112	dramsize = test1;
	113	} else {
	114	dramsize = test2;
	115	}
	116
	117	/* memory smaller than 1MB is impossible */
	118	if (dramsize < (1 << 20)) {
	119	dramsize = 0;
	120	}
	121
	122	/* set SDRAM CS0 size according to the amount of RAM found */
	123	if (dramsize > 0) {
2344bb8d DZ	124	out_be32(&mm->sdram0, 0x13 +
2344bb8d DZ	125	__builtin_ffs(dramsize >> 20) - 1);
138ff60c	126	} else {
2344bb8d	127	out_be32(&mm->sdram0, 0); /* disabled */
138ff60c WD	128	}
138ff60c WD	129
2344bb8d	130	out_be32(&mm->sdram1, dramsize); /* disabled */
6d0f6bcf	131	#else /* CONFIG_SYS_RAMBOOT */
138ff60c WD	132
138ff60c WD	133	/* retrieve size of memory connected to SDRAM CS0 */
2344bb8d	134	dramsize = in_be32(&mm->sdram0) & 0xFF;
138ff60c WD	135	if (dramsize >= 0x13) {
	136	dramsize = (1 << (dramsize - 0x13)) << 20;
	137	} else {
	138	dramsize = 0;
	139	}
6d0f6bcf	140	#endif /* CONFIG_SYS_RAMBOOT */
138ff60c	141
138ff60c WD	142	return dramsize;
	143	}
	144
	145	int checkboard (void)
	146	{
08f27278	147	puts ("Board: INKA 4X0\n");
138ff60c WD	148	return 0;
	149	}
	150
	151	void flash_preinit(void)
	152	{
2344bb8d DZ	153	volatile struct mpc5xxx_lpb lpb = (struct mpc5xxx_lpb )MPC5XXX_LPB;
2344bb8d DZ	154
138ff60c WD	155	/*
	156	* Now, when we are in RAM, enable flash write
	157	* access for detection process.
2344bb8d	158	* Note that CS_BOOT (CS0) cannot be cleared when
138ff60c WD	159	* executing in flash.
138ff60c WD	160	*/
2344bb8d	161	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
138ff60c	162	}
436be29c	163
151ab83a WD	164	int misc_init_f (void)
151ab83a WD	165	{
2344bb8d DZ	166	volatile struct mpc5xxx_gpio *gpio =
	167	(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
	168	volatile struct mpc5xxx_wu_gpio *wu_gpio =
	169	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	170	volatile struct mpc5xxx_gpt *gpt;
f23cb34c	171	char tmp[10];
a0bdf49e WD	172	int i, br;
a0bdf49e WD	173
cdb74977	174	i = getenv_f("brightness", tmp, sizeof(tmp));
a0bdf49e WD	175	br = (i > 0)
a0bdf49e WD	176	? (int) simple_strtoul (tmp, NULL, 10)
6d0f6bcf	177	: CONFIG_SYS_BRIGHTNESS;
a0bdf49e WD	178	if (br > 255)
	179	br = 255;
	180
f4733a07 WD	181	/* Initialize GPIO output pins.
f4733a07 WD	182	*/
342717f7	183	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
2344bb8d DZ	184	for (i = 0; i <= 5; i++) {
	185	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (i 0x10));
	186	out_be32(&gpt->emsr, 0x34);
	187	}
f4733a07	188
a0bdf49e	189	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
2344bb8d DZ	190	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (7 0x10));
	191	out_be32(&gpt->emsr, 0); /* Disable */
	192	out_be32(&gpt->cir, 0x020000fe);
	193	out_be32(&gpt->pwmcr, (br << 16));
	194	out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
f4733a07 WD	195
f4733a07 WD	196	/* Configure PSC3_6,7 as GPIO output */
2344bb8d DZ	197	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	198	MPC5XXX_GPIO_SIMPLE_PSC3_7);
	199	setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	200	MPC5XXX_GPIO_SIMPLE_PSC3_7);
f4733a07 WD	201
f4733a07 WD	202	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
2344bb8d DZ	203	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 \|
	204	MPC5XXX_GPIO_WKUP_7 \|
	205	MPC5XXX_GPIO_WKUP_PSC3_9);
	206	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 \|
	207	MPC5XXX_GPIO_WKUP_7 \|
	208	MPC5XXX_GPIO_WKUP_PSC3_9);
f4733a07	209
342717f7	210	/* Set LR mirror bit because it is low-active */
2344bb8d DZ	211	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
	212
	213	/* Reset Coral-P graphics controller */
	214	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
	215
	216	/* Enable display backlight */
	217	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	218	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	219	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
	220	setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
e979e85f DZ	221
	222	/*
	223	* Configure three wire serial interface to RTC (PSC1_4,
	224	* PSC2_4, PSC3_4, PSC3_5)
	225	*/
	226	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	227	MPC5XXX_GPIO_WKUP_PSC2_4);
	228	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	229	MPC5XXX_GPIO_WKUP_PSC2_4);
	230	clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
	231	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 \|
	232	MPC5XXX_GPIO_SINT_PSC3_5);
	233	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 \|
	234	MPC5XXX_GPIO_SINT_PSC3_5);
	235	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
	236	clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
	237
f4733a07	238	return 0;
151ab83a WD	239	}
151ab83a WD	240
f4733a07	241	#ifdef CONFIG_PCI
436be29c WD	242	static struct pci_controller hose;
	243
	244	extern void pci_mpc5xxx_init(struct pci_controller *);
	245
	246	void pci_init_board(void)
	247	{
f4733a07	248	pci_mpc5xxx_init(&hose);
436be29c WD	249	}
436be29c WD	250	#endif