[u-boot.git] / include / configs / ls1046a_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2016 Freescale Semiconductor
 * Copyright 2019-2021 NXP
 */

#ifndef __LS1046A_COMMON_H
#define __LS1046A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_QBMAN
#define SPL_NO_FMAN
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_QSPI
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
#if defined(CONFIG_SPL_BUILD) && \
	(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define SPL_NO_MMC
#endif
#if defined(CONFIG_SPL_BUILD)		&& \
	!defined(CONFIG_SPL_FSL_LS_PPA)
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF
#define CONFIG_GICV2

#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>

/* Link Definitions */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_addr

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
#define CONFIG_SPL_STACK		0x10020000
#define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_NXP_ESBC */
#endif

#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
#define CONFIG_SPL_TARGET		"spl/u-boot-spl.pbl"
#define CONFIG_SPL_MAX_SIZE		0x1f000
#define CONFIG_SPL_STACK		0x10020000
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_WATCHDOG
#define CONFIG_SPL_I2C
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT

#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC
#define CONFIG_SPL_MAX_SIZE		0x17000		/* 90 KiB */
#define CONFIG_SPL_STACK		0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* GPIO */
#ifdef CONFIG_DM_GPIO
#ifndef CONFIG_MPC8XXX_GPIO
#define CONFIG_MPC8XXX_GPIO
#endif
#endif

/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

/* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA				AHCI_BASE_ADDR

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)
#endif

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
#endif

#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_FMAN_FW_ADDR		0x900000
#else
#ifdef CONFIG_SD_BOOT
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
 */
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_FMAN_FW_ADDR		(36 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
#endif
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(SCSI, scsi, 0) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif

#if defined(CONFIG_TARGET_LS1046AFRWY)
#define LS1046A_BOOT_SRC_AND_HDR\
	"boot_scripts=ls1046afrwy_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
#elif defined(CONFIG_TARGET_LS1046AQDS)
#define LS1046A_BOOT_SRC_AND_HDR\
	"boot_scripts=ls1046aqds_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1046aqds_bs.out\0"
#else
#define LS1046A_BOOT_SRC_AND_HDR\
	"boot_scripts=ls1046ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1046ardb_bs.out\0"
#endif
#ifndef SPL_NO_MISC
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"bootm_size=0x10000000\0"		\
	"fdt_addr=0x64f00000\0"                 \
	"kernel_addr=0x61000000\0"              \
	"scriptaddr=0x80000000\0"               \
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"         \
	"kernelheader_addr_r=0x80200000\0"      \
	"load_addr=0xa0000000\0"            \
	"kernel_addr_r=0x81000000\0"            \
	"fdt_addr_r=0x90000000\0"               \
	"ramdisk_addr_r=0xa0000000\0"           \
	"kernel_start=0x1000000\0"		\
	"kernelheader_start=0x600000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernelheader_size=0x40000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_addr_sd=0x3000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"console=ttyS0,115200\0"                \
	 CONFIG_MTDPARTS_DEFAULT "\0"		\
	BOOTENV					\
	LS1046A_BOOT_SRC_AND_HDR		\
	"scan_dev_for_boot_part="               \
		"part list ${devtype} ${devnum} devplist; "   \
		"env exists devplist || setenv devplist 1; "  \
		"for distro_bootpart in ${devplist}; do "     \
		  "if fstype ${devtype} "                  \
			"${devnum}:${distro_bootpart} "      \
			"bootfstype; then "                  \
			"run scan_dev_for_boot; "            \
		  "fi; "                                   \
		"done\0"                                   \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
			"env exists secureboot "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"	  \
	"qspi_bootcmd=echo Trying load from qspi..;"      \
		"sf probe && sf read $load_addr "         \
		"$kernel_start $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_start "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"		\
	"nand_bootcmd=echo Trying load from nand..;"      \
		"nand info; nand read $load_addr "         \
		"$kernel_start $kernel_size; env exists secureboot "	\
		"&& nand read $kernelheader_addr_r $kernelheader_start " \
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"		\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"	\
		"mmcinfo; mmc read $load_addr "		\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"

#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1046A_COMMON_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
dd02936f MH	2	/*
dd02936f MH	3	* Copyright 2016 Freescale Semiconductor
34f39ce8	4	* Copyright 2019-2021 NXP
dd02936f MH	5	*/
	6
	7	#ifndef __LS1046A_COMMON_H
	8	#define __LS1046A_COMMON_H
	9
a52ff334 SG	10	/* SPL build */
	11	#ifdef CONFIG_SPL_BUILD
	12	#define SPL_NO_QBMAN
	13	#define SPL_NO_FMAN
	14	#define SPL_NO_ENV
	15	#define SPL_NO_MISC
	16	#define SPL_NO_QSPI
	17	#define SPL_NO_USB
	18	#define SPL_NO_SATA
	19	#endif
038b965c YS	20	#if defined(CONFIG_SPL_BUILD) && \
038b965c YS	21	(defined(CONFIG_NAND_BOOT) \|\| defined(CONFIG_QSPI_BOOT))
a52ff334 SG	22	#define SPL_NO_MMC
a52ff334 SG	23	#endif
80bec96e	24	#if defined(CONFIG_SPL_BUILD) && \
80bec96e	25	!defined(CONFIG_SPL_FSL_LS_PPA)
a52ff334 SG	26	#define SPL_NO_IFC
	27	#endif
	28
dd02936f	29	#define CONFIG_REMAKE_ELF
dd02936f MH	30	#define CONFIG_GICV2
	31
	32	#include <asm/arch/config.h>
b52a0507	33	#include <asm/arch/stream_id_lsch2.h>
dd02936f MH	34
dd02936f MH	35	/* Link Definitions */
8e156bb1 RB	36	#ifdef CONFIG_TFABOOT
	37	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
	38	#else
dd02936f	39	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
8e156bb1	40	#endif
dd02936f	41
dd02936f	42	#define CONFIG_SKIP_LOWLEVEL_INIT
dd02936f MH	43
	44	#define CONFIG_VERY_BIG_RAM
	45	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	46	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	47	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	48	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
	49
3d3fe8b1	50	#define CPU_RELEASE_ADDR secondary_boot_addr
dd02936f MH	51
	52	/* Generic Timer Definitions */
	53	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	54
	55	/* Size of malloc() pool */
	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	57
	58	/* Serial Port */
dd02936f MH	59	#define CONFIG_SYS_NS16550_SERIAL
dd02936f MH	60	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	61	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
dd02936f	62
dd02936f MH	63	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	64
	65	/* SD boot SPL */
	66	#ifdef CONFIG_SD_BOOT
dd02936f MH	67	#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
	68	#define CONFIG_SPL_STACK 0x10020000
	69	#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
	70	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	71	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	72	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	73	CONFIG_SPL_BSS_MAX_SIZE)
	74	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
511fc86d	75
5536c3c9	76	#ifdef CONFIG_NXP_ESBC
511fc86d RG	77	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	78	/*
	79	* HDR would be appended at end of image and copied to DDR along
	80	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	81	* size increases then increase this size in case of secure boot as
	82	* it uses raw u-boot image instead of fit image.
	83	*/
	84	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	85	#else
	86	#define CONFIG_SYS_MONITOR_LEN 0x100000
5536c3c9	87	#endif /* ifdef CONFIG_NXP_ESBC */
dd02936f MH	88	#endif
dd02936f MH	89
038b965c YS	90	#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
038b965c YS	91	#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
038b965c YS	92	#define CONFIG_SPL_MAX_SIZE 0x1f000
	93	#define CONFIG_SPL_STACK 0x10020000
	94	#define CONFIG_SPL_PAD_TO 0x20000
	95	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	96	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	97	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	98	CONFIG_SPL_BSS_MAX_SIZE)
	99	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	100	#define CONFIG_SYS_MONITOR_LEN 0x100000
038b965c YS	101	#endif
038b965c YS	102
126fe70d SX	103	/* NAND SPL */
	104	#ifdef CONFIG_NAND_BOOT
	105	#define CONFIG_SPL_PBL_PAD
126fe70d SX	106	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	107	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	108	#define CONFIG_SPL_ENV_SUPPORT
078111b9	109	#define CONFIG_SPL_WATCHDOG
975e7cf3	110	#define CONFIG_SPL_I2C
126fe70d SX	111	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	112
	113	#define CONFIG_SPL_NAND_SUPPORT
9ca00684	114	#define CONFIG_SPL_DRIVERS_MISC
511fc86d	115	#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
126fe70d SX	116	#define CONFIG_SPL_STACK 0x1001f000
	117	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	118	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	119
	120	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	121	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	122	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	123	CONFIG_SPL_BSS_MAX_SIZE)
	124	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	125	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	126	#endif
	127
0077d711 BL	128	/* GPIO */
	129	#ifdef CONFIG_DM_GPIO
	130	#ifndef CONFIG_MPC8XXX_GPIO
	131	#define CONFIG_MPC8XXX_GPIO
	132	#endif
	133	#endif
	134
dd02936f	135	/* I2C */
2147a169	136	#if !CONFIG_IS_ENABLED(DM_I2C)
bb1165f9 BL	137	#else
	138	#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
	139	#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
	140	#endif
dd02936f	141
3098e539 HZ	142	/* PCIe */
	143	#define CONFIG_PCIE1 /* PCIE controller 1 */
	144	#define CONFIG_PCIE2 /* PCIE controller 2 */
	145	#define CONFIG_PCIE3 /* PCIE controller 3 */
	146
	147	#ifdef CONFIG_PCI
	148	#define CONFIG_PCI_SCAN_SHOW
3098e539 HZ	149	#endif
3098e539 HZ	150
f216ef25 YT	151	/* SATA */
	152	#ifndef SPL_NO_SATA
	153	#define CONFIG_SCSI_AHCI_PLAT
	154
	155	#define CONFIG_SYS_SATA AHCI_BASE_ADDR
	156
	157	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	158	#define CONFIG_SYS_SCSI_MAX_LUN 1
	159	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	160	CONFIG_SYS_SCSI_MAX_LUN)
	161	#endif
	162
dd02936f	163	/* FMan ucode */
a52ff334	164	#ifndef SPL_NO_FMAN
dd02936f MH	165	#define CONFIG_SYS_DPAA_FMAN
	166	#ifdef CONFIG_SYS_DPAA_FMAN
	167	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
a52ff334	168	#endif
dd02936f	169
8e156bb1 RB	170	#ifdef CONFIG_TFABOOT
8e156bb1 RB	171	#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
8e156bb1	172	#else
dd02936f MH	173	#ifdef CONFIG_SD_BOOT
	174	/*
	175	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	176	* about 1MB (2048 blocks), Env is stored after the image, and the env size is
8104deb2	177	* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
dd02936f	178	*/
8104deb2	179	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
126fe70d	180	#elif defined(CONFIG_QSPI_BOOT)
8104deb2	181	#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
126fe70d	182	#elif defined(CONFIG_NAND_BOOT)
752513d8	183	#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
126fe70d	184	#else
8104deb2	185	#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
dd02936f	186	#endif
8e156bb1	187	#endif
dd02936f MH	188	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	189	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	190	#endif
	191
	192	/* Miscellaneous configurable options */
	193	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
dd02936f MH	194
	195	#define CONFIG_HWCONFIG
	196	#define HWCONFIG_BUFFER_SIZE 128
	197
8de227ee QG	198	#ifndef CONFIG_SPL_BUILD
8de227ee QG	199	#define BOOT_TARGET_DEVICES(func) \
f216ef25	200	func(SCSI, scsi, 0) \
8de227ee	201	func(MMC, mmc, 0) \
f43cc402 MYK	202	func(USB, usb, 0) \
f43cc402 MYK	203	func(DHCP, dhcp, na)
8de227ee QG	204	#include <config_distro_bootcmd.h>
	205	#endif
	206
d90c7ac7 VS	207	#if defined(CONFIG_TARGET_LS1046AFRWY)
	208	#define LS1046A_BOOT_SRC_AND_HDR\
	209	"boot_scripts=ls1046afrwy_boot.scr\0" \
	210	"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
d71f65ed BL	211	#elif defined(CONFIG_TARGET_LS1046AQDS)
	212	#define LS1046A_BOOT_SRC_AND_HDR\
	213	"boot_scripts=ls1046aqds_boot.scr\0" \
	214	"boot_script_hdr=hdr_ls1046aqds_bs.out\0"
d90c7ac7 VS	215	#else
	216	#define LS1046A_BOOT_SRC_AND_HDR\
	217	"boot_scripts=ls1046ardb_boot.scr\0" \
	218	"boot_script_hdr=hdr_ls1046ardb_bs.out\0"
	219	#endif
a52ff334	220	#ifndef SPL_NO_MISC
dd02936f MH	221	/* Initial environment variables */
	222	#define CONFIG_EXTRA_ENV_SETTINGS \
	223	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
dd02936f MH	224	"ramdisk_addr=0x800000\0" \
dd02936f MH	225	"ramdisk_size=0x2000000\0" \
e9d9c2e5	226	"bootm_size=0x10000000\0" \
8de227ee	227	"fdt_addr=0x64f00000\0" \
d71f65ed	228	"kernel_addr=0x61000000\0" \
8de227ee	229	"scriptaddr=0x80000000\0" \
f7b75f8b	230	"scripthdraddr=0x80080000\0" \
8de227ee QG	231	"fdtheader_addr_r=0x80100000\0" \
	232	"kernelheader_addr_r=0x80200000\0" \
	233	"load_addr=0xa0000000\0" \
f7b75f8b	234	"kernel_addr_r=0x81000000\0" \
8de227ee QG	235	"fdt_addr_r=0x90000000\0" \
8de227ee QG	236	"ramdisk_addr_r=0xa0000000\0" \
dd02936f	237	"kernel_start=0x1000000\0" \
e735ad3c	238	"kernelheader_start=0x600000\0" \
dd02936f MH	239	"kernel_load=0xa0000000\0" \
dd02936f MH	240	"kernel_size=0x2800000\0" \
9b457cc6	241	"kernelheader_size=0x40000\0" \
aab2ef9a SL	242	"kernel_addr_sd=0x8000\0" \
aab2ef9a SL	243	"kernel_size_sd=0x14000\0" \
e735ad3c	244	"kernelhdr_addr_sd=0x3000\0" \
9b457cc6	245	"kernelhdr_size_sd=0x10\0" \
dd02936f	246	"console=ttyS0,115200\0" \
43ede0bc	247	CONFIG_MTDPARTS_DEFAULT "\0" \
8de227ee	248	BOOTENV \
d90c7ac7	249	LS1046A_BOOT_SRC_AND_HDR \
8de227ee QG	250	"scan_dev_for_boot_part=" \
	251	"part list ${devtype} ${devnum} devplist; " \
	252	"env exists devplist \|\| setenv devplist 1; " \
	253	"for distro_bootpart in ${devplist}; do " \
	254	"if fstype ${devtype} " \
	255	"${devnum}:${distro_bootpart} " \
	256	"bootfstype; then " \
	257	"run scan_dev_for_boot; " \
	258	"fi; " \
	259	"done\0" \
f7b75f8b SG	260	"boot_a_script=" \
	261	"load ${devtype} ${devnum}:${distro_bootpart} " \
	262	"${scriptaddr} ${prefix}${script}; " \
	263	"env exists secureboot && load ${devtype} " \
	264	"${devnum}:${distro_bootpart} " \
78c58082 VP	265	"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
	266	"env exists secureboot " \
	267	"&& esbc_validate ${scripthdraddr};" \
f7b75f8b	268	"source ${scriptaddr}\0" \
8de227ee QG	269	"qspi_bootcmd=echo Trying load from qspi..;" \
8de227ee QG	270	"sf probe && sf read $load_addr " \
9b457cc6 VPB	271	"$kernel_start $kernel_size; env exists secureboot " \
	272	"&& sf read $kernelheader_addr_r $kernelheader_start " \
	273	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	274	"bootm $load_addr#$board\0" \
d71f65ed BL	275	"nand_bootcmd=echo Trying load from nand..;" \
	276	"nand info; nand read $load_addr " \
	277	"$kernel_start $kernel_size; env exists secureboot " \
	278	"&& nand read $kernelheader_addr_r $kernelheader_start " \
	279	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	280	"bootm $load_addr#$board\0" \
	281	"nor_bootcmd=echo Trying load from nor..;" \
	282	"cp.b $kernel_addr $load_addr " \
	283	"$kernel_size; env exists secureboot " \
	284	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	285	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	286	"bootm $load_addr#$board\0" \
aab2ef9a SL	287	"sd_bootcmd=echo Trying load from SD ..;" \
	288	"mmcinfo; mmc read $load_addr " \
	289	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	290	"env exists secureboot && mmc read $kernelheader_addr_r " \
	291	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	292	" && esbc_validate ${kernelheader_addr_r};" \
aab2ef9a	293	"bootm $load_addr#$board\0"
8de227ee	294
a52ff334 SG	295	#endif
a52ff334 SG	296
dd02936f MH	297	/* Monitor Command Prompt */
dd02936f MH	298	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
a52ff334	299
dd02936f MH	300	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	301
	302	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	303
457e51cf SG	304	#include <asm/arch/soc.h>
457e51cf SG	305
dd02936f	306	#endif /* __LS1046A_COMMON_H */