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Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream
[u-boot.git] / drivers / adc / meson-saradc.c
CommitLineData
59beb238
NA		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Martin Blumenstingl <[email protected]>
4 * Copyright (C) 2018 BayLibre, SAS
5 * Author: Neil Armstrong <[email protected]>
6 *
7 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
8 */
9
59beb238
NA		 10#include <adc.h>
11#include <clk.h>
12#include <dm.h>
13#include <regmap.h>
14#include <errno.h>
15#include <asm/io.h>
cd93d625 16#include <linux/bitops.h>
c05ed00a 17#include <linux/delay.h>
59beb238
NA		 18#include <linux/math64.h>
19#include <linux/bitfield.h>
1e94b46f 20#include <linux/printk.h>
97ab802a 21#include <power/regulator.h>
59beb238
NA		 22
23#define MESON_SAR_ADC_REG0 0x00
24 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
25 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
26 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
27 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
28 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
29 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
30 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
31 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
32 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
33 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
34 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
35 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
36 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
37 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
38 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
39 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
40 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
41 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
42 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
43 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
44
45#define MESON_SAR_ADC_CHAN_LIST 0x04
46 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
47 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
48 (GENMASK(2, 0) << ((_chan) * 3))
49
50#define MESON_SAR_ADC_AVG_CNTL 0x08
51 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
52 (16 + ((_chan) * 2))
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
54 (GENMASK(17, 16) << ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
56 (0 + ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
58 (GENMASK(1, 0) << ((_chan) * 2))
59
60#define MESON_SAR_ADC_REG3 0x0c
61 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
62 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
63 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
64 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
65 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
66 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
67 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
68 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
69 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
70 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
71 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
72 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
73 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
74 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
75
76#define MESON_SAR_ADC_DELAY 0x10
77 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
78 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
79 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
80 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
81 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
82 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
83
84#define MESON_SAR_ADC_LAST_RD 0x14
85 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
86 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
87
88#define MESON_SAR_ADC_FIFO_RD 0x18
89 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
90 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
91
92#define MESON_SAR_ADC_AUX_SW 0x1c
93 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
94 (8 + (((_chan) - 2) * 3))
95 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
96 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
97 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
98 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
99 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
100 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
101 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
102
103#define MESON_SAR_ADC_CHAN_10_SW 0x20
104 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
105 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
120
121#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
122 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
123 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
139
140#define MESON_SAR_ADC_DELTA_10 0x28
141 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
142 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
143 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
145 #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
146 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
147 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
148 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
149
150/*
151 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
152 * and u-boot source served as reference). These only seem to be relevant on
153 * GXBB and newer.
154 */
155#define MESON_SAR_ADC_REG11 0x2c
156 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
157
158#define MESON_SAR_ADC_REG13 0x34
159 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
160
161#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
162#define MESON_SAR_ADC_TIMEOUT 100 /* ms */
163
164#define NUM_CHANNELS 8
165
166#define MILLION 1000000
167
168struct meson_saradc_data {
169 int num_bits;
170};
171
172struct meson_saradc_priv {
173 const struct meson_saradc_data *data;
174 struct regmap *regmap;
175 struct clk core_clk;
176 struct clk adc_clk;
177 bool initialized;
178 int active_channel;
179 int calibbias;
180 int calibscale;
181};
182
183static unsigned int
184meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
185{
186 u32 regval;
187
188 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
189
190 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
191}
192
193static int meson_saradc_lock(struct meson_saradc_priv *priv)
194{
195 uint val, timeout = 10000;
196
197 /* prevent BL30 from using the SAR ADC while we are using it */
198 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
199 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
200 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
201
202 /*
203 * wait until BL30 releases it's lock (so we can use the SAR ADC)
204 */
205 do {
206 udelay(1);
207 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
208 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
209
210 if (timeout < 0) {
211 printf("Timeout while waiting for BL30 unlock\n");
212 return -ETIMEDOUT;
213 }
214
215 return 0;
216}
217
218static void meson_saradc_unlock(struct meson_saradc_priv *priv)
219{
220 /* allow BL30 to use the SAR ADC again */
221 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
222 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
223}
224
225static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
226{
227 unsigned int count, tmp;
228
229 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
230 if (!meson_saradc_get_fifo_count(priv))
231 break;
232
233 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
234 }
235}
236
237static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
238{
239 int tmp;
240
241 /* use val_calib = scale * val_raw + offset calibration function */
242 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
243
244 return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
245}
246
247static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
248{
249 uint regval, timeout = 10000;
250
251 /*
252 * NOTE: we need a small delay before reading the status, otherwise
253 * the sample engine may not have started internally (which would
254 * seem to us that sampling is already finished).
255 */
256 do {
257 udelay(1);
258 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
259 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
260
261 if (timeout < 0)
262 return -ETIMEDOUT;
263
264 return 0;
265}
266
267static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
268 unsigned int channel, uint *val)
269{
270 uint regval, fifo_chan, fifo_val, count;
271 int ret;
272
273 ret = meson_saradc_wait_busy_clear(priv);
274 if (ret)
275 return ret;
276
277 count = meson_saradc_get_fifo_count(priv);
278 if (count != 1) {
279 printf("ADC FIFO has %d element(s) instead of one\n", count);
280 return -EINVAL;
281 }
282
283 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
284 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
285 if (fifo_chan != channel) {
d50b7364 286 printf("ADC FIFO entry belongs to channel %u instead of %u\n",
59beb238
NA		 287 fifo_chan, channel);
288 return -EINVAL;
289 }
290
291 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
292 fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
293 *val = meson_saradc_calib_val(priv, fifo_val);
294
295 return 0;
296}
297
298static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
299{
300 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
301 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
302 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
303
304 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
305 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
306 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
307
308 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
309 MESON_SAR_ADC_REG0_SAMPLING_START,
310 MESON_SAR_ADC_REG0_SAMPLING_START);
311}
312
313static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
314{
315 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
316 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
317
318 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
319 MESON_SAR_ADC_REG0_SAMPLING_STOP,
320 MESON_SAR_ADC_REG0_SAMPLING_STOP);
321
322 /* wait until all modules are stopped */
323 meson_saradc_wait_busy_clear(priv);
324
325 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
326 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
327}
328
329enum meson_saradc_avg_mode {
330 NO_AVERAGING = 0x0,
331 MEAN_AVERAGING = 0x1,
332 MEDIAN_AVERAGING = 0x2,
333};
334
335enum meson_saradc_num_samples {
336 ONE_SAMPLE = 0x0,
337 TWO_SAMPLES = 0x1,
338 FOUR_SAMPLES = 0x2,
339 EIGHT_SAMPLES = 0x3,
340};
341
342static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
343 unsigned int channel,
344 enum meson_saradc_avg_mode mode,
345 enum meson_saradc_num_samples samples)
346{
347 int val;
348
349 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
350 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
351 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
352 val);
353
354 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
355 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
356 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
357}
358
359static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
360 unsigned int channel)
361{
362 uint regval;
363
364 /*
365 * the SAR ADC engine allows sampling multiple channels at the same
366 * time. to keep it simple we're only working with one *internal*
367 * channel, which starts counting at index 0 (which means: count = 1).
368 */
369 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
370 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
371 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
372
373 /* map channel index 0 to the channel which we want to read */
374 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
375 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
376 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
377
378 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
379 channel);
380 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
381 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
382 regval);
383
384 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
385 channel);
386 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
387 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
388 regval);
389
390 if (channel == 6)
391 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
392 MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
393}
394
395static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
396 int chan, uint *val)
397{
398 int ret;
399
400 ret = meson_saradc_lock(priv);
401 if (ret)
402 return ret;
403
404 /* clear the FIFO to make sure we're not reading old values */
405 meson_saradc_clear_fifo(priv);
406
407 meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
408
409 meson_saradc_enable_channel(priv, chan);
410
411 meson_saradc_start_sample_engine(priv);
412 ret = meson_saradc_read_raw_sample(priv, chan, val);
413 meson_saradc_stop_sample_engine(priv);
414
415 meson_saradc_unlock(priv);
416
417 if (ret) {
418 printf("failed to read sample for channel %d: %d\n",
419 chan, ret);
420 return ret;
421 }
422
423 return 0;
424}
425
426static int meson_saradc_channel_data(struct udevice *dev, int channel,
427 unsigned int *data)
428{
429 struct meson_saradc_priv *priv = dev_get_priv(dev);
430
431 if (channel != priv->active_channel) {
432 pr_err("Requested channel is not active!");
433 return -EINVAL;
434 }
435
436 return meson_saradc_get_sample(priv, channel, data);
437}
438
439enum meson_saradc_chan7_mux_sel {
440 CHAN7_MUX_VSS = 0x0,
441 CHAN7_MUX_VDD_DIV4 = 0x1,
442 CHAN7_MUX_VDD_DIV2 = 0x2,
443 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
444 CHAN7_MUX_VDD = 0x4,
445 CHAN7_MUX_CH7_INPUT = 0x7,
446};
447
448static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
449 enum meson_saradc_chan7_mux_sel sel)
450{
451 u32 regval;
452
453 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
454 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
455 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
456
457 udelay(20);
458}
459
460static int meson_saradc_calib(struct meson_saradc_priv *priv)
461{
462 uint nominal0, nominal1, value0, value1;
463 int ret;
464
465 /* use points 25% and 75% for calibration */
466 nominal0 = (1 << priv->data->num_bits) / 4;
467 nominal1 = (1 << priv->data->num_bits) * 3 / 4;
468
469 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
470 udelay(20);
471 ret = meson_saradc_get_sample(priv, 7, &value0);
472 if (ret < 0)
473 goto out;
474
475 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
476 udelay(20);
477 ret = meson_saradc_get_sample(priv, 7, &value1);
478 if (ret < 0)
479 goto out;
480
481 if (value1 <= value0) {
482 ret = -EINVAL;
483 goto out;
484 }
485
486 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
487 value1 - value0);
488 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
489 MILLION);
490 ret = 0;
491out:
492 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
493
494 return ret;
495}
496
497static int meson_saradc_init(struct meson_saradc_priv *priv)
498{
499 uint regval;
500 int ret, i;
501
502 priv->calibscale = MILLION;
503
504 /*
505 * make sure we start at CH7 input since the other muxes are only used
506 * for internal calibration.
507 */
508 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
509
510 /*
511 * leave sampling delay and the input clocks as configured by
512 * BL30 to make sure BL30 gets the values it expects when
513 * reading the temperature sensor.
514 */
515 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
81b1c475
MS		 516 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) {
517 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
518 if (regval & MESON_SAR_ADC_REG3_ADC_EN)
519 return 0;
520 }
59beb238
NA		 521
522 meson_saradc_stop_sample_engine(priv);
523
524 /* update the channel 6 MUX to select the temperature sensor */
525 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
526 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
527 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
528
529 /* disable all channels by default */
530 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
531
532 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
533 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
534 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
535 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
536 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
537
538 /* delay between two samples = (10+1) * 1uS */
539 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
540 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
541 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
542 10));
543 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
544 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
545 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
546 0));
547
548 /* delay between two samples = (10+1) * 1uS */
549 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
550 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
551 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
552 10));
553 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
554 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
555 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
556 1));
557
558 /*
559 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
560 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
561 */
562 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
563 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
564 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
565 regval);
566 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
567 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
568 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
569 regval);
570
571 /*
572 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
573 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
574 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
575 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
576 */
577 regval = 0;
578 for (i = 2; i <= 7; i++)
579 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
580 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
581 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
582 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
583
584 ret = meson_saradc_lock(priv);
585 if (ret)
586 return ret;
587
588#if CONFIG_IS_ENABLED(CLK)
589 ret = clk_enable(&priv->core_clk);
590 if (ret)
591 return ret;
592#endif
593
594 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
595 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
596 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
597
598 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
599 MESON_SAR_ADC_REG11_BANDGAP_EN,
600 MESON_SAR_ADC_REG11_BANDGAP_EN);
601
602 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
603 MESON_SAR_ADC_REG3_ADC_EN,
604 MESON_SAR_ADC_REG3_ADC_EN);
605
606 udelay(5);
607
608#if CONFIG_IS_ENABLED(CLK)
609 ret = clk_enable(&priv->adc_clk);
610 if (ret)
611 return ret;
612#endif
613
614 meson_saradc_unlock(priv);
615
616 ret = meson_saradc_calib(priv);
617 if (ret) {
618 printf("calibration failed\n");
619 return -EIO;
620 }
621
622 return 0;
623}
624
625static int meson_saradc_start_channel(struct udevice *dev, int channel)
626{
627 struct meson_saradc_priv *priv = dev_get_priv(dev);
628
629 if (channel < 0 || channel >= NUM_CHANNELS) {
630 printf("Requested channel is invalid!");
631 return -EINVAL;
632 }
633
634 if (!priv->initialized) {
635 int ret;
636
637 ret = meson_saradc_init(priv);
638 if (ret)
639 return ret;
640
641 priv->initialized = true;
642 }
643
644 priv->active_channel = channel;
645
646 return 0;
647}
648
649static int meson_saradc_stop(struct udevice *dev)
650{
651 struct meson_saradc_priv *priv = dev_get_priv(dev);
652
653 priv->active_channel = -1;
654
655 return 0;
656}
657
658static int meson_saradc_probe(struct udevice *dev)
659{
97ab802a 660 struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
59beb238 661 struct meson_saradc_priv *priv = dev_get_priv(dev);
97ab802a
MS		 662 struct udevice *vref;
663 int vref_uv;
59beb238
NA		 664 int ret;
665
0421c980 666 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
59beb238
NA		 667 if (ret)
668 return ret;
669
670#if CONFIG_IS_ENABLED(CLK)
671 ret = clk_get_by_name(dev, "core", &priv->core_clk);
672 if (ret)
673 return ret;
674
675 ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
676 if (ret)
677 return ret;
678#endif
679
680 priv->active_channel = -1;
681
97ab802a
MS		 682 ret = device_get_supply_regulator(dev, "vref-supply", &vref);
683 if (ret) {
684 printf("can't get vref-supply: %d\n", ret);
685 return ret;
686 }
687
688 vref_uv = regulator_get_value(vref);
689 if (vref_uv < 0) {
690 printf("can't get vref-supply value: %d\n", vref_uv);
691 return vref_uv;
692 }
693
694 /* VDD supplied by common vref pin */
695 uc_pdata->vdd_supply = vref;
696 uc_pdata->vdd_microvolts = vref_uv;
697 uc_pdata->vss_microvolts = 0;
698
59beb238
NA		 699 return 0;
700}
701
d1998a9f 702int meson_saradc_of_to_plat(struct udevice *dev)
59beb238 703{
caa4daa2 704 struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
59beb238
NA		 705 struct meson_saradc_priv *priv = dev_get_priv(dev);
706
707 priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
708
709 uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
710 uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
711 uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
712 uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
713
714 return 0;
715}
716
717static const struct adc_ops meson_saradc_ops = {
718 .start_channel = meson_saradc_start_channel,
719 .channel_data = meson_saradc_channel_data,
720 .stop = meson_saradc_stop,
721};
722
723static const struct meson_saradc_data gxbb_saradc_data = {
724 .num_bits = 10,
725};
726
727static const struct meson_saradc_data gxl_saradc_data = {
728 .num_bits = 12,
729};
730
731static const struct udevice_id meson_saradc_ids[] = {
732 { .compatible = "amlogic,meson-gxbb-saradc",
733 .data = (ulong)&gxbb_saradc_data },
734 { .compatible = "amlogic,meson-gxl-saradc",
735 .data = (ulong)&gxl_saradc_data },
736 { .compatible = "amlogic,meson-gxm-saradc",
737 .data = (ulong)&gxl_saradc_data },
220992bd
MS		 738 { .compatible = "amlogic,meson-g12a-saradc",
739 .data = (ulong)&gxl_saradc_data },
8a4a73f4
VB		 740 { .compatible = "amlogic,meson-axg-saradc",
741 .data = (ulong)&gxl_saradc_data },
59beb238
NA		 742 { }
743};
744
745U_BOOT_DRIVER(meson_saradc) = {
746 .name = "meson_saradc",
747 .id = UCLASS_ADC,
748 .of_match = meson_saradc_ids,
749 .ops = &meson_saradc_ops,
750 .probe = meson_saradc_probe,
d1998a9f 751 .of_to_plat = meson_saradc_of_to_plat,
41575d8e 752 .priv_auto = sizeof(struct meson_saradc_priv),
59beb238 753};
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