[u-boot.git] / drivers / spi / zynq_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 Xilinx, Inc.
 * (C) Copyright 2015 Jagan Teki <[email protected]>
 *
 * Xilinx Zynq PS SPI controller driver (master mode only)
 */

#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <time.h>
#include <clk.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
#define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */

#define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
#define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
#define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */

#define ZYNQ_SPI_FIFO_DEPTH		128
#define ZYNQ_SPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */

/* zynq spi register set */
struct zynq_spi_regs {
	u32 cr;		/* 0x00 */
	u32 isr;	/* 0x04 */
	u32 ier;	/* 0x08 */
	u32 idr;	/* 0x0C */
	u32 imr;	/* 0x10 */
	u32 enr;	/* 0x14 */
	u32 dr;		/* 0x18 */
	u32 txdr;	/* 0x1C */
	u32 rxdr;	/* 0x20 */
};


/* zynq spi platform data */
struct zynq_spi_plat {
	struct zynq_spi_regs *regs;
	u32 frequency;		/* input frequency */
	u32 speed_hz;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

/* zynq spi priv */
struct zynq_spi_priv {
	struct zynq_spi_regs *regs;
	u8 cs;
	u8 mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 fifo_depth;
	u32 freq;		/* required frequency */
};

static int zynq_spi_of_to_plat(struct udevice *bus)
{
	struct zynq_spi_plat *plat = bus->plat;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->regs = dev_read_addr_ptr(bus);

	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	plat->activate_delay_us = fdtdec_get_int(blob, node,
						 "spi-activate-delay", 0);

	return 0;
}

static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	/* Disable SPI */
	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	/* Disable Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);

	/* Clear RX FIFO */
	while (readl(&regs->isr) &
			ZYNQ_SPI_IXR_RXNEMPTY_MASK)
		readl(&regs->rxdr);

	/* Clear Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);

	/* Manual slave select and Auto start */
	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
		ZYNQ_SPI_CR_MSTREN_MASK;
	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
	writel(confr, &regs->cr);

	/* Enable SPI */
	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
}

static int zynq_spi_probe(struct udevice *bus)
{
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct clk clk;
	unsigned long clock;
	int ret;

	priv->regs = plat->regs;
	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;

	ret = clk_get_by_name(bus, "ref_clk", &clk);
	if (ret < 0) {
		dev_err(bus, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(bus, "failed to get rate\n");
		return clock;
	}

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}

	/* init the zynq spi hw */
	zynq_spi_init_hw(priv);

	plat->frequency = clock;
	plat->speed_hz = plat->frequency / 2;

	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);

	return 0;
}

static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_plat *plat = bus->plat;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 cr;

	/* If it's too soon to do another transaction, wait */
	if (plat->deactivate_delay_us && priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < plat->deactivate_delay_us)
			udelay(plat->deactivate_delay_us - delay_us);
	}

	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
	cr = readl(&regs->cr);
	/*
	 * CS cal logic: CS[13:10]
	 * xxx0	- cs0
	 * xx01	- cs1
	 * x011 - cs2
	 */
	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
	writel(cr, &regs->cr);

	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_plat *plat = bus->plat;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

static int zynq_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	return 0;
}

static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	u32 len = bitlen / 8;
	u32 tx_len = len, rx_len = len, tx_tvl;
	const u8 *tx_buf = dout;
	u8 *rx_buf = din, buf;
	u32 ts, status;

	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
	      dev_seq(bus), slave_plat->cs, bitlen, len, flags);

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	priv->cs = slave_plat->cs;
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev);

	while (rx_len > 0) {
		/* Write the data into TX FIFO - tx threshold is fifo_depth */
		tx_tvl = 0;
		while ((tx_tvl < priv->fifo_depth) && tx_len) {
			if (tx_buf)
				buf = *tx_buf++;
			else
				buf = 0;
			writel(buf, &regs->txdr);
			tx_len--;
			tx_tvl++;
		}

		/* Check TX FIFO completion */
		ts = get_timer(0);
		status = readl(&regs->isr);
		while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
			if (get_timer(ts) > ZYNQ_SPI_WAIT) {
				printf("spi_xfer: Timeout! TX FIFO not full\n");
				return -1;
			}
			status = readl(&regs->isr);
		}

		/* Read the data from RX FIFO */
		status = readl(&regs->isr);
		while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
			buf = readl(&regs->rxdr);
			if (rx_buf)
				*rx_buf++ = buf;
			status = readl(&regs->isr);
			rx_len--;
		}
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	return 0;
}

static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
	struct zynq_spi_plat *plat = bus->plat;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;
	u8 baud_rate_val = 0;

	if (speed > plat->frequency)
		speed = plat->frequency;

	/* Set the clock frequency */
	confr = readl(&regs->cr);
	if (speed == 0) {
		/* Set baudrate x8, if the freq is 0 */
		baud_rate_val = 0x2;
	} else if (plat->speed_hz != speed) {
		while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
				((plat->frequency /
				(2 << baud_rate_val)) > speed))
			baud_rate_val++;
		plat->speed_hz = speed / (2 << baud_rate_val);
	}
	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);

	writel(confr, &regs->cr);
	priv->freq = speed;

	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
	      priv->regs, priv->freq);

	return 0;
}

static int zynq_spi_set_mode(struct udevice *bus, uint mode)
{
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;

	/* Set the SPI Clock phase and polarities */
	confr = readl(&regs->cr);
	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);

	if (mode & SPI_CPHA)
		confr |= ZYNQ_SPI_CR_CPHA_MASK;
	if (mode & SPI_CPOL)
		confr |= ZYNQ_SPI_CR_CPOL_MASK;

	writel(confr, &regs->cr);
	priv->mode = mode;

	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops zynq_spi_ops = {
	.claim_bus	= zynq_spi_claim_bus,
	.release_bus	= zynq_spi_release_bus,
	.xfer		= zynq_spi_xfer,
	.set_speed	= zynq_spi_set_speed,
	.set_mode	= zynq_spi_set_mode,
};

static const struct udevice_id zynq_spi_ids[] = {
	{ .compatible = "xlnx,zynq-spi-r1p6" },
	{ .compatible = "cdns,spi-r1p6" },
	{ }
};

U_BOOT_DRIVER(zynq_spi) = {
	.name	= "zynq_spi",
	.id	= UCLASS_SPI,
	.of_match = zynq_spi_ids,
	.ops	= &zynq_spi_ops,
	.of_to_plat = zynq_spi_of_to_plat,
	.plat_auto	= sizeof(struct zynq_spi_plat),
	.priv_auto	= sizeof(struct zynq_spi_priv),
	.probe	= zynq_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1465d055	2	/*
86e99b98	3	* (C) Copyright 2013 Xilinx, Inc.
b1c82da2	4	* (C) Copyright 2015 Jagan Teki <[email protected]>
1465d055 JT	5	*
1465d055 JT	6	* Xilinx Zynq PS SPI controller driver (master mode only)
1465d055 JT	7	*/
1465d055 JT	8
1465d055	9	#include <common.h>
b1c82da2	10	#include <dm.h>
b79a7030	11	#include <dm/device_compat.h>
f7ae49fc	12	#include <log.h>
1465d055 JT	13	#include <malloc.h>
1465d055 JT	14	#include <spi.h>
1045315d	15	#include <time.h>
b79a7030	16	#include <clk.h>
1465d055	17	#include <asm/io.h>
cd93d625	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
1465d055	20
cdc9dd07 JT	21	DECLARE_GLOBAL_DATA_PTR;
cdc9dd07 JT	22
1465d055	23	/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
736b4df1 JT	24	#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
736b4df1 JT	25	#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
9cf2ffb3 JT	26	#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
9cf2ffb3 JT	27	#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
736b4df1 JT	28	#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
	29	#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
	30	#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
	31	#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
	32	#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
9cf2ffb3	33	#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
736b4df1	34	#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
1465d055	35
46ab8a6a JT	36	#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
	37	#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
	38	#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
	39
1465d055	40	#define ZYNQ_SPI_FIFO_DEPTH 128
f44bd3bc	41	#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
1465d055 JT	42
	43	/* zynq spi register set */
	44	struct zynq_spi_regs {
	45	u32 cr; /* 0x00 */
	46	u32 isr; /* 0x04 */
	47	u32 ier; /* 0x08 */
	48	u32 idr; /* 0x0C */
	49	u32 imr; /* 0x10 */
	50	u32 enr; /* 0x14 */
	51	u32 dr; /* 0x18 */
	52	u32 txdr; /* 0x1C */
	53	u32 rxdr; /* 0x20 */
	54	};
	55
b1c82da2 JT	56
b1c82da2 JT	57	/* zynq spi platform data */
8a8d24bd	58	struct zynq_spi_plat {
b1c82da2 JT	59	struct zynq_spi_regs *regs;
b1c82da2 JT	60	u32 frequency; /* input frequency */
1465d055	61	u32 speed_hz;
ac6991fb MF	62	uint deactivate_delay_us; /* Delay to wait after deactivate */
ac6991fb MF	63	uint activate_delay_us; /* Delay to wait after activate */
1465d055 JT	64	};
1465d055 JT	65
b1c82da2 JT	66	/* zynq spi priv */
	67	struct zynq_spi_priv {
	68	struct zynq_spi_regs *regs;
19126998	69	u8 cs;
b1c82da2	70	u8 mode;
ac6991fb	71	ulong last_transaction_us; /* Time of last transaction end */
b1c82da2 JT	72	u8 fifo_depth;
	73	u32 freq; /* required frequency */
	74	};
1465d055	75
d1998a9f	76	static int zynq_spi_of_to_plat(struct udevice *bus)
1465d055	77	{
8a8d24bd	78	struct zynq_spi_plat *plat = bus->plat;
cdc9dd07	79	const void *blob = gd->fdt_blob;
e160f7d4	80	int node = dev_of_offset(bus);
cdc9dd07	81
8613c8d8	82	plat->regs = dev_read_addr_ptr(bus);
b1c82da2	83
ac6991fb MF	84	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
	85	"spi-deactivate-delay", 0);
	86	plat->activate_delay_us = fdtdec_get_int(blob, node,
	87	"spi-activate-delay", 0);
cdc9dd07	88
b1c82da2 JT	89	return 0;
	90	}
	91
	92	static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
	93	{
	94	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	95	u32 confr;
	96
	97	/* Disable SPI */
5f647c22 MS	98	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	99	writel(~confr, &regs->enr);
1465d055 JT	100
1465d055 JT	101	/* Disable Interrupts */
b1c82da2	102	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
1465d055 JT	103
1465d055 JT	104	/* Clear RX FIFO */
b1c82da2	105	while (readl(&regs->isr) &
1465d055	106	ZYNQ_SPI_IXR_RXNEMPTY_MASK)
b1c82da2	107	readl(&regs->rxdr);
1465d055 JT	108
1465d055 JT	109	/* Clear Interrupts */
b1c82da2	110	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
1465d055 JT	111
	112	/* Manual slave select and Auto start */
	113	confr = ZYNQ_SPI_CR_MCS_MASK \| ZYNQ_SPI_CR_CS_MASK \|
	114	ZYNQ_SPI_CR_MSTREN_MASK;
	115	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
b1c82da2	116	writel(confr, &regs->cr);
1465d055 JT	117
1465d055 JT	118	/* Enable SPI */
b1c82da2	119	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055 JT	120	}
1465d055 JT	121
b1c82da2	122	static int zynq_spi_probe(struct udevice *bus)
1465d055	123	{
8a8d24bd	124	struct zynq_spi_plat *plat = dev_get_plat(bus);
b1c82da2	125	struct zynq_spi_priv *priv = dev_get_priv(bus);
b79a7030 KR	126	struct clk clk;
	127	unsigned long clock;
	128	int ret;
b1c82da2 JT	129
	130	priv->regs = plat->regs;
	131	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
	132
b79a7030 KR	133	ret = clk_get_by_name(bus, "ref_clk", &clk);
	134	if (ret < 0) {
	135	dev_err(bus, "failed to get clock\n");
	136	return ret;
	137	}
	138
	139	clock = clk_get_rate(&clk);
	140	if (IS_ERR_VALUE(clock)) {
	141	dev_err(bus, "failed to get rate\n");
	142	return clock;
	143	}
	144
	145	ret = clk_enable(&clk);
	146	if (ret && ret != -ENOSYS) {
	147	dev_err(bus, "failed to enable clock\n");
	148	return ret;
	149	}
	150
b1c82da2 JT	151	/* init the zynq spi hw */
	152	zynq_spi_init_hw(priv);
	153
b79a7030 KR	154	plat->frequency = clock;
	155	plat->speed_hz = plat->frequency / 2;
	156
	157	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
	158
b1c82da2	159	return 0;
1465d055 JT	160	}
1465d055 JT	161
19126998	162	static void spi_cs_activate(struct udevice *dev)
1465d055	163	{
b1c82da2	164	struct udevice *bus = dev->parent;
8a8d24bd	165	struct zynq_spi_plat *plat = bus->plat;
b1c82da2 JT	166	struct zynq_spi_priv *priv = dev_get_priv(bus);
b1c82da2 JT	167	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	168	u32 cr;
1465d055 JT	169
ac6991fb MF	170	/* If it's too soon to do another transaction, wait */
	171	if (plat->deactivate_delay_us && priv->last_transaction_us) {
	172	ulong delay_us; /* The delay completed so far */
	173	delay_us = timer_get_us() - priv->last_transaction_us;
	174	if (delay_us < plat->deactivate_delay_us)
	175	udelay(plat->deactivate_delay_us - delay_us);
	176	}
	177
b1c82da2 JT	178	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
b1c82da2 JT	179	cr = readl(&regs->cr);
1465d055 JT	180	/*
	181	* CS cal logic: CS[13:10]
	182	* xxx0 - cs0
	183	* xx01 - cs1
	184	* x011 - cs2
	185	*/
19126998	186	cr \|= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
b1c82da2	187	writel(cr, &regs->cr);
ac6991fb MF	188
	189	if (plat->activate_delay_us)
	190	udelay(plat->activate_delay_us);
1465d055 JT	191	}
1465d055 JT	192
b1c82da2	193	static void spi_cs_deactivate(struct udevice *dev)
1465d055	194	{
b1c82da2	195	struct udevice *bus = dev->parent;
8a8d24bd	196	struct zynq_spi_plat *plat = bus->plat;
b1c82da2 JT	197	struct zynq_spi_priv *priv = dev_get_priv(bus);
b1c82da2 JT	198	struct zynq_spi_regs *regs = priv->regs;
1465d055	199
b1c82da2	200	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
ac6991fb MF	201
	202	/* Remember time of this transaction so we can honour the bus delay */
	203	if (plat->deactivate_delay_us)
	204	priv->last_transaction_us = timer_get_us();
1465d055 JT	205	}
1465d055 JT	206
b1c82da2	207	static int zynq_spi_claim_bus(struct udevice *dev)
1465d055	208	{
b1c82da2 JT	209	struct udevice *bus = dev->parent;
	210	struct zynq_spi_priv *priv = dev_get_priv(bus);
	211	struct zynq_spi_regs *regs = priv->regs;
1465d055	212
b1c82da2	213	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055	214
b1c82da2	215	return 0;
1465d055 JT	216	}
1465d055 JT	217
b1c82da2	218	static int zynq_spi_release_bus(struct udevice *dev)
1465d055	219	{
b1c82da2 JT	220	struct udevice *bus = dev->parent;
	221	struct zynq_spi_priv *priv = dev_get_priv(bus);
	222	struct zynq_spi_regs *regs = priv->regs;
5f647c22	223	u32 confr;
1465d055	224
5f647c22 MS	225	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	226	writel(~confr, &regs->enr);
1465d055 JT	227
	228	return 0;
	229	}
	230
b1c82da2 JT	231	static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
b1c82da2 JT	232	const void dout, void din, unsigned long flags)
1465d055	233	{
b1c82da2 JT	234	struct udevice *bus = dev->parent;
	235	struct zynq_spi_priv *priv = dev_get_priv(bus);
	236	struct zynq_spi_regs *regs = priv->regs;
8a8d24bd	237	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
1465d055 JT	238	u32 len = bitlen / 8;
	239	u32 tx_len = len, rx_len = len, tx_tvl;
	240	const u8 *tx_buf = dout;
	241	u8 *rx_buf = din, buf;
	242	u32 ts, status;
	243
	244	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
8b85dfc6	245	dev_seq(bus), slave_plat->cs, bitlen, len, flags);
1465d055	246
1465d055 JT	247	if (bitlen % 8) {
	248	debug("spi_xfer: Non byte aligned SPI transfer\n");
	249	return -1;
	250	}
	251
19126998	252	priv->cs = slave_plat->cs;
1465d055	253	if (flags & SPI_XFER_BEGIN)
19126998	254	spi_cs_activate(dev);
1465d055 JT	255
	256	while (rx_len > 0) {
	257	/* Write the data into TX FIFO - tx threshold is fifo_depth */
	258	tx_tvl = 0;
b1c82da2	259	while ((tx_tvl < priv->fifo_depth) && tx_len) {
1465d055 JT	260	if (tx_buf)
	261	buf = *tx_buf++;
	262	else
	263	buf = 0;
b1c82da2	264	writel(buf, &regs->txdr);
1465d055 JT	265	tx_len--;
	266	tx_tvl++;
	267	}
	268
	269	/* Check TX FIFO completion */
	270	ts = get_timer(0);
b1c82da2	271	status = readl(&regs->isr);
1465d055	272	while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
f44bd3bc	273	if (get_timer(ts) > ZYNQ_SPI_WAIT) {
1465d055 JT	274	printf("spi_xfer: Timeout! TX FIFO not full\n");
	275	return -1;
	276	}
b1c82da2	277	status = readl(&regs->isr);
1465d055 JT	278	}
	279
	280	/* Read the data from RX FIFO */
b1c82da2	281	status = readl(&regs->isr);
d2998286	282	while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
b1c82da2	283	buf = readl(&regs->rxdr);
1465d055 JT	284	if (rx_buf)
1465d055 JT	285	*rx_buf++ = buf;
b1c82da2	286	status = readl(&regs->isr);
1465d055 JT	287	rx_len--;
	288	}
	289	}
	290
	291	if (flags & SPI_XFER_END)
b1c82da2 JT	292	spi_cs_deactivate(dev);
	293
	294	return 0;
	295	}
	296
	297	static int zynq_spi_set_speed(struct udevice *bus, uint speed)
	298	{
8a8d24bd	299	struct zynq_spi_plat *plat = bus->plat;
b1c82da2 JT	300	struct zynq_spi_priv *priv = dev_get_priv(bus);
	301	struct zynq_spi_regs *regs = priv->regs;
	302	uint32_t confr;
	303	u8 baud_rate_val = 0;
	304
	305	if (speed > plat->frequency)
	306	speed = plat->frequency;
	307
	308	/* Set the clock frequency */
	309	confr = readl(&regs->cr);
	310	if (speed == 0) {
	311	/* Set baudrate x8, if the freq is 0 */
	312	baud_rate_val = 0x2;
	313	} else if (plat->speed_hz != speed) {
46ab8a6a	314	while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
b1c82da2 JT	315	((plat->frequency /
	316	(2 << baud_rate_val)) > speed))
	317	baud_rate_val++;
	318	plat->speed_hz = speed / (2 << baud_rate_val);
	319	}
dda6241a	320	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
46ab8a6a	321	confr \|= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
b1c82da2 JT	322
	323	writel(confr, &regs->cr);
	324	priv->freq = speed;
	325
a22bba81 JT	326	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
a22bba81 JT	327	priv->regs, priv->freq);
b1c82da2 JT	328
	329	return 0;
	330	}
	331
	332	static int zynq_spi_set_mode(struct udevice *bus, uint mode)
	333	{
	334	struct zynq_spi_priv *priv = dev_get_priv(bus);
	335	struct zynq_spi_regs *regs = priv->regs;
	336	uint32_t confr;
	337
	338	/* Set the SPI Clock phase and polarities */
	339	confr = readl(&regs->cr);
	340	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK \| ZYNQ_SPI_CR_CPOL_MASK);
	341
a22bba81	342	if (mode & SPI_CPHA)
b1c82da2	343	confr \|= ZYNQ_SPI_CR_CPHA_MASK;
a22bba81	344	if (mode & SPI_CPOL)
b1c82da2 JT	345	confr \|= ZYNQ_SPI_CR_CPOL_MASK;
	346
	347	writel(confr, &regs->cr);
	348	priv->mode = mode;
	349
	350	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
1465d055 JT	351
	352	return 0;
	353	}
b1c82da2 JT	354
	355	static const struct dm_spi_ops zynq_spi_ops = {
	356	.claim_bus = zynq_spi_claim_bus,
	357	.release_bus = zynq_spi_release_bus,
	358	.xfer = zynq_spi_xfer,
	359	.set_speed = zynq_spi_set_speed,
	360	.set_mode = zynq_spi_set_mode,
	361	};
	362
	363	static const struct udevice_id zynq_spi_ids[] = {
40b383fa	364	{ .compatible = "xlnx,zynq-spi-r1p6" },
23ef5aea	365	{ .compatible = "cdns,spi-r1p6" },
b1c82da2 JT	366	{ }
	367	};
	368
	369	U_BOOT_DRIVER(zynq_spi) = {
	370	.name = "zynq_spi",
	371	.id = UCLASS_SPI,
	372	.of_match = zynq_spi_ids,
	373	.ops = &zynq_spi_ops,
d1998a9f	374	.of_to_plat = zynq_spi_of_to_plat,
8a8d24bd	375	.plat_auto = sizeof(struct zynq_spi_plat),
41575d8e	376	.priv_auto = sizeof(struct zynq_spi_priv),
b1c82da2 JT	377	.probe = zynq_spi_probe,
b1c82da2 JT	378	};