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Commit | Line | Data |
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89c1e2da SW |
1 | menu "Reset Controller Support" |
2 | ||
3 | config DM_RESET | |
4 | bool "Enable reset controllers using Driver Model" | |
5 | depends on DM && OF_CONTROL | |
6 | help | |
7 | Enable support for the reset controller driver class. Many hardware | |
8 | modules are equipped with a reset signal, typically driven by some | |
9 | reset controller hardware module within the chip. In U-Boot, reset | |
10 | controller drivers allow control over these reset signals. In some | |
11 | cases this API is applicable to chips outside the CPU as well, | |
12 | although driving such reset isgnals using GPIOs may be more | |
13 | appropriate in this case. | |
14 | ||
4581b717 SW |
15 | config SANDBOX_RESET |
16 | bool "Enable the sandbox reset test driver" | |
17 | depends on DM_MAILBOX && SANDBOX | |
18 | help | |
19 | Enable support for a test reset controller implementation, which | |
20 | simply accepts requests to reset various HW modules without actually | |
21 | doing anything beyond a little error checking. | |
22 | ||
584861ff PC |
23 | config STI_RESET |
24 | bool "Enable the STi reset" | |
25 | depends on ARCH_STI | |
26 | help | |
27 | Support for reset controllers on STMicroelectronics STiH407 family SoCs. | |
28 | Say Y if you want to control reset signals provided by system config | |
29 | block. | |
30 | ||
23a06416 PC |
31 | config STM32_RESET |
32 | bool "Enable the STM32 reset" | |
a7519b33 | 33 | depends on STM32 || ARCH_STM32MP |
23a06416 PC |
34 | help |
35 | Support for reset controllers on STMicroelectronics STM32 family SoCs. | |
36 | This resset driver is compatible with STM32 F4/F7 and H7 SoCs. | |
37 | ||
fe60f06d SW |
38 | config TEGRA_CAR_RESET |
39 | bool "Enable Tegra CAR-based reset driver" | |
40 | depends on TEGRA_CAR | |
41 | help | |
42 | Enable support for manipulating Tegra's on-SoC reset signals via | |
43 | direct register access to the Tegra CAR (Clock And Reset controller). | |
44 | ||
4dd99d14 SW |
45 | config TEGRA186_RESET |
46 | bool "Enable Tegra186 BPMP-based reset driver" | |
47 | depends on TEGRA186_BPMP | |
48 | help | |
49 | Enable support for manipulating Tegra's on-SoC reset signals via IPC | |
50 | requests to the BPMP (Boot and Power Management Processor). | |
51 | ||
65c8a798 AD |
52 | config RESET_TI_SCI |
53 | bool "TI System Control Interface (TI SCI) reset driver" | |
54 | depends on DM_RESET && TI_SCI_PROTOCOL | |
55 | help | |
56 | This enables the reset driver support over TI System Control Interface | |
57 | available on some new TI's SoCs. If you wish to use reset resources | |
58 | managed by the TI System Controller, say Y here. Otherwise, say N. | |
59 | ||
18393f70 ÁFR |
60 | config RESET_BCM6345 |
61 | bool "Reset controller driver for BCM6345" | |
62 | depends on DM_RESET && ARCH_BMIPS | |
63 | help | |
64 | Support reset controller on BCM6345. | |
65 | ||
4fb96c48 MY |
66 | config RESET_UNIPHIER |
67 | bool "Reset controller driver for UniPhier SoCs" | |
68 | depends on ARCH_UNIPHIER | |
69 | default y | |
70 | help | |
71 | Support for reset controllers on UniPhier SoCs. | |
72 | Say Y if you want to control reset signals provided by System Control | |
73 | block, Media I/O block, Peripheral Block. | |
74 | ||
858d4976 | 75 | config AST2500_RESET |
76 | bool "Reset controller driver for AST2500 SoCs" | |
77 | depends on DM_RESET && WDT_ASPEED | |
78 | default y if ASPEED_AST2500 | |
79 | help | |
80 | Support for reset controller on AST2500 SoC. This controller uses | |
81 | watchdog to reset different peripherals and thus only supports | |
82 | resets that are supported by watchdog. The main limitation though | |
83 | is that some reset signals, like I2C or MISC reset multiple devices. | |
84 | ||
760188c1 EZ |
85 | config RESET_ROCKCHIP |
86 | bool "Reset controller driver for Rockchip SoCs" | |
87 | depends on DM_RESET && ARCH_ROCKCHIP && CLK | |
88 | default y | |
89 | help | |
90 | Support for reset controller on rockchip SoC. The main limitation | |
91 | though is that some reset signals, like I2C or MISC reset multiple | |
92 | devices. | |
93 | ||
20367bb5 NA |
94 | config RESET_MESON |
95 | bool "Reset controller driver for Amlogic Meson SoCs" | |
96 | depends on DM_RESET && ARCH_MESON | |
97 | imply REGMAP | |
98 | default y | |
99 | help | |
100 | Support for reset controller on Amlogic Meson SoC. | |
101 | ||
2ac71882 DN |
102 | config RESET_SOCFPGA |
103 | bool "Reset controller driver for SoCFPGA" | |
104 | depends on DM_RESET && ARCH_SOCFPGA | |
105 | default y | |
106 | help | |
107 | Support for reset controller on SoCFPGA platform. | |
108 | ||
3e066bca WG |
109 | config RESET_MEDIATEK |
110 | bool "Reset controller driver for MediaTek SoCs" | |
111 | depends on DM_RESET && ARCH_MEDIATEK && CLK | |
112 | default y | |
113 | help | |
114 | Support for reset controller on MediaTek SoCs. | |
115 | ||
99ba4308 JT |
116 | config RESET_SUNXI |
117 | bool "RESET support for Allwinner SoCs" | |
118 | depends on DM_RESET && ARCH_SUNXI | |
119 | default y | |
120 | help | |
121 | This enables support for common reset driver for | |
122 | Allwinner SoCs. | |
123 | ||
f5e6c168 SG |
124 | config RESET_HISILICON |
125 | bool "Reset controller driver for HiSilicon SoCs" | |
126 | depends on DM_RESET | |
127 | help | |
128 | Support for reset controller on HiSilicon SoCs. | |
129 | ||
6300dc4c PW |
130 | config RESET_IMX7 |
131 | bool "i.MX7/8 Reset Driver" | |
132 | depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M) | |
133 | default y | |
134 | help | |
135 | Support for reset controller on i.MX7/8 SoCs. | |
136 | ||
89c1e2da | 137 | endmenu |