[u-boot.git] / drivers / mmc / sdhci-cadence.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <sdhci.h>

/* HRS - Host Register Set (specific to Cadence) */
#define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
#define   SDHCI_CDNS_HRS04_ACK			BIT(26)
#define   SDHCI_CDNS_HRS04_RD			BIT(25)
#define   SDHCI_CDNS_HRS04_WR			BIT(24)
#define   SDHCI_CDNS_HRS04_RDATA		GENMASK(23, 16)
#define   SDHCI_CDNS_HRS04_WDATA		GENMASK(15, 8)
#define   SDHCI_CDNS_HRS04_ADDR			GENMASK(5, 0)

#define SDHCI_CDNS_HRS06		0x18		/* eMMC control */
#define   SDHCI_CDNS_HRS06_TUNE_UP		BIT(15)
#define   SDHCI_CDNS_HRS06_TUNE			GENMASK(13, 8)
#define   SDHCI_CDNS_HRS06_MODE			GENMASK(2, 0)
#define   SDHCI_CDNS_HRS06_MODE_SD		0x0
#define   SDHCI_CDNS_HRS06_MODE_MMC_SDR		0x2
#define   SDHCI_CDNS_HRS06_MODE_MMC_DDR		0x3
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS200	0x4
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400	0x5
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES	0x6

/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE		0x200

/* PHY */
#define SDHCI_CDNS_PHY_DLY_SD_HS	0x00
#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT	0x01
#define SDHCI_CDNS_PHY_DLY_UHS_SDR12	0x02
#define SDHCI_CDNS_PHY_DLY_UHS_SDR25	0x03
#define SDHCI_CDNS_PHY_DLY_UHS_SDR50	0x04
#define SDHCI_CDNS_PHY_DLY_UHS_DDR50	0x05
#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY	0x06
#define SDHCI_CDNS_PHY_DLY_EMMC_SDR	0x07
#define SDHCI_CDNS_PHY_DLY_EMMC_DDR	0x08
#define SDHCI_CDNS_PHY_DLY_SDCLK	0x0b
#define SDHCI_CDNS_PHY_DLY_HSMMC	0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE	0x0d

/*
 * The tuned val register is 6 bit-wide, but not the whole of the range is
 * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
 * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
 */
#define SDHCI_CDNS_MAX_TUNING_LOOP	40

struct sdhci_cdns_plat {
	struct mmc_config cfg;
	struct mmc mmc;
	void __iomem *hrs_addr;
};

struct sdhci_cdns_phy_cfg {
	const char *property;
	u8 addr;
};

static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};

static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
				    u8 addr, u8 data)
{
	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
	u32 tmp;
	int ret;

	tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
	      FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
	writel(tmp, reg);

	tmp |= SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
	if (ret)
		return ret;

	tmp &= ~SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	return 0;
}

static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
				const void *fdt, int nodeoffset)
{
	const fdt32_t *prop;
	int ret, i;

	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
		prop = fdt_getprop(fdt, nodeoffset,
				   sdhci_cdns_phy_cfgs[i].property, NULL);
		if (!prop)
			continue;

		ret = sdhci_cdns_write_phy_reg(plat,
					       sdhci_cdns_phy_cfgs[i].addr,
					       fdt32_to_cpu(*prop));
		if (ret)
			return ret;
	}

	return 0;
}

static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
{
	struct mmc *mmc = host->mmc;
	struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
	unsigned int clock = mmc->clock;
	u32 mode, tmp;

	/*
	 * REVISIT:
	 * The mode should be decided by MMC_TIMING_* like Linux, but
	 * U-Boot does not support timing.  Use the clock frequency instead.
	 */
	if (clock <= 26000000) {
		mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
	} else if (clock <= 52000000) {
		if (mmc->ddr_mode)
			mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
		else
			mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
	} else {
		if (mmc->ddr_mode)
			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
		else
			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
	}

	tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
	tmp &= ~SDHCI_CDNS_HRS06_MODE;
	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
	writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
}

static const struct sdhci_ops sdhci_cdns_ops = {
	.set_control_reg = sdhci_cdns_set_control_reg,
};

static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
				   unsigned int val)
{
	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
	u32 tmp;

	if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
		return -EINVAL;

	tmp = readl(reg);
	tmp &= ~SDHCI_CDNS_HRS06_TUNE;
	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
	tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
	writel(tmp, reg);

	return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
				  1);
}

static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
						    unsigned int opcode)
{
	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	struct mmc *mmc = &plat->mmc;
	int cur_streak = 0;
	int max_streak = 0;
	int end_of_streak = 0;
	int i;

	/*
	 * This handler only implements the eMMC tuning that is specific to
	 * this controller.  The tuning for SD timing should be handled by the
	 * SDHCI core.
	 */
	if (!IS_MMC(mmc))
		return -ENOTSUPP;

	if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
		return -EINVAL;

	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
		if (sdhci_cdns_set_tune_val(plat, i) ||
		    mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
			cur_streak = 0;
		} else { /* good */
			cur_streak++;
			if (cur_streak > max_streak) {
				max_streak = cur_streak;
				end_of_streak = i;
			}
		}
	}

	if (!max_streak) {
		dev_err(dev, "no tuning point found\n");
		return -EIO;
	}

	return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
}

static struct dm_mmc_ops sdhci_cdns_mmc_ops;

static int sdhci_cdns_bind(struct udevice *dev)
{
	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static int sdhci_cdns_probe(struct udevice *dev)
{
	DECLARE_GLOBAL_DATA_PTR;
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	fdt_addr_t base;
	int ret;

	base = devfdt_get_addr(dev);
	if (base == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
	if (!plat->hrs_addr)
		return -ENOMEM;

	host->name = dev->name;
	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
	host->ops = &sdhci_cdns_ops;
	host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
	sdhci_cdns_mmc_ops = sdhci_ops;
#ifdef MMC_SUPPORTS_TUNING
	sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
#endif

	ret = mmc_of_parse(dev, &plat->cfg);
	if (ret)
		return ret;

	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
	if (ret)
		return ret;

	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
	if (ret)
		return ret;

	upriv->mmc = &plat->mmc;
	host->mmc = &plat->mmc;
	host->mmc->priv = host;

	return sdhci_probe(dev);
}

static const struct udevice_id sdhci_cdns_match[] = {
	{ .compatible = "socionext,uniphier-sd4hc" },
	{ .compatible = "cdns,sd4hc" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(sdhci_cdns) = {
	.name = "sdhci-cdns",
	.id = UCLASS_MMC,
	.of_match = sdhci_cdns_match,
	.bind = sdhci_cdns_bind,
	.probe = sdhci_cdns_probe,
	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
	.ops = &sdhci_cdns_mmc_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e5e7a7c2 MY	2	/*
	3	* Copyright (C) 2016 Socionext Inc.
	4	* Author: Masahiro Yamada <[email protected]>
e5e7a7c2 MY	5	*/
	6
	7	#include <common.h>
9d922450	8	#include <dm.h>
954a9631	9	#include <linux/bitfield.h>
e5e7a7c2	10	#include <linux/io.h>
0cacd6b7	11	#include <linux/iopoll.h>
e5e7a7c2	12	#include <linux/sizes.h>
b08c8c48	13	#include <linux/libfdt.h>
e5e7a7c2 MY	14	#include <mmc.h>
	15	#include <sdhci.h>
	16
	17	/* HRS - Host Register Set (specific to Cadence) */
	18	#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
	19	#define SDHCI_CDNS_HRS04_ACK BIT(26)
	20	#define SDHCI_CDNS_HRS04_RD BIT(25)
	21	#define SDHCI_CDNS_HRS04_WR BIT(24)
954a9631 MY	22	#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
	23	#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
	24	#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
e5e7a7c2	25
3d3108d4 MY	26	#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
3d3108d4 MY	27	#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
954a9631 MY	28	#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
954a9631 MY	29	#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
3d3108d4 MY	30	#define SDHCI_CDNS_HRS06_MODE_SD 0x0
	31	#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
	32	#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
	33	#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
	34	#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
	35	#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
	36
e5e7a7c2 MY	37	/* SRS - Slot Register Set (SDHCI-compatible) */
	38	#define SDHCI_CDNS_SRS_BASE 0x200
	39
	40	/* PHY */
	41	#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
	42	#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
	43	#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
	44	#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
	45	#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
	46	#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
	47	#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
	48	#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
	49	#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
0cacd6b7 MY	50	#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
	51	#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
	52	#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
e5e7a7c2	53
dd43e2a6 MY	54	/*
	55	* The tuned val register is 6 bit-wide, but not the whole of the range is
	56	* available. The range 0-42 seems to be available (then 43 wraps around to 0)
	57	* but I am not quite sure if it is official. Use only 0 to 39 for safety.
	58	*/
	59	#define SDHCI_CDNS_MAX_TUNING_LOOP 40
	60
e5e7a7c2 MY	61	struct sdhci_cdns_plat {
	62	struct mmc_config cfg;
	63	struct mmc mmc;
	64	void __iomem *hrs_addr;
	65	};
	66
0cacd6b7 MY	67	struct sdhci_cdns_phy_cfg {
	68	const char *property;
	69	u8 addr;
	70	};
	71
	72	static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	73	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	74	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	75	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	76	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	77	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	78	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	79	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	80	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	81	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	82	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	83	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
	84	};
	85
	86	static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
	87	u8 addr, u8 data)
e5e7a7c2 MY	88	{
	89	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
	90	u32 tmp;
0cacd6b7	91	int ret;
e5e7a7c2	92
954a9631 MY	93	tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) \|
954a9631 MY	94	FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
e5e7a7c2 MY	95	writel(tmp, reg);
	96
	97	tmp \|= SDHCI_CDNS_HRS04_WR;
	98	writel(tmp, reg);
	99
0cacd6b7 MY	100	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
	101	if (ret)
	102	return ret;
	103
e5e7a7c2 MY	104	tmp &= ~SDHCI_CDNS_HRS04_WR;
e5e7a7c2 MY	105	writel(tmp, reg);
0cacd6b7 MY	106
0cacd6b7 MY	107	return 0;
e5e7a7c2 MY	108	}
e5e7a7c2 MY	109
0cacd6b7 MY	110	static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
0cacd6b7 MY	111	const void *fdt, int nodeoffset)
e5e7a7c2	112	{
aae6f016	113	const fdt32_t *prop;
0cacd6b7 MY	114	int ret, i;
	115
	116	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
	117	prop = fdt_getprop(fdt, nodeoffset,
	118	sdhci_cdns_phy_cfgs[i].property, NULL);
	119	if (!prop)
	120	continue;
	121
	122	ret = sdhci_cdns_write_phy_reg(plat,
	123	sdhci_cdns_phy_cfgs[i].addr,
	124	fdt32_to_cpu(*prop));
	125	if (ret)
	126	return ret;
	127	}
	128
	129	return 0;
e5e7a7c2 MY	130	}
e5e7a7c2 MY	131
3d3108d4 MY	132	static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
	133	{
	134	struct mmc *mmc = host->mmc;
	135	struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
	136	unsigned int clock = mmc->clock;
	137	u32 mode, tmp;
	138
	139	/*
	140	* REVISIT:
	141	* The mode should be decided by MMC_TIMING_* like Linux, but
	142	* U-Boot does not support timing. Use the clock frequency instead.
	143	*/
dd43e2a6	144	if (clock <= 26000000) {
3d3108d4	145	mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
dd43e2a6	146	} else if (clock <= 52000000) {
3d3108d4 MY	147	if (mmc->ddr_mode)
	148	mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
	149	else
	150	mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
	151	} else {
dd43e2a6 MY	152	if (mmc->ddr_mode)
	153	mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
	154	else
	155	mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
3d3108d4 MY	156	}
	157
	158	tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
954a9631 MY	159	tmp &= ~SDHCI_CDNS_HRS06_MODE;
954a9631 MY	160	tmp \|= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
3d3108d4 MY	161	writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
	162	}
	163
	164	static const struct sdhci_ops sdhci_cdns_ops = {
	165	.set_control_reg = sdhci_cdns_set_control_reg,
	166	};
	167
dd43e2a6 MY	168	static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
	169	unsigned int val)
	170	{
	171	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
	172	u32 tmp;
	173
	174	if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
	175	return -EINVAL;
	176
	177	tmp = readl(reg);
	178	tmp &= ~SDHCI_CDNS_HRS06_TUNE;
	179	tmp \|= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
	180	tmp \|= SDHCI_CDNS_HRS06_TUNE_UP;
	181	writel(tmp, reg);
	182
	183	return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
	184	1);
	185	}
	186
	187	static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
	188	unsigned int opcode)
	189	{
	190	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	191	struct mmc *mmc = &plat->mmc;
	192	int cur_streak = 0;
	193	int max_streak = 0;
	194	int end_of_streak = 0;
	195	int i;
	196
	197	/*
	198	* This handler only implements the eMMC tuning that is specific to
	199	* this controller. The tuning for SD timing should be handled by the
	200	* SDHCI core.
	201	*/
	202	if (!IS_MMC(mmc))
	203	return -ENOTSUPP;
	204
	205	if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
	206	return -EINVAL;
	207
	208	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
	209	if (sdhci_cdns_set_tune_val(plat, i) \|\|
	210	mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
	211	cur_streak = 0;
	212	} else { /* good */
	213	cur_streak++;
	214	if (cur_streak > max_streak) {
	215	max_streak = cur_streak;
	216	end_of_streak = i;
	217	}
	218	}
	219	}
	220
	221	if (!max_streak) {
	222	dev_err(dev, "no tuning point found\n");
	223	return -EIO;
	224	}
	225
	226	return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
	227	}
	228
	229	static struct dm_mmc_ops sdhci_cdns_mmc_ops;
	230
e5e7a7c2 MY	231	static int sdhci_cdns_bind(struct udevice *dev)
	232	{
	233	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	234
	235	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
	236	}
	237
	238	static int sdhci_cdns_probe(struct udevice *dev)
	239	{
0cacd6b7	240	DECLARE_GLOBAL_DATA_PTR;
e5e7a7c2 MY	241	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	242	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	243	struct sdhci_host *host = dev_get_priv(dev);
	244	fdt_addr_t base;
	245	int ret;
	246
a821c4af	247	base = devfdt_get_addr(dev);
e5e7a7c2 MY	248	if (base == FDT_ADDR_T_NONE)
	249	return -EINVAL;
	250
	251	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
	252	if (!plat->hrs_addr)
	253	return -ENOMEM;
	254
	255	host->name = dev->name;
	256	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
3d3108d4	257	host->ops = &sdhci_cdns_ops;
e5e7a7c2	258	host->quirks \|= SDHCI_QUIRK_WAIT_SEND_CMD;
dd43e2a6 MY	259	sdhci_cdns_mmc_ops = sdhci_ops;
	260	#ifdef MMC_SUPPORTS_TUNING
	261	sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
	262	#endif
e5e7a7c2	263
4041bf7f MY	264	ret = mmc_of_parse(dev, &plat->cfg);
	265	if (ret)
	266	return ret;
	267
da409ccc	268	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
0cacd6b7 MY	269	if (ret)
0cacd6b7 MY	270	return ret;
e5e7a7c2 MY	271
	272	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
	273	if (ret)
	274	return ret;
	275
	276	upriv->mmc = &plat->mmc;
	277	host->mmc = &plat->mmc;
	278	host->mmc->priv = host;
	279
	280	return sdhci_probe(dev);
	281	}
	282
	283	static const struct udevice_id sdhci_cdns_match[] = {
	284	{ .compatible = "socionext,uniphier-sd4hc" },
	285	{ .compatible = "cdns,sd4hc" },
	286	{ /* sentinel */ }
	287	};
	288
	289	U_BOOT_DRIVER(sdhci_cdns) = {
	290	.name = "sdhci-cdns",
	291	.id = UCLASS_MMC,
	292	.of_match = sdhci_cdns_match,
	293	.bind = sdhci_cdns_bind,
	294	.probe = sdhci_cdns_probe,
	295	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	296	.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
dd43e2a6	297	.ops = &sdhci_cdns_mmc_ops,
e5e7a7c2	298	};